Improved Vth Stability and Gate Reliability of GaN-Based MIS-HEMTs by Employing Alternating O2 Plasma Treatment

The Vth stability and gate reliability of AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) with alternating O2 plasma treatment were systematically investigated in this article. It was found that the conduction band offset at the Al2O3/AlGaN interface was elevated to 2.4 eV, which contributed to the suppressed gate leakage current. The time-dependent dielectric breakdown (TDDB) test results showed that the ALD-Al2O3 with the alternating O2 plasma treatment had better quality and reliability. The AlGaN/GaN MIS-HEMT with the alternating O2 plasma treatment demonstrated remarkable advantages in higher Vth stability under high-temperature and long-term gate bias stress.

It is suggested that using O 3 as an oxidant during the deposition process of Al 2 O 3 can improve device performance [16], but the carbon impurity in Al 2 O 3 film increases [17].It has been reported that there is less trap state density in the O 2 plasma-assisted ALD-Al 2 O 3 film [18,19].It has been reported that adding O 2 plasma in each ALD cycle can improve Al 2 O 3 film quality [20].However, the AlGaN surface can be damaged by O 2 plasma at the initial stage of Al 2 O 3 film deposition, since the O 2 plasma can introduce deep-level traps at the AlGaN surface, which leads to device performance degradation and current collapse [21].Meanwhile, there is little research on the threshold stability and gate reliability of the ALD-Al 2 O 3 gate dielectric.We have already characterized the trap states and performance of the device with alternating O 2 plasma treatment in our previous articles [22].In this work, the V th stability and gate reliability characteristics of the AlGaN/GaN MIS-HEMTs with the alternating O 2 plasma treatment were investigated.
ally doped GaN channel layer and 5.1 µm C-doped GaN buffer layer grown using MOCVD on a 6-inch Si (111) substrate.Figure 1a shows the schematic cross-sectional illustration of the AlGaN/GaN MIS-HEMTs.The AlGaN/GaN MIS-HEMTs process began with AlN/SiNx passivation layer deposition.The device active region was isolated by mesa etching using BCl3/Ar.Then, a Ti/Al/Ni/Au metal stack with a thickness of 20/160/50/50 nm was deposited by Electron Beam Evaporation (EBE) on the source/drain region, and ohmic contact was achieved by rapid thermal process (RTP) at 780 °C for 30 s in N2 ambient.The transfer length method (TLM) test results show that the contact resistance was 1Ω•mm.The ALD-Al2O3 gate dielectrics with and without the alternating O2 plasma treatment were deposited and denoted as devices A and B, respectively.Finally, Ni/Au metal stack was deposited for the gate electrode.
The schematic process flow of depositing ALD-Al2O3 film with the alternating O2 plasma treatment is shown in Figure 1b.The entire depositing process was carried out using a Sentech SI ALD system.The deposition process consisted of a cycle of two subprocesses.Sub-process one: 4 nm ALD-Al2O3 was deposited with TMA and H2O as precursors.Sub-process two: The film deposited in sub-process one was treated with in situ O2 plasma for 2 min.The O2 gas flow was 100 sccm, gas pressure was 15 Pa, and the plasma power was 100 W. Throughout the process, the substrate temperature was maintained at 300 °C.Sub-process one and sub-process two were repeated five times.Finally, a 20 nm ALD-Al2O3 film with alternating O2 plasma treatment was obtained.It is worth noting that the deposited 4 nm ALD-Al2O3 film could serve as a protective layer on the AlGaN surface to prevent the O2 plasma damage [23].The schematic process flow of depositing ALD-Al 2 O 3 film with the alternating O 2 plasma treatment is shown in Figure 1b.The entire depositing process was carried out using a Sentech SI ALD system.The deposition process consisted of a cycle of two subprocesses.Sub-process one: 4 nm ALD-Al 2 O 3 was deposited with TMA and H 2 O as precursors.Sub-process two: The film deposited in sub-process one was treated with in situ O 2 plasma for 2 min.The O 2 gas flow was 100 sccm, gas pressure was 15 Pa, and the plasma power was 100 W. Throughout the process, the substrate temperature was maintained at 300 • C. Sub-process one and sub-process two were repeated five times.Finally, a 20 nm ALD-Al 2 O 3 film with alternating O 2 plasma treatment was obtained.It is worth noting that the deposited 4 nm ALD-Al 2 O 3 film could serve as a protective layer on the AlGaN surface to prevent the O 2 plasma damage [23].

Results and Discussion
Figure 2 exhibits the atomic force microscopy (AFM) image of the Al 2 O 3 film surface with an area of 2 µm × 2 µm.For the Al 2 O 3 film with and without the alternating O 2 plasma treatment, the root mean square (RMS) of surface roughness is 0.094 nm and 0.096 nm, respectively.This indicates that the alternating O 2 plasma treatment will not have adverse effects on the surface morphology of the Al 2 O 3 film.

Results and Discussion
Figure 2 exhibits the atomic force microscopy (AFM) image of the Al2O3 film su with an area of 2 µm × 2 µm.For the Al2O3 film with and without the alternating O2 p treatment, the root mean square (RMS) of surface roughness is 0.094 nm and 0.09 respectively.This indicates that the alternating O2 plasma treatment will not have ad effects on the surface morphology of the Al2O3 film.The gate leakage current density of the device is illustrated in Figure 3a.Th leakage density of device A significantly decreased compared with that of device B breakdown voltage of device A also improved.In order to explore the reasons for t duction of gate leakage in device A, the gate leakage mechanism was analyzed.Con ing that ALD-Al2O3 has good quality, Fowler-Nordheim (FN) tunneling was believ be the dominant gate leakage mechanism [24].The effective barrier width of the die narrowed under the forward gate voltage, and driven by the electric field in the gat lectric, electrons at the Al2O3/AlGaN interface could directly tunnel through the gat lectric.Leakage current by FN tunneling is illustrated in Figure 3b, which can be expr as where q is the charge of electrons, ℏ is the Planck's constant,  is the conduction offset at Al2O3/AlGaN interface,  is the electric field strength in Al2O3 gate diel  * is the effective electron mass in Al2O3, and 0.23  of an electron mass was us the Al2O3 film [19].The FN plots of log (/ ) versus 1/ were straight lin shown in Figure 3b, indicating that FN tunneling was the dominant gate leakage m nism under a high electric field.The linear slope was used to extract the conduction offset at the Al2O3/AlGaN interface, which were 2.40 and 1.87 eV, respectively, for d A and B. The lower gate leakage current density of device A was attributed to the h conduction band offset at the Al2O3/AlGaN interface.The conduction band offset f vice A was larger than the value of 2.2 eV in Ref.
[25].The gate leakage current density of the device is illustrated in Figure 3a.The gate leakage density of device A significantly decreased compared with that of device B. The breakdown voltage of device A also improved.In order to explore the reasons for the reduction of gate leakage in device A, the gate leakage mechanism was analyzed.Considering that ALD-Al 2 O 3 has good quality, Fowler-Nordheim (FN) tunneling was believed to be the dominant gate leakage mechanism [24].The effective barrier width of the dielectric narrowed under the forward gate voltage, and driven by the electric field in the gate dielectric, electrons at the Al 2 O 3 /AlGaN interface could directly tunnel through the gate dielectric.Leakage current by FN tunneling is illustrated in Figure 3b, which can be expressed as where q is the charge of electrons, ℏ is the Planck's constant, φ ox is the conduction band offset at Al 2 O 3 /AlGaN interface, E ox is the electric field strength in Al 2 O 3 gate dielectric, m * is the effective electron mass in Al 2 O 3 , and 0.23 m 0 of an electron mass was used for the Al 2 O 3 film [19].The FN plots of log J/E 2 ox versus 1/E ox were straight lines, as shown in Figure 3b, indicating that FN tunneling was the dominant gate leakage mechanism under a high electric field.The linear slope was used to extract the conduction band offset at the Al 2 O 3 /AlGaN interface, which were 2.40 and 1.87 eV, respectively, for devices A and B. The lower gate leakage current density of device A was attributed to the higher conduction band offset at the Al 2 O 3 /AlGaN interface.The conduction band offset for device A was larger than the value of 2.2 eV in Ref. [25].
Time-dependent dielectric breakdown (TDDB) is one of the most common characterization methods for evaluating gate dielectric reliability [26].The testing process of TDDB involves applying a constant bias stress on the gate dielectric for a long time, and monitoring the variation in leakage current passing through the dielectric layer.The quality of the gate dielectric can be evaluated using the magnitude of leakage and the time to breakdown (t BD ) under the same gate bias stress.The reasons for leakage current and breakdown of the gate dielectric are as follows.There are defects inside the gate dielectric at the initial state, and these defects are mainly bulk defects formed during the sedimentation process.Applying electrical stress to the gate dielectric can induce random defects within the gate dielectric, causing leakage current.In addition, when electrons accelerate through the gate dielectric, it can also cause damage to the gate dielectric and form new defects.When the defects form a continuous seepage path inside the gate dielectric, the leakage current rapidly increases and the gate dielectric layer undergoes breakdown.High electrical stress will accelerate the generation of defects, generate higher leakage current, and thus accelerate the breakdown process of the gate dielectric.Due to the different breakdown voltages for device A and device B, two sets of gate bias were used to stress the devices A and B, respectively.The time-dependent gate breakdown characteristics are shown in Figure 4a,b.The t BD for gate dielectric at different gate voltages statistically obey the Weibull distribution, which can be described by [27]  Time-dependent dielectric breakdown (TDDB) is one of the most common chara ization methods for evaluating gate dielectric reliability [26].The testing process of T involves applying a constant bias stress on the gate dielectric for a long time, and m toring the variation in leakage current passing through the dielectric layer.The quali the gate dielectric can be evaluated using the magnitude of leakage and the time to br down (tBD) under the same gate bias stress.The reasons for leakage current and br down of the gate dielectric are as follows.There are defects inside the gate dielectric a initial state, and these defects are mainly bulk defects formed during the sedimenta process.Applying electrical stress to the gate dielectric can induce random defects w the gate dielectric, causing leakage current.In addition, when electrons accelerate thro the gate dielectric, it can also cause damage to the gate dielectric and form new def When the defects form a continuous seepage path inside the gate dielectric, the lea current rapidly increases and the gate dielectric layer undergoes breakdown.High trical stress will accelerate the generation of defects, generate higher leakage current thus accelerate the breakdown process of the gate dielectric.Due to the different br down voltages for device A and device B, two sets of gate bias were used to stres devices A and B, respectively.The time-dependent gate breakdown characteristic shown in Figure 4a,b.The tBD for gate dielectric at different gate voltages statistically the Weibull distribution, which can be described by [27] where t is the gate voltage application time,  is the Weibull slope, and  is the chara istic lifespan or scale factor.The Weibull failure distribution is linearly simplified as follows:

𝑙𝑛 −𝑙𝑛(1 − 𝐹(𝑡)) = 𝛽𝑙𝑛(𝑡) − 𝛽𝑙𝑛(𝜂)
A larger  indicates a more concentrated distribution of tBD in the breakdown c acteristic [28].Figure 4c,d shows the Weibull plots of the tBD distribution for devices A B. Weibull slope  was extracted and found to be 5 and 4.5 for devices A and B, w indicated that ALD-Al2O3 with alternating O2 plasma treatment has better quality an liability.These results were larger than the value of 4.45 in Ref. [29], although Al2O3 h thicker thickness (25 nm).
where t is the gate voltage application time, β is the Weibull slope, and η is the characteristic lifespan or scale factor.
Nanomaterials 2024, 14, 523 5 of 9 The Vth instability induced by high-temperature operation and long-term gate stress limits the commercial application of AlGaN/GaN MIS-HEMTs.To investigate the thermal stability of Vth, the transfer characteristic curves of device A and device B at various temperatures from 30 °C to 150 °C in steps of 30 °C were measured, as is shown in Figure 5.The OFF-state drain current increased by about two orders of magnitude as a result of increased buffer leakage current [30].The ON-state IDS decreased slightly due to the lower carrier mobility at higher temperatures [31].The Weibull failure distribution is linearly simplified as follows: A larger β indicates a more concentrated distribution of t BD in the breakdown characteristic [28].Figure 4c,d shows the Weibull plots of the t BD distribution for devices A and B. Weibull slope β was extracted and found to be 5 and 4.5 for devices A and B, which indicated that ALD-Al 2 O 3 with alternating O 2 plasma treatment has better quality and reliability.These results were larger than the value of 4.45 in Ref. [29], although Al 2 O 3 had a thicker thickness (25 nm).
The V th instability induced by high-temperature operation and long-term gate stress limits the commercial application of AlGaN/GaN MIS-HEMTs.To investigate the thermal stability of V th , the transfer characteristic curves of device A and device B at various temperatures from 30 • C to 150 • C in steps of 30 • C were measured, as is shown in Figure 5.The OFF-state drain current increased by about two orders of magnitude as a result of increased buffer leakage current [30].The ON-state I DS decreased slightly due to the lower carrier mobility at higher temperatures [31].The Vth instability induced by high-temperature operation and long-term gate stress limits the commercial application of AlGaN/GaN MIS-HEMTs.To investigate the thermal stability of Vth, the transfer characteristic curves of device A and device B at various temperatures from 30 °C to 150 °C in steps of 30 °C were measured, as is shown in Figure 5.The OFF-state drain current increased by about two orders of magnitude as a result of increased buffer leakage current [30].The ON-state IDS decreased slightly due to the lower carrier mobility at higher temperatures [31].Figure 6 shows the temperature-dependence Vth shift (ΔVth) for devices A and B. The device A demonstrated a better Vth thermal stability and the maximum ΔVth of 0.24 V was achieved at 150 °C at the IDS level of 1 µA/mm, less than that of 0.55 V for device B at 150 °C.However, ΔVth in Ref. [30] is larger than 1V at the same test temperature.Figure 6 shows the temperature-dependence V th shift (∆V th ) for devices A and B. The device A demonstrated a better V th thermal stability and the maximum ∆V th of 0.24 V was achieved at 150 • C at the I DS level of 1 µA/mm, less than that of 0.55 V for device B at 150 • C.However, ∆V th in Ref. [30] is larger than 1V at the same test temperature.To assess the Vth stability of the device under long-time gate bias stress, the forward gate bias stress (VG_stress) of 2 V was applied to the gate with source and drain grounded.A quick ID-VGS test was conducted after certain interval times (1,5,10,20,40,60,80,100,200, 400, 500, 600, 800, 1000, 2000, and 3000 s). Figure 7 shows the multiple ID-VGS curves throughout the entire testing process.The ID-VGS curves positively shift under the forward gate bias stress, which corresponded to electrons in the channel being trapped [32].During the forward gate bias stress application process, the electric field in the AlGaN barrier layer is very high, especially at the edge of the gate.A strong electric field can cause electrons to tunnel from the defects in the AlGaN barrier layer to the valence band, which is known as Zener trapping.Electrons in 2DEG are then emitted into the defects, causing a To assess the V th stability of the device under long-time gate bias stress, the forward gate bias stress (V G_stress ) of 2 V was applied to the gate with source and drain grounded.A quick I D -V GS test was conducted after certain interval times (1,5,10,20,40,60,80,100,200, 400, 500, 600, 800, 1000, 2000, and 3000 s). Figure 7 shows the multiple I D -V GS curves throughout the entire testing process.The I D -V GS curves positively shift under the forward gate bias stress, which corresponded to electrons in the channel being trapped [32].During the forward gate bias stress application process, the electric field in the AlGaN barrier layer is very high, especially at the edge of the gate.A strong electric field can cause electrons to tunnel from the defects in the AlGaN barrier layer to the valence band, which is known as Zener trapping.Electrons in 2DEG are then emitted into the defects, causing a decrease in electron concentration in the channel and a positive shift in the V th .To assess the Vth stability of the device under long-time gate bias stress, the forward gate bias stress (VG_stress) of 2 V was applied to the gate with source and drain grounded.A quick ID-VGS test was conducted after certain interval times (1,5,10,20,40,60,80,100,200, 400, 500, 600, 800, 1000, 2000, and 3000 s). Figure 7 shows the multiple ID-VGS curves throughout the entire testing process.The ID-VGS curves positively shift under the forward gate bias stress, which corresponded to electrons in the channel being trapped [32].During the forward gate bias stress application process, the electric field in the AlGaN barrier layer is very high, especially at the edge of the gate.A strong electric field can cause electrons to tunnel from the defects in the AlGaN barrier layer to the valence band, which is known as Zener trapping.Electrons in 2DEG are then emitted into the defects, causing a decrease in electron concentration in the channel and a positive shift in the Vth.As shown in Figure 8, the extracted ΔVth after the 3000 s gate bias stress of 2 V were 0.55 V and 0.88 V for devices A and B, respectively.Device A showed a relatively small ΔVth compared to device B. This indicated that the trap state density in the dielectric was reduced by the alternating O2 plasma treatment [15].Furthermore, subthreshold slope (SS) did not show any significant changes after long-time gate bias stress for both devices.As shown in Figure 8, the extracted ∆V th after the 3000 s gate bias stress of 2 V were 0.55 V and 0.88 V for devices A and B, respectively.Device A showed a relatively small ∆V th compared to device B. This indicated that the trap state density in the dielectric was reduced by the alternating O 2 plasma treatment [15].Furthermore, subthreshold slope (SS) did not show any significant changes after long-time gate bias stress for both devices.

Conclusions
The Vth stability and gate reliability of the AlGaN/GaN MIS-HEMTs with alternating O2 plasma treatment were investigated in this article.The conduction band offset at the Al2O3/AlGaN interface was elevated to 2.4 eV after the alternating O2 plasma treatment, and hence resulted in lower gate leakage current density.The gate dielectric reliability was also improved, which was characterized by the TDDB test.The device with the alternating O2 plasma treatment also showed improved thermal stability of Vth and long-time gate bias induced Vth instability.The proposed O2 plasma alternating treatment technique was found to exhibit superior performance, which is highly desirable in high-performance and reliable power devices.

Figure 1 .
Figure 1.(a) Schematic cross-sectional illustration of the AlGaN/GaN MIS-HEMT.(b) Schematic process flow of depositing ALD-Al2O3 film with the alternating O2 plasma treatment.Figure 1.(a) Schematic cross-sectional illustration of the AlGaN/GaN MIS-HEMT.(b) Schematic process flow of depositing ALD-Al 2 O 3 film with the alternating O 2 plasma treatment.

Figure 1 .
Figure 1.(a) Schematic cross-sectional illustration of the AlGaN/GaN MIS-HEMT.(b) Schematic process flow of depositing ALD-Al2O3 film with the alternating O2 plasma treatment.Figure 1.(a) Schematic cross-sectional illustration of the AlGaN/GaN MIS-HEMT.(b) Schematic process flow of depositing ALD-Al 2 O 3 film with the alternating O 2 plasma treatment.

Figure 3 .
Figure 3. (a) Gate leakage current density characteristic and (b) FN tunneling plot of log versus for device A and device B.

Figure 3 .
Figure 3. (a) Gate leakage current density characteristic and (b) FN tunneling plot of log J/E 2 ox

Figure 4 .
Figure 4. (a,b) tBD of device A and device B. (c,d) Weibull plots of the tBD distribution for device A and device B.

Figure 4 .
Figure 4. (a,b) t BD of device A and device B. (c,d) Weibull plots of the t BD distribution for device A and device B.

Figure 4 .
Figure 4. (a,b) tBD of device A and device B. (c,d) Weibull plots of the tBD distribution for device A and device B.

Figure 5 .
Figure 5. (a,b) Temperature-dependent ID-VGS characteristics of device A and device B with the measurement temperature increasing from 30 to 150 °C.

Figure 5 .
Figure 5. (a,b) Temperature-dependent I D -V GS characteristics of device A and device B with the measurement temperature increasing from 30 to 150 • C.

Figure 6 .
Figure 6.The measured temperature-dependent ΔVth for device A and device B.

Figure 6 .
Figure 6.The measured temperature-dependent ∆V th for device A and device B.

Figure 6 .
Figure 6.The measured temperature-dependent ΔVth for device A and device B.

Figure 7 .
Figure 7. (a,b) Multiple ID-VGS characteristics of the MIS-HEMTs during the 3000 s gate bias stress of 2 V for device A and device B.

Figure 7 .
Figure 7. (a,b) Multiple I D -V GS characteristics of the MIS-HEMTs during the 3000 s gate bias stress of 2 V for device A and device B.

Nanomaterials 2024, 14 , 523 7 of 9 Figure 8 .
Figure 8.The measured ΔVth during the 3000 s forward gate bias stress for device A and device B.