Search Results (546)

In this paper, we present a study on the automated design optimization of a wideband low-noise amplifier (LNA) operating in Ku-band (12 to 18 GHz) using proximal policy optimization (PPO), one of the widely applied reinforcement learning (RL) algorithms for engineering problems. As a target microwave active circuit, we select a two-stage LNA architecture, where transmission lines (TLs) are dominantly used for impedance matching and gain/noise optimization. For simplicity, all widths of TLs were fixed so that the characteristic impedance is 50 Ω, with lengths of TLs being set as design parameters. In addition, dimension variables of capacitors were treated as design parameters and, in total, we optimized 29 parameters. For target specifications, we set both $S_{11}$ and $S_{22}$ to be below −10 dB over the 12–18 GHz band and the noise figure (NF) to be below 2 dB. A total of 20,140 simulations were performed for training and the overall process took about 24 h. The results show that both the reward and the loss converged appropriately, achieving the target specifications successfully. For the final results, we performed up to 25 predictions, and the prediction process was terminated early if a solution meeting all target specifications was found within the given number of attempts. The device model used was a commercial 150 nm GaN high-electron-mobility transistor (HEMT) process technology. Full article

This research focuses on the design and simulation of a V-band single-chip transmit-and-receive front-end integrating an LNA, PA and switching functions for ISL terminals. Two technologies are compared: a 60 nm GaN/Si HEMT from MESC and a 100 nm GaAs HEMT from UMS. In Tx mode, the proposed design targets a saturated output power of at least 20 dBm and a power-added efficiency of no less than 5%. In Rx mode, the goal is 4 dB noise figure. In both cases, the small signal gain must exceed 20 dB across the 59–71 GHz band. Full article

We propose a terahertz (THz) antenna-coupled wire-channel field-effect transistor—modified EdgeFET (m-EdgeFET), formed by combining single-gate FinFET and dual-side-gate EdgeFET concepts, which is used for THz detection. The proposed hybrid design was implemented on AlGaN/GaN high-electron-mobility transistor (HEMT) structures, demonstrating distinct response characteristics under 150 GHz and 300 GHz radiation at room temperature. The responsivity dependence on the channel length was determined, revealing that the peak responsivity reached up to 6.5 V/W at a gate voltage of −3 V, i.e., at a gate bias that is an order lower in magnitude than that required for EdgeFET to reach the maximum response. Meanwhile, the gate leakage current decreased by an order of magnitude (to about 1 nA) compared to a FinFET with similar geometry. The proposed geometry was shown to operate in two regimes: source-drain coupling (SD) and gate coupling (GG) of THz radiation with the transistor wire channel. The results confirm that the m-EdgeFET design is suitable for electrically controlled and fast THz detection. Full article

This paper presents a 13 W Ku-band GaN HEMT MMIC power amplifier employing a coupled-line interstage stabilization technique for radar sensor front-end applications. High-efficiency and stable power amplification in the Ku-band is essential for radar sensing systems, where low-frequency instability and process sensitivity often limit multistage GaN amplifier performance. To address these challenges, a coupled-line interstage network is introduced instead of conventional series capacitors and parallel RC stabilization circuits. The proposed structure effectively suppresses low-frequency gain while maintaining RF performance and improving robustness against process variations due to its planar transmission-line implementation. The two-stage power amplifier was fabricated using a 0.25 μm commercial GaN HEMT MMIC process. For compact implementation, the coupled-line structure was realized in a meandered layout and verified through full electromagnetic simulations. Measured small-signal results show a gain (S21) of 18.6–21.6 dB, with input and output return losses (S11 and S22) of −3.3 to −10.2 dB and −4.4 to −7.2 dB, respectively, over 13.5–16 GHz. Large-signal measurements demonstrate a saturated output power of 40.7–41.5 dBm and a power-added efficiency of 21.3–28.1% across the same frequency range. The fabricated MMIC achieved stable operation without oscillation, validating the effectiveness of the proposed coupled-line stabilization approach for Ku-band radar sensor systems. Full article

In this work, a novel understanding of the main failure mechanism of a Schottky p-GaN gate AlGaN/GaN HEMT subject to forward gate stress is reported. First an experimental characterization of the gate leakage current (I_GSS) at different temperatures is reported. Then, Technology Computer Aided Design (TCAD) simulations are used to reproduce the experimental I_GSS thanks to the impact ionization model, also at different temperatures. Simulation results underline how the stressed regions for the Device Under Test (DUT) at high gate biases are the Schottky/p-GaN interface, the p-GaN/AlGaN barrier interface, and p-GaN sidewalls. Moreover, Time Dependent Gate Breakdown (TDGB) measurements were done, and the TEM analysis on the failed device showed the lattice crystal damage located at the p-GaN/AlGaN interface, in accordance with TCAD simulations’ current density distribution at high voltage gate stress. Full article

The threshold voltage (Vth) of p-GaN gate enhancement-mode (E-mode) high electron mobility transistors (HEMTs) on silicon substrates grown by metal–organic chemical vapor deposition (MOCVD) is often limited to 1.0–1.5 V. Apart from the low Mg acceptor activation rate, the non-uniform vertical Mg distribution in thin p-GaN layers is also a key bottleneck limiting Vth. This work reveals that the vertical distribution (not only magnitude) of Mg doping fundamentally influences Vth by modulating the charge centroid and electric field coupling to the heterointerface. Through bis(cyclopentadienyl)magnesium (Cp₂Mg) flow modulation, surfactant-assisted growth, and growth rate adjustment, the vertical Mg doping uniformity within the 80 nm p-GaN layer was improved while effectively suppressing Mg out-diffusion. A short-cycle gate-first self-aligned process was used to fabricate the devices, and the results showed that the improved Mg vertical distribution led to a significant Vth enhancement by 0.75 V. Technology Computer-Aided Design (TCAD) simulations further demonstrated that the uniform doping profile builds a stronger negative space charge field beneath the gate, raising the energy band and increasing Vth. This work not only presents practical strategies, but also establishes a direct physical link between vertical Mg doping distribution and Vth in Si-based E-mode HEMTs. Full article

A comparative study was undertaken to examine the V_TH stability of p-GaN gate high electron mobility transistors (HEMTs) without the p-NiO reduced surface field (RESURF) terminal and with the RESURF terminal under off-state drain voltage stress and negative gate stress, involving in-depth analyses of the net negative charge accumulation processes in the gate region and buffer layer, thereby revealing the degradation mechanisms of the devices. The findings indicate that the p-NiO RESURF terminal effectively enhances the stability of V_TH under off-state drain voltage stress by injecting holes into the buffer layer and hence initiating a light-pumping effect, and simultaneously also by flattening the electric field peak on the drain side beneath the gate and thus significantly mitigating hole loss in the gate region and electron capture in the buffer layer. This study provides a theoretical basis for the application of the p-NiO RESURF terminal in p-GaN HEMTs. Full article

The accelerating adoption of electric vehicles (EVs) is driving the demand for next-generation wide-bandgap (WBG) power devices that can deliver high efficiency, high power density, and robust operation under stringent electrical and thermal stress. Gallium nitride (GaN) high-electron-mobility transistors (HEMTs) have emerged as a leading WBG technology due to their high breakdown voltage, ultrafast switching capability, and low conduction and switching losses relative to silicon devices, enabling high-performance EV power converters such as on-board chargers, DC-DC converters, and traction inverters. This review provides a comprehensive device-level assessment of GaN HEMTs, emphasizing advanced device architectures, state-of-the-art discrete transistors, and their implications for high-frequency, high-efficiency power conversion. Critical performance and reliability challenges, including current collapse, self-heating, and gate degradation, are analyzed in the context of their physical mechanisms and operational behavior under realistic conditions such as elevated junction temperatures, high switching frequencies, and dynamic load profiles. Furthermore, emerging opportunities in ultra-wide-bandgap semiconductor technologies beyond GaN are discussed, providing insights to guide the design, optimization, and robust integration of WBG devices into next-generation EV power electronic systems. Full article

Power density and power efficiency are crucial for the design of high-performance computing servers. Buck converters exist due to their simplicity, but achieving a solution that combines high efficiency and high power density remains an ongoing research area in buck converter design. High-frequency switching, which reduces inductor size in buck converters, is a common method for achieving high power density; however, high-frequency switching introduces higher switching losses, hence the frequent use of GaN HEMTs, which have low switching losses. To achieve both high efficiency and high power density, this study proposes a compact buck converter design that pairs a D-type GaN HEMT with a low-voltage PMOS, termed a P-cascode GaN HEMT. We analyze different current switching modes and find that boundary conduction mode (BCM) can minimize inductor size while maintaining high power efficiency. This paper explores the theoretical basis of BCM and the P-cascode GaN HEMT, derives the operating conditions of BCM, estimates power efficiency, and proposes a high-power density buck converter solution. Simulation and experimental results show that the proposed design achieves 95% power efficiency in applications from 12 V to 3.3 V, while reducing the inductor size by a factor of 10 compared to continuous conduction mode (CCM) designs. Full article

In this study, enhancement- and depletion-mode (E- and D-mode) GaN-based 120 nm-wide fin-gated multiple nanochannel metal–oxide–semiconductor high-electron-mobility transistors (MOS-HEMTs) were manufactured on the epitaxial Al_0.83In_0.17N/GaN/Al_0.18Ga_0.82N/GaN two-dimensional electron gas (2DEG) channel layers grown on Si substrates using a metal-organic chemical vapor deposition system. The oxide layer grown directly by the photoelectrochemical oxidation method was used as the gate oxide layer in D-mode MOS-HEMTs. Furthermore, E-mode MOS-HEMTs used ferroelectric stacked LiNbO₃/HfO₂/Al₂O₃ layers as the gate oxide layers. The 120 nm-wide multiple nanochannels and various-length source field plates (SFPs) were fabricated and incorporated into monolithic complementary MOS-HEMTs (CMOS-HEMTs) consisting of D- and E-mode MOS-HEMTs. The resulting monolithic unskewed inverter was achieved by modulating the drain-source current of the D-mode MOS-HEMTs. The noise low margin of 2.03 V and noise high margin of 2.10 V of the unskewed monolithic inverter were obtained. From the dynamic experimental results, the rising time and falling time of the unskewed monolithic inverter were 4.9 μs and 3.2 μs, respectively. The breakdown voltage could be improved by incorporating an SFP. When the SFP edge was located at the center between the gate electrode and the drain electrode, the maximum breakdown voltage of 855 V was obtained. Full article

This article presents the design and implementation of a 6–18 GHz GaN monolithic microwave integrated circuit (MMIC) power amplifier (PA). A two-stage cascaded reactive matching network structure based on transistor stacking technology is employed to achieve circuit gain, and a multi-cell combination is used in the final stage to simultaneously achieve high power and high efficiency. For demonstration, a prototype of the proposed PA with an area of 4.5 × 3.4 mm² is fabricated in a 0.1 µm GaN-on-Si high-electron-mobility transistor (HEMT) process. The measured results of the GaN PA show a small signal gain of 25–29 dB, an output power of 40.8–42.5 dBm, and a power-added efficiency (PAE) of 27–38% in the operating frequency range of 6–18 GHz. Full article

Accurate and efficient modeling of AlGaN/GaN HEMTs is essential for the design of next-generation power electronics. This study introduces a hybrid Auxiliary Classifier Generative Adversarial Network (ACGAN)–mixup data augmentation framework to enhance deep neural network application in AlGaN/GaN high-electron-mobility transistor modeling with limited data. Based on only 20 distinctive devices, ACGAN uses technology computer-aided design (TCAD)-calibrated data to generate high-quality synthetic drain current ($I_{ds}$) under various electronic bias conditions. The quality of the generated data is validated via Jensen–Shannon divergence with an average of 0.0341. A one-dimensional convolutional neural network (1D-CNN) predictive model is trained on augmented data and achieves stable convergence, with a mean absolute error of 0.002 A/mm for the off-state $I_{ds}$ and 0.052 A/mm for the linear region. It also shows improved robustness over the model trained on original non-augmented data. The proposed approach offers a low-cost alternative to resource-intensive TCAD simulations, enabling accurate device modeling with limited data. Full article

This study presents a detailed electrical analysis of AlGaN/GaN/Si HEMTs grown by molecular beam epitaxy, using direct and pulse current, small-signal microwave, and deep-level transient spectroscopy (DLTS) techniques to investigate transport characteristics and defect-related effects. DC measurements revealed self-heating effects and leakage currents, while RF analysis highlighted the devices’ high-frequency capabilities alongside parasitic effects linked to deep-level traps. Pulsed I–V characterization demonstrated gate-lag and drain-lag behaviors associated with dynamic charge trapping. DLTS identified electron traps, emphasizing their critical role in device degradation and switching performance. The strong correlation between trap states and electrical behavior underlines the importance of defect control for enhancing efficiency and reliability. Full article

From 4G to 5G to 6G, every few years, a new generation of data transmission technology emerges to meet the growing demand for faster and more efficient communication. Artificial intelligence, the Internet of Things and the increasing need for global connectivity are the key drivers of this evolution, pushing both research and industry toward ever-higher data rates. These advanced technologies already consume vast amounts of resources and energy, relying on high-tech nano-fabrication processes such as metal–organic chemical vapor deposition, dry etching, deposition and lithography, all of which typically occur in energy-intensive cleanroom environments. This study evaluates the epitaxy process of GaN on SiC for high-electron-mobility transistor (HEMT) devices and integrated circuits using life cycle assessment. GaN HEMTs offer high efficiency and excellent thermal conductivity, paving the way for reduced chip footprints for lower energy consumption. This analysis enables informed decision-making regarding sustainability by providing detailed data and interpretation of Fraunhofer IAF’s GaN-on-SiC HEMT technology. Full article

The substantially lower breakdown electric field of Si compared to GaN necessitates thick buffer layers in Si-based GaN power devices for medium-voltage applications, significantly increasing cost. Recently, sapphire substrates, offering high electrical insulation and excellent mechanical strength, have emerged as a promising alternative. In this work, we demonstrate a CMOS-compatible process for sapphire-based GaN MIS-HEMTs utilizing a thin buffer layer. The fabricated devices with a W_G of 20.4 mm and an L_GD of 24 μm achieve a high off-state breakdown voltage >1650 V and a maximum on-state current > 4.1 A, with tight statistical distributions of V_TH and R_ON across the wafer. Furthermore, statistical characterization results of dynamic R_ON and leakage current under electrical stress conditions at both room temperature and 150 °C, confirm operational viability at high temperatures. Finally, long-term reliability for 650 V operation is validated by high-temperature reverse bias (HTRB) accelerated aging tests. Full article