Design of GaN HEMT Buck Converter for BCM Operation

Abstract

Power density and power efficiency are crucial for the design of high-performance computing servers. Buck converters exist due to their simplicity, but achieving a solution that combines high efficiency and high power density remains an ongoing research area in buck converter design. High-frequency switching, which reduces inductor size in buck converters, is a common method for achieving high power density; however, high-frequency switching introduces higher switching losses, hence the frequent use of GaN HEMTs, which have low switching losses. To achieve both high efficiency and high power density, this study proposes a compact buck converter design that pairs a D-type GaN HEMT with a low-voltage PMOS, termed a P-cascode GaN HEMT. We analyze different current switching modes and find that boundary conduction mode (BCM) can minimize inductor size while maintaining high power efficiency. This paper explores the theoretical basis of BCM and the P-cascode GaN HEMT, derives the operating conditions of BCM, estimates power efficiency, and proposes a high-power density buck converter solution. Simulation and experimental results show that the proposed design achieves 95% power efficiency in applications from 12 V to 3.3 V, while reducing the inductor size by a factor of 10 compared to continuous conduction mode (CCM) designs.

1. Introduction

Modern electronic systems rely on DC-DC converters for efficient power delivery across various applications. Among these converters, linear-mode converters are noted for their simplicity, low output noise, and rapid transient response; however, they are constrained by their inability to step up voltage and their relatively low efficiency [1]. In contrast, high-frequency pulse-width modulation (PWM) switching converters frequently achieve efficiencies exceeding 90% and support higher power densities with multiple outputs [2,3]. Nonetheless, such converters face greater circuit complexity, elevated electromagnetic interference (EMI), and restricted switching frequencies, largely due to heightened stress on semiconductor devices.

Since the size and weight of inductors, transformers, and capacitors are inversely proportional to the switching frequency, converter designs have increasingly turned to higher-frequency operations to reduce the physical footprint of these passive components. In this context, the next generation of power converters—referred to as soft-switching resonant converters—offers a promising solution to mitigate switching losses and EMI by minimizing the overlap between voltage and current during switching transitions [4,5,6]. Since the size and weight of passive components are inversely proportional to the switching frequency, converter designs have increasingly shifted toward higher-frequency operation to achieve higher power density. However, conventional hard-switched buck converters, while efficient at moderate frequencies, suffer from increased switching losses as the switching frequency rises. To address the growing demands of low-voltage, high-current applications, such as point-of-load (PoL) converters in advanced computing systems and AI power supplies, several advanced buck-derived architectures have been developed [7]. Multiphase buck converters distribute the load current across multiple interleaved phases, reducing conduction losses, enabling ripple cancelation, and improving thermal performance [8,9]. Multilevel buck converters, such as three-level structures, reduce voltage stress on switching devices and lower current ripple, allowing higher switching frequency operation and improved efficiency [10]. Switched-capacitor–inductor (SCI) hybrid converters further enhance power density and efficiency by combining capacitive voltage conversion with inductive regulation, enabling reduced voltage stress and improved current sharing [10,11].

Despite these advancements, switching losses remain a critical limitation at high frequencies. Therefore, soft-switching techniques are introduced to ensure that switching transitions occur under zero or near-zero voltage or current conditions [12,13]. By minimizing the overlap between voltage and current during switching transitions, switching noise and energy losses are significantly reduced. This approach also alleviates dv/dt and di/dt stresses on power semiconductor devices and enables higher switching frequencies, resulting in improved power density, reduced passive component size, and lower electromagnetic interference. In this context, buck converters that utilize soft-switching resonant principles can have high efficiency with high power density [14]. Although silicon-based MOSFETs remain prevalent in converters operating at switching frequencies of 50–200 kHz [15,16], their performance suffers at higher frequencies due to the intrinsic limitations of high output capacitance (Coss) and gate charge [16]. However, as the switching frequency increases, conventional silicon-based converters experience rapidly rising switching losses and parasitic-related inefficiencies, underscoring the need for high-performance wide-bandgap (WBG) devices such as GaN power transistors to sustain efficiency at MHz operation. The above features make the synchronous buck converter an attractive candidate for SiP high-voltage conversion [17,18]. In response, wide-bandgap (WBG) devices, including gallium nitride (GaN) and silicon carbide (SiC), offer substantial advantages stemming from their superior material properties—low gate charge, reduced output capacitance, and excellent thermal performance in comparison with the Si counterparts [19]. Among GaN devices, cascode GaN-FETs stand out for their higher blocking voltage, faster switching speed, and lower on-resistance. By pairing a normally-on GaN HEMT with a low-voltage silicon MOSFET, cascode structures achieve normally-off operation, simplifying gate driver design. Several studies discussed in [16,17,20] have documented the performance advantages of cascode GaN-FETs. In [20], the cascode GaN-FET is utilized in a bidirectional DC-DC buck/boost converter, achieving 96% efficiency as the output power level is increased from 200 to 500 W, which is 2–3% better than the Si-IGBT device counterpart. In [21], the cascode GaN-FET-based converter showed above 96% efficiency from 200 to 400 W at a switching frequency of 100 kHz, mainly due to the superior intrinsic material properties and high electron mobility of GaN HEMT, while also highlighting challenges related to parasitic inductances and thermal management [22]. These studies indicate that cascode configurations offer superior performance compared to standalone devices. However, certain challenges must be addressed, including the matching of intrinsic device capacitances [23,24], potential avalanche conditions in the low-side switch [25], and stray inductance analysis within the interconnection of the two cascode devices [26].

The recent challenge of the PoL design in AI cluster power supplies is to simultaneously achieve high power density (>1 kW/in³) and high efficiency (>90%). Despite these hurdles, cascode GaN-FETs remain a promising option for high-efficiency power applications. However, the switching frequency of the cascode topology is constrained by the NMOS device, and the returning current flow from the load to the source from the body diode of the high-side transistor renders the configuration unsuitable for synchronous rectification applications. Although the issue is addressed by implementing a P-cascode GaN HEMT topology [27] to increase the power density, the studies on the P-cascode GaN HEMT are more recent.

This study aims to highlight the importance of minimizing inductance to reduce power loss caused by its equivalent series resistance (ESR) through the analysis of different switching modes. The paper is organized as follows. Section 1 introduces the research motivation and the importance of inductance reduction in power conversion systems. Section 2 derives the relationship between inductor size and power efficiency under different current modes. Section 3 presents the implementation of the P-cascode GaN HEMT and the corresponding System-in-Package (SiP) integration approach. Section 4 describes the experimental validation using discrete D-mode GaN HEMTs and PMOS devices. Section 5 discusses the experimental results and provides further analysis. Finally, Section 6 concludes the paper.

2. Buck Converter with Active Rectification

2.1. Currrent Modes

The buck converter in Figure 1a is a voltage step-down device that converts electrical power from high-voltage storage to low-voltage usage. The converter consists of the minimal number of components among all possible circuit topologies for a voltage step-down device, allowing it to achieve the smallest size and highest power density. The buck converter uses an inductor $L$ to absorb the voltage difference between the high-voltage storage and low-voltage usage without causing power loss. From the perspective of the inductor, the buck converter operates in three current modes including CCM, BCM and Discontinuous Current Mode (DCM). CCM is defined by $I_{L,min}>0$. BCM is defined as a boundary condition where $I_{L,min}=0$, and the blocking time $t_b=0$. DCM is characterized by $I_{L,min}=0$, and a non-zero blocking time $t_b>0$, as shown in Figure 1b.

$V_L$ is the voltage across the inductor and $V_r$ is the forward voltage of the body diode. In CCM, assuming that the RC time constant of the load is much greater than the period time $T=1/f_s$, the control of duty $\delta >0$ is derived as follows.

$$\delta ={\displaystyle \frac{V_o+V_r}{V_{DD}+V_r}}$$

(1)

The above equation holds true only when $V_o>V_r$. The minimum current $I_{L,min}$ is derived as follows.

$$I_{L,min}={\displaystyle \frac{P_o}{V_o}}-{\displaystyle \frac{\delta \left(V_{DD}-V_o\right)}{2L{f}_s}}$$

(2)

The power efficiency of the buck converter is analyzed considering $P_{Re}$ denoting the resistive loss, $P_{sw}$ denoting the switching loss, and $P_{PCB}$ denoting the circuit loss which is the sum of the PCB wire loss, connector loss and equivalent series resistance (ESR) loss of the inductor.

$$\eta ={\displaystyle \frac{P_{in}-P_{sw}-P_{Re}-P_{PCB}}{P_{in}}}$$

(3)

The resistive loss $P_{Re}$ when the buck converter employs a large inductor $L$ is derived as follows.

$$P_{Re}={I_o}^2(\delta R_D+(1-\delta {)R}_r)$$

(4)

$R_D$ denotes the resistance in the switch $s$. $R_r$ denotes the resistance in the active rectification $\overline{s}$.

2.2. Switching Loss in CCM and BCM

An interlocked half-bridge circuit, as shown in Figure 2a, can be used to simultaneously perform switching $s$ and active rectification $\overline{s}$. The interlock mechanism between switching and active rectification is implemented using an inverter with hysteresis (or dead-time) control, which prevents current shoot-through and protects both the switch and the active rectification circuit. The switching and active rectification alternately operate to direct the current into the capacitor $C$ and the load $R_o$. Therefore, from the switching perspective, they alternately drain their conduction channels, raising the drain-source voltage, while the other transistor fills charges into its channel to enable charge transportation. A specific instance of the switching may be shown as in Figure 2b.

It is assumed that the voltage and current changes follow a linear function, with a total of four switching instances occurring during each switching cycle. In BCM, since $I_{L,min}=$ 0, the high-side transistor operates under Zero Current Switching (ZCS) when turning on, while the low-side transistor operates in a near zero-voltage switching (ZVS) condition when it is turning on. Only the charge $Q_{oss,s}$ from the high-side transistor enters the drain-source channel and contributes to switching loss in the form of heat. When the inductor current approaches to the maximum current, $I_{L,max}$, the high-side transistor turns off, and after a dead time, the low-side transistor turns on. The charges $Q_{oss,\overline{s}}$ on the low-side transistor can follow the inductor current and flow into the output capacitor $C$. During the Miller plateau time, the decreasing drain current multiplied by the increasing drain-source voltage on the high-side transistor generates an additional switching loss $E_{oss,\overline{s}}$, while the diode loss on the low-side transistor during the dead time contributes to another component of the switching loss. Following a similar equation as the switching loss expression provided in [19], one may write the overall switching loss as follows.

$$P_{sw}=P_{sw,s}+P_{sw,\overline{s}}={\displaystyle \frac{1}{2}}\ast f_s{C}_{oss,s}^{*}{V_{DD}}^2+f_s\left(E_{oss,\overline{s}}+E_{doide,\overline{s}}\right)$$

(5)

$C_{oss,s}^{*}$ denotes the parasitic output capacitance of the high-side transistor which is a GaN HEMT device in this study. The parasitic output capacitance (as shown in Figure 3) of the voltage of interest, $V_{DD}=12 \mathrm{V}$, is two-thirds of the zero-voltage capacitance, i.e., 200 pF. The switching loss $E_{oss,\overline{s}}$ may be evaluated using the double pulse test [28,29] or the simplified expression in [19]. The direct dead-time loss is the energy loss due to the body diode conduction during the dead time $t_d$.

$$E_{doide,\overline{s}}=I_{L,max}·V_r·t_d$$

(6)

Among the three components in (5), our practical experience indicates that the direct dead-time loss, $E_{doide,\overline{s}}$, is the most significant in our study. However, the required dead time depends on the Miller plateau time, which is influenced by the channel resistance. A lower channel resistance in the high-side transistor results in a shorter Miller plateau time, and consequently, a shorter dead-time period, $t_d$.

2.3. Resistive Loss in BCM

The switching loss $P_{sw}$ is a function of the current, voltage rise and switching frequency. According to (2), the buck converter relates the inductance $L$ to the switching frequency $f_s$ as follows.

$$L={\displaystyle \frac{\delta }{2f_s(I_o-I_{L,min})}}\left(V_{DD}-V_o\right)$$

(7)

BCM is the degenerate case of CCM, which has the lowest inductance when $I_{L,min}=0$. The resistive loss due to $R_D$ in the switch $s$ is derived from the derivative chain-rule and (1) as follows.

$$P_{Re,s}={\int }_0^{\delta T}{i_L}^2{R}_{D}d{i}_L{\displaystyle \frac{dt}{d{i}_L}}={\displaystyle \frac{L}{V_{DD}-V_o}}{\displaystyle \frac{{I_{L,max}}^2}{3}}{R}_D{f}_s={\displaystyle \frac{4\delta }{3}}{I_o}^2{R}_D$$

(8)

The resistive loss due to the resistance $R_r$ in the active rectification is $\overline{s}$.

$$P_{Re,\overline{s}}={\displaystyle \frac{1}{T}}{\int }_{\delta T}^T{i_L}^2{R}_{D}dt={\displaystyle \frac{4(1-\delta )}{3}}{I_o}^2{R}_r$$

(9)

The buck converter application must satisfy $V_o>v_r$ during the current discharging time, $\delta T<t<T$, and the restriction for active rectification is provided as follows.

$$R_o={\displaystyle \frac{V_o}{I_o}}>{\displaystyle \frac{V_r}{I_o}}=2{\displaystyle \frac{V_r}{I_{L,max}}}=2R_r$$

(10)

In other words, the active rectifier must have a low resistance to support applications requiring low output voltage and high output power. Let the resistance of the active rectifier as well as the on-resistance of the switch both be expressed as the same fraction $\alpha$ of the load resistance, i.e.,

$$R_D=R_r=\alpha R_O, \mathrm{w}\mathrm{h}\mathrm{e}\mathrm{r}\mathrm{e} \alpha <0.5$$

(11)

The fraction $\alpha$, defined as the ratio of the on-resistance of the switch to that of the active rectifier, is referred to as the normalized on-resistance. The duty $\delta$ in (1) can be simplified as follows.

$$\delta ={\displaystyle \frac{1-\alpha }{A-\alpha }}$$

(12)

The step-down ratio $A$ is defined as $A=V_{DD}/V_o$. Without considering the switching loss, the power efficiency in (3) can be simplified as follows.

$$\eta =1-{\displaystyle \frac{4}{3}}{\displaystyle \frac{\alpha }{A}} {\displaystyle \frac{A-\alpha }{1-\alpha }}$$

(13)

The above equation appears to suggest that power efficiency is independent of the output power. However, the resistance fraction $\alpha$ is, in fact, a function of the ratio between output power and output voltage. For the same output voltage, a higher power requirement results in a lower output resistance $R$, causing the resistance fraction $\alpha$ to increase when using the same switch with the same $R_D$. The above equation can be used to derive the maximum $\alpha$, subjected to the power efficiency requirement, under the assumption that $A\gg \alpha$.

$$\alpha ={\displaystyle \frac{1-\eta }{\frac{7}{3}-\eta }}\approx 0.65\left(1-\eta \right)$$

(14)

The resistance ratio between the maximum on-resistance $R_D$ of the switch and the output resistance $R_o$ of the buck converter is shown in Figure 4. The maximum on-resistance of the switch $R_D$ can be calculated from the equation as follows.

$$R_D\le 0.65\left(1-\eta \right){V_o}^2/P_o$$

(15)

According to the design specifications in this research, where $V_{DD}=12 \mathrm{V}$, $V_o=3.3 \mathrm{V}$, $P_o=5 \mathrm{W}$ and $\eta =95\%$, we obtain that $\alpha =0.0325$ and $R_D<70 \mathrm{m}\mathsf{\Omega }$. Based on the alternative design specifications, where $V_{DD}=48 \mathrm{V}$, $V_o=0.7 \mathrm{V}$, $P_o=50 \mathrm{W}$ and $\eta =90\%$, the result derived from (4) is $R_D<0.637 \mathrm{m}\mathsf{\Omega }$. An important observation from (15) is that the requirement of low on-resistance $R_D$ of the switch is independent of the input voltage $V_{DD}$.

Accordingly, the inductor size in the buck converter is related to the switching frequency $f_s$ as follows.

$$L{f}_s={\displaystyle \frac{V_o}{2P_o}}{\displaystyle \frac{A-1}{A-\alpha }}\left(1-\alpha \right)$$

(16)

According to the design specifications in this research, where $V_{DD}=12 \mathrm{V}$, $A={\displaystyle \frac{12}{3.3}}=3.636$, $\alpha =0.1$, $P_o=5 \mathrm{W}$ and $f_s=250$ kHz, we have $L={\displaystyle \frac{1}{250k}}·{\displaystyle \frac{3.3}{10}}·{\displaystyle \frac{2.636}{3.536}}·0.9=3.12 \mathrm{u}\mathrm{H}$.

3. P-Cascode GaN HEMT

The implementation of a buck converter using a half-bridge circuit, as shown in Figure 2a, is well known. However, converting a D-mode GaN HEMT into an E-mode device requires an additional Low Voltage MOSFET (LVMOS), which increases the complexity of IC packaging. The LVMOS is an n-channel MOSFET with extremely low resistance, which, integrated together with the GaN HEMT, can bring the normally-on D-mode GaN HEMTs into a normally-off power module [28]. Including active rectification within the same package further complicates the IC packaging process. The D-mode devices exhibit lower on-resistance and higher saturation current density [30], making them well-suited for parallel configurations where increased output power is required. A specific half-bridge circuit configuration, known as the P-cascode GaN HEMT, was proposed in our previous research work [27] for a buck converter application. The P-Cascode GaN HEMT remains a normally-off power module, similar to the cascode GaN HEMT using an NMOS. A key advantage is that the connection between the D-mode GaN HEMT and the PMOS can be exposed as an output terminal for the buck converter, making it well-suited for high power density requirements in AI server applications. However, a limitation of the P-Cascode GaN HEMT is that the drain-source voltage cannot exceed the maximum gate-source voltage range, which is 43 V in this study. The key feature of this configuration is the use of GaN HEMTs to enable high-frequency applications. However, its TO-220 packaging did not allow for high power density, and it was originally designed for CCM operation, where resistive loss was not a primary concern.

3.1. Circuit Design

The P-cascode GaN HEMT uses an E-mode PMOS to replace the LVMOS for initial current blocking in the D-mode GaN HEMT. Simultaneously, the PMOS itself performs active rectification, reducing the number of ICs required in a package. A possible packaging method for the P-cascode GaN HEMT device (National Yang Ming Chiao Tung University, Hsinchu, Taiwan), using the Power Dual Flat No-Lead (PDFN) package, is shown schematically in Figure 5. This approach stacks the PMOS on top of the D-mode GaN HEMT to minimize the footprint.

The integration of the GaN HEMT, PMOS, inductor, and gate-drive circuitry on the same substrate raises thermal and electromagnetic interference. The GaN HEMT and PMOS are likely the major heat-generating components, and the resulting local temperature rise may affect nearby devices and long-term reliability. In addition, the high switching speed of GaN devices can lead to strong dv/dt and di/dt-related noise, parasitic ringing, and crosstalk within the integrated structure. To address these issues, the authors propose using an AlN DBC substrate as both a heat-spreading layer and an interposer to form the interconnection between the passive and active components, thereby improving thermal dissipation while reducing interconnect parasitics through compact routing and optimized layout.

It is also preferable to integrate the inductor, the gate-drive circuit, and the P-cascode GaN HEMT device into a module (blue rectangle), using the System-in-Package (SiP) method (green rectangle), as shown in Figure 6a, to enhance power density. This is why it is necessary to reduce the inductance $L$ and why the BCM switching method should be used. In Figure 6a, the gate signal is generated by a PWM IC. The gate driver circuit, which will be discussed further in a later section, is responsible for generating the same voltage levels (i.e., $v_G\approx v_{G,s}\approx v_{G,\overline{s}}$), but with different rise/fall time signals for $v_{G,s}$ and $v_{G,\overline{s}}$. The gate voltages are at the same signal levels; however, the referenced sources are different. The PMOS source is connected to the midpoint of the half-bridge, while the D-mode GaN source is connected to the input. Therefore, the gate voltage produces different effects on the switch and active rectifier turn-on conditions. The different rise and fall times will cause the PMOS to turn on and off with a time delay $t_d$ relative to the D-mode GaN HEMT turning off and on in opposite polarities. Another feature of the P-cascode GaN HEMT device is that it requires only a single low-side gate-driver IC.

The time delay serves two main purposes: preventing the current shooting through and the smooth corner transition of the inductor current $i_L$ triangular waveform. Figure 6b, with some exaggeration of the time delay, shows the source-gate voltage $v_{sg,\overline{s}}$ of the active rectifier turning on when $v_{sg,\overline{s}}>V_{sg,\overline{s},on}$ after the time delay period $t_{d,1}$. During this time delay period, the body diode in the PMOS is activated and smooths the changes at the corners of the triangle. However, due to the body diode’s threshold voltage of conduction, the power loss is also increased. The second time delay occurs between the time when the PMOS is turned off and the D-mode GaN HEMT is turned on when $v_{gs,\mathrm{s}}>V_{gs,\mathrm{s},\mathrm{o}\mathrm{n}}$. The difference between the PMOS turn-on voltage $V_{sg,\overline{s},on}$ and the D-mode GaN HEMT turn-on voltage $V_{gs,\mathrm{s},\mathrm{o}\mathrm{n}}$ can also be utilized to create a time delay, as will be discussed in the gate-driver design section.

3.2. Gate Driver Circuit

The gate driver circuit includes a gate driver IC, a clamped charge pump circuit and the gate resistor circuit as shown in Figure 7a. The gate driver IC generates sufficient current to quickly change the gate voltage levels of the transistors. The clamped charge pump circuit is a clamped design that converts the non-negative on–off voltage from the gate driver IC output into both positive and negative on–off voltages. The gate resistor circuit generates different current resistances, resulting in different time constants for the transistor gates. The responses of the input and individual outputs are shown in Figure 7b. Assuming that the input $v_s$ of the gate driver IC is a square wave, the clamped charge pump response $V_G$ can be expressed as follows.

$$V_G=\{\begin{array}{cc}{V}_{GG}-V_z& if v_s>0\\ -V_z& else\end{array}$$

(17)

The gate resistors are responsible for yielding different voltage slew rates for charging the input-capacitances $C_{iss,s}$ and $C_{iss,\overline{s}}$ at different moments in time. In this study, we require $R_{G,1}>R_{G,2}>R_{diode}$ to ensure that the rising time of the switch $s$ is the longest, the falling time of the switch $s$ is the shortest and both rising and falling times of the active rectifier $\overline{s}$ remain intermediate. With this gate resistor arrangement, the gate-source voltage of the D-mode GaN HEMT drops faster than that of the PMOS when $v_s$ turns off, creating a time delay $t_{d,1}$ between the D-mode GaN HEMT turning off and the PMOS turning on. Similarly, it creates a time delay $t_{d,2}$ between the PMOS turning off and the D-mode GaN HEMT turning on. As shown in Figure 7b, the body diode loss is reduced because the body diode of the switch turns on only briefly, or not at all, during switching. In practical applications, bootstrap gate drivers are widely used for high-side switches due to their low cost and circuit simplicity. However, during startup, the uncharged bootstrap capacitor can cause large inrush currents, dropping the driver supply voltage and triggering UVLO. This leads to gate-source oscillation and instability [31]. In GaN-based systems, the risk is greater due to their narrow gate voltage margin. Typically, gate-source voltage is less than 7 V due to the low turn-on voltage of the p-GaN gate, making them highly sensitive to overshoot and gate stress during startup or switching. In contrast, D-mode GaN devices tolerate a much wider gate voltage range (typically −30 V to +13 V), making them more robust against such gate voltage oscillations. However, using the D-mode GaN as a high-side switch introduces startup challenges due to its normally-on behavior. If the gate signal is not established quickly, a large inrush current may flow immediately, posing serious safety risks. In practical designs, an additional series-connected MOSFET is often used to block the current path during startup, ensuring that the D-mode GaN remains off until the gate driver becomes fully operational [28,32].

4. Simulation and Experiment

4.1. Simulation

Figure 8a shows the OrCAD PSpice simulation circuit, which includes two parallel D-mode GaN HEMTs and two parallel PMOS transistors in the half-bridge configuration. All transistors have an on-resistance $100 \mathrm{m}\mathsf{\Omega }$. Therefore, the equivalent on-resistance of the switch and active rectifier is $R_D=50 \mathrm{m}\mathsf{\Omega }$. The switching frequency is 250 kHz with a duty cycle of 27.5% (calculated as 1.1 μs/4.0 µs). Instead of the theoretical inductance 3.12 µH, we chose a SMT POWER INDUCTORS 3.3 µH inductor. The equivalent series resistance (ESR) and parasitic self-capacitance of a 3.3 µH inductor typically range from 5 to 150 mΩ and 2 to 30 pF, respectively, depending on the inductor’s size, construction, and rated current. In PoL applications with currents less than 5 A, we can choose 10 mΩ and 4 pF as nominal values and apply them in analog models. Stray inductance on the PCB is already included in the package inductor. The $C_{j0}$ of diode is 10 pF, which leads to a recovery effect. In Figure 8b, the inductor current (green trace) indicates that the switching mode is BCM. The switching transition between the D-mode GaN HEMT turning off and the PMOS turning on is shown on the right side of Figure 8b. The turn-on voltage of the D-mode GaN HEMT (−7 V) and the turn-on voltage of the PMOS (7 V) are indicated by the horizontal dashed lines. The gate-source voltage $v_{gs,s}$ of the D-mode GaN HEMT reaches the turn-off voltage earlier than the source-gate voltage $v_{sg,\overline{s}}$ of the PMOS, resulting in a dead-time period of 3 ns. Considering the bonding inductances of the D-mode GaN HEMT and PMOS within the packaging and PCB, typically around 2 nH, we observed voltage ringing on the gate-source and drain-source voltages of the transistor when the inductor current reaches the maximum current, $I_{L,max}$, as shown in Figure 8b. The voltage ripple caused by the parasitic inductance and parasitic components resulted in an additional 0.42 W power loss. Compared to the inductance-free output of 4.76 W from a 5 W input, the power efficiency decreased from 95% to 94.2%. Additional simulations revealed that increasing the output parasitic capacitance of either the D-mode GaN HEMT or the PMOS up to 2500 pF reduces power efficiency by less than 0.6%. This result indicates that the dead time during switching with the P-cascode GaN HEMT is beneficial for power efficiency, and the increased parasitic capacitance does not require additional attention to the dead time.

In the PSPICE simulation, we assumed that the output parasitic capacitances $C_{OSS}$ of both the GaN HEMT and PMOS were constant. However, this assumption still resulted in nonlinear changes in current and voltage during the conversion process, as shown in Figure 8b,c. This differs from the theoretical waveforms shown in Figure 7. Subsequent experiments will show that the even greater nonlinearity in current and voltage changes is due to the nonlinear parasitic effects of these parasitic capacitances.

4.2. Experiment

The experiment was conducted using discrete devices laid out on a printed circuit board (PCB) according to the circuit design. There are two versions of PCB implemented for the comparison study, which are the single and parallel P-cascode as shown in Figure 9a and Figure 9b respectively. The elements used in the buck converter implementation is listed in

Table 1. Design parameters and components of the buck converter.

Symbol	Description	Unit	Value
$R_o$	Load	data	2.1
$L$	Inductor	μH	3.3
$C$	Load capacitor	μF	100
$f_s$	Switching frequency	Hz	250k
$\mathrm{G}\mathrm{a}\mathrm{N}$	NYCU fabricated		130 mm (Width) D-mode
$\mathrm{P}\mathrm{M}\mathrm{O}\mathrm{S}$			SIR871DP
$\mathrm{G}\mathrm{a}\mathrm{t}\mathrm{e}\mathrm{d}\mathrm{r}\mathrm{i}\mathrm{v}\mathrm{e}\mathrm{r}$			NCP81074

.

The input voltage 12 V is supplied by the power supply Chroma 62012P-600-8 (Chroma ATE Inc., Taoyuan, Taiwan) and the output voltage 3.3 V is controlled by the electronics loading Chroma 63206A-600-420(Chroma ATE Inc., Taoyuan, Taiwan). The initial version of the PCB layout, as shown in Figure 9a, employs a single D-Mode GaN HEMT and a single PMOS to construct the half-bridge. The experiment results are shown in Figure 10a, in which the orange trace is $v_{DS,GaN}$ of the D-Mode GaN HEMT, the gray trace is $v_{SD,PMOS}$ of the PMOS and the yellow trace is the inductor current $i_L$. The half-bridge control is under the 250 kHz switching frequency with a 30% duty cycle to allow a 100 ns dead time. The three power losses in (3) are extracted from the overall losses by the formula as follows.

$$\begin{array}{c}{P}_{sw}=[\begin{array}{cc}{i}_L(v_{DS,GaN}+v_{DS,PMOS})& \mathrm{i}\mathrm{f} 7 \mathrm{V}\ge v_{DS,GaN}\ge 0.2 \mathrm{V} \\ 0& \mathrm{e}\mathrm{l}\mathrm{s}\mathrm{e}\end{array}\\ P_{Re}=[\begin{array}{cc}{i}_L{v}_{DS,GaN}& \mathrm{i}\mathrm{f} P_{loss,S} \ne 0 \mathrm{a}\mathrm{n}\mathrm{d} v_{GS,GaN}\ge v_{GS,GaN,ON} \\ i_L{v}_{DS,PMOS}& \mathrm{i}\mathrm{f} P_{loss,S} \ne 0 \mathrm{a}\mathrm{n}\mathrm{d} v_{GS,GaN}<v_{GS,GaN,ON}\end{array}\\ P_{PCB}=P_{in}-P_o-P_{Re}-P_{sw}\end{array}$$

(18)

The switching loss time is marked in Figure 10a with a blue line, while the remainder of the conversion time is attributed to resistive loss. The calculation results are provided in

Table 2. Experiment result of buck converter for 12 to 3.3 VDC conversion.

Symbol	Description	Unit	Value
			Single	Parallel
$P_{in}$	Power Input	W	6.24	5.97
$P_o$	Power Output	W	5.63	5.41
$I_L$	Output Current	A	1.71	1.64
$P_{sw}$	Switching Loss	W	0.13	0.05
$P_{Re}$	Resistive Loss	W	0.42	0.25
$P_{PCB}$	PCB Loss	W	0.06	0.26
$\eta$	Efficiency	%	90.22	90.62
${\eta }_T$	Transistor Efficiency	%	91.58	95.01
$R_D$	Resistance	mΩ	144	92
$R_D/R_o$	Normalized Resistance		0.053	0.034
$P_D$	Power Density	${\displaystyle \frac{\mathrm{W}}{{\mathrm{i}\mathrm{n}}^3}}$	1280	805

under the column labeled ‘Single’. The second version of the PCB layout employs a 2-in-parallel D-mode-GaN HEMT and a 2-in-parallel PMOS to construct the half-bridge, aiming to reduce both the on-resistance $R_D$ and the resistance of the active rectifier. The experimental results, shown in Figure 10b, indicate that the switching loss is even smaller in the second version compared to the initial version. This improvement is attributed to the use of a smaller dead time, 50 ns, made possible by the reduced resistance, which allows a shorter duration to drain out the reverse recovery current. The dead time can be reduced by adjusting the values of $R_{G,1}$ and $R_{G,2}$ in Figure 7a. In Figure 7a, smaller resistances were selected compared to those in the initial version. The calculation results are provided in Table 2 under the column labeled ‘Parallel’. The overall efficiencies $\eta$ and the individual transistor efficiencies ${\eta }_T$ are compared, which are 90.2% to 93.3% and 91.6% to 95%, respectively. The lumped on-resistance, $R_D$, is obtained by dividing the resistive losses $P_{Re}$ by the inductor current $I_L$. The normalized on-resistance $R_D/R_o$ is obtained by dividing $R_D$ by the output loading derived in (14). Given the fast switching speeds of the D-type GaN, device efficiency is highly sensitive to changes in dead time. When the dead time is too short, shoot-through occurs between the D-type GaN HEMT and the PMOS, significantly reducing power efficiency. When the dead time is too long, diode rectification leads to power loss in the PMOS body diode. Since GaN HEMTs do not have a body diode, the dead time of a D-type GaN HEMT can be made shorter than its on-time. As shown in Figure 10c,d, the experimental dead times are 8 to 10 ns, both greater than the 3 ns simulation result in Figure 8a. In practical applications, a high-speed ADC [33] is needed to monitor load and temperature changes to achieve more precise dead time control.

The particular interest in this study is that we successfully reduced the size of the inductor (yellow box in Figure 9a) to match the footprint of the GaN HEMT (red box) and PMOS (blue box), creating potential for future integrated packaging.

Using the same simulation parameters as shown in Figure 8a, we varied the on-resistance $R_D$ from 30 $\mathrm{m}\mathsf{\Omega }$ to 150 $\mathrm{m}\mathsf{\Omega }$. When divided by $R_o=2.178\mathsf{\Omega }$, these on-resistances were converted into normalized resistances ranging from 0.033 to 0.074. The simulation results, compared with the theoretical results derived in (21), are shown in Figure 11. The difference between the theoretical and simulation results arises from the theoretical assumption that switching losses can be ignored. Switching losses become increasingly significant when higher efficiency is required, playing a critical role when efficiency exceeds 95%. The experimental results listed in Table 2 are also plotted according to the normalized on-resistance $R_D/R_o$ in Figure 11 for comparison and validation. The results indicate that the experiment exhibits lower switching losses compared to the simulation, leading to higher efficiency in the experimental data than in the simulation. The linear interpolation, displayed in the red dash line, shows the agreement with the theoretical results derived in (14), which exclude switching losses.

The power density, determined by dividing the input power by the total volume of the transistors and inductor, is expressed as follows.

$$P_d={\displaystyle \frac{P_{in}}{Vol\left(Inductor\right)+Vol\left(GaN HEMT\right)+Vol\left(PMOS\right)}}$$

(19)

The transistors have a footprint of 5 $\times$ 6 mm and the total thickness of the P-cascode when they were packaged together as shown in Figure 5 can be 1.5 mm (including molding compound). As to the inductor, the Eaton EXLA1V0402-3R3-R 3.3 µH 5.5 A hafootprintrint of 4.1 × 4.1 mm and the thickness is 1.9 mm. According to (19), we calculate the power density of the single P-cascode GaN HEMT configuration as 6 W/(45 + 32)${\mathrm{m}\mathrm{m}}^3$ × 16,384 ${\mathrm{m}\mathrm{m}}^3/{\mathrm{i}\mathrm{n}}^3$ = 1280 W/${\mathrm{i}\mathrm{n}}^3$, while that of the parallel P-cascode GaN HEMT is 805 W/${\mathrm{i}\mathrm{n}}^3$. From a power density perspective, a single P-cascode GaN HEMT is superior to a parallel configuration. The results are also compared in Table 2.

5. Discussion

The output power rating linearly increases with the inductor current, $I_o=I_L$, and the power loss derived in (4) quadratically increases with the same current. Therefore, the transistor efficiency can decrease linearly with the output power rating. Equipped with the same circuit, the power rating is increased by reducing the output resistance $R_o$ from 2.1 $\mathsf{\Omega }$ to 0.688 $\mathsf{\Omega }$ and the power rating increases from 6 W to 17.2 W as shown in Figure 12. The linear regression of the efficiency versus the power rating shows the transistor efficiency is degraded by 0.366% by each output Watt increment. It is also shown that the current mode becomes CCM for a higher power rating than the rated power output 6 W for BCM. When the transistor efficiency ${\eta }_T$ requirement is 90%, the output power rating is 19.74 W and the power density is derived from the parallel P-cascode GaN HEMT arrangement in Table 2 as (19.74/5.97) $\times$ 805 = 2650 W/${\mathrm{i}\mathrm{n}}^3$. The power density can match today’s AI server power module design specification which requires 90% transistor efficiency.

When the switching frequency increases from 250 kHz to 800 kHz when $V_{DD}=12 \mathrm{V}$ and $V_o=3.3 \mathrm{V}$ remained, the inductance $L$ can be reduced from 3.3 μH to 470 nH, as predicted by (19). The equivalent series resistance (ESR) of the inductor is simultaneously reduced as the inductance decreases, owing to the shorter winding length. As shown in Figure 13, the transistor efficiencies ${\eta }_T$ are compared: the switching loss of the transistor increases with the switching frequency; therefore, the transistor efficiency of 800 kHz is lower than that of the 250 kHz application. However, the advantages of the higher switching frequency includes the BCM power rating increasing from 6W to 10 W and the 90% transistor efficiency having been extended to 25.5 W. Although, the power density is a function of the transistor efficiency ${\eta }_T$ and the input/output voltage ratio $A$, it is worth noting that the highest transistor efficiency always favors the BCM current mode. It is therefore convenient to compare the power density at their individual highest transistor efficiency points. Under the condition that $A=12 \mathrm{V}/3.3 \mathrm{V}=3.636$, the comparison shows that the power density for 800 kHz is 1300 W/${\mathrm{i}\mathrm{n}}^3$@${\eta }_T=$ 94% and for 250 kHz is 805 W/${\mathrm{i}\mathrm{n}}^3$@${\eta }_T=$ 95.01%.

In the BCM operation of the PoL application, the switching loss of the P-cascode GaN HEMT module is primarily caused by direct dead-time loss, $E_{doide,\overline{s}}$. According to the switching loss expression in (5), the GaN HEMT contributes negligible loss due to its low parasitic output capacitance (200 pF). Both simulation and experimental results show that switching loss accounts for less than 15% of the total power loss. Zero-voltage switching (ZVS), which helps reduce losses associated with parasitic output capacitance, is not as critical in this study as channel resistance. A lower channel resistance in the high-side transistor leads to a shorter Miller plateau time, which in turn reduces the dead time $t_d,$ and the associated direct dead-time loss. This reduction is crucial for achieving high efficiency in PoL applications.

This study aims to verify the ability of BCM to minimize inductance while maintaining power efficiency. Under the same circuit conditions, DCM can improve the conversion ratio or reduce the output voltage. As shown in Figure 13, at a switching frequency of 800 kHz, the DCM indicated by the triangle in the figure operates with an output voltage of less than 3.3 V, and the leftmost case has an output voltage of 2.56 V, but the efficiency drops to 91%. Other buck circuit topologies, such as using an interleaved buck converter [34] to achieve a conversion from 48 V to 1.8 V, or using a multiphase adaptive buck converter [35] to achieve a conversion from 12 V to 1.5 V, can provide a higher conversion ratio, but may sacrifice power density.

Its efficiency is comparable to that of Texas Instruments (Dallas, TX, USA) TPS54620 buck converter [36], which uses the same 250 kHz switching frequency to convert 12 V to the same 3.3 V output voltage. The power efficiency presented in this paper is 95%, which is better than the 92.8% of the Texas Instruments TPS54620 buck converter (Dallas, TX, USA) at a 2 A output current.

6. Conclusions

The demand for high-power density, high-efficiency point-of-load (PoL) converters is growing in data center and server applications. As a candidate circuit topology, buck converters need to increase their power density while maintaining high power efficiency. This paper aims to reduce the inductor size in a buck converter by applying a BCM in switching operations and to minimize switching losses by applying a complementary circuit P-cascode GaN HEMT circuit with high-frequency switching capability, thereby simultaneously improving the conversion efficiency and power density. The normalized on-resistance required for the switch and active rectifier is determined based on efficiency specifications. Simulations and analyses confirm that low on-resistance is crucial for power efficiency. While simulations show that careful consideration of switching losses is essential when power efficiency requirements exceed 95%, experiments demonstrate that shortening the dead time can reduce switching losses. The main contribution of this research is the successful reduction in the inductor size to match the dimensions of GaN HEMTs and PMOS transistors. This achievement was realized through theoretical design and experimental verification. This achievement makes it possible to integrate the GaN HEMT, PMOS, inductors, and possible gate drive circuits using heterogeneous packaging methods, paving the way for future high power density and high-efficiency point-of-load (PoL) applications.