GaN HEMTs for Electric Vehicle Power Electronics: Device Architectures, Reliability and Next-Generation Wide Bandgap Opportunities

Abstract

The accelerating adoption of electric vehicles (EVs) is driving the demand for next-generation wide-bandgap (WBG) power devices that can deliver high efficiency, high power density, and robust operation under stringent electrical and thermal stress. Gallium nitride (GaN) high-electron-mobility transistors (HEMTs) have emerged as a leading WBG technology due to their high breakdown voltage, ultrafast switching capability, and low conduction and switching losses relative to silicon devices, enabling high-performance EV power converters such as on-board chargers, DC-DC converters, and traction inverters. This review provides a comprehensive device-level assessment of GaN HEMTs, emphasizing advanced device architectures, state-of-the-art discrete transistors, and their implications for high-frequency, high-efficiency power conversion. Critical performance and reliability challenges, including current collapse, self-heating, and gate degradation, are analyzed in the context of their physical mechanisms and operational behavior under realistic conditions such as elevated junction temperatures, high switching frequencies, and dynamic load profiles. Furthermore, emerging opportunities in ultra-wide-bandgap semiconductor technologies beyond GaN are discussed, providing insights to guide the design, optimization, and robust integration of WBG devices into next-generation EV power electronic systems.

1. Introduction

The global transition to electric mobility is reshaping the automotive landscape, with electric vehicles (EVs) increasingly positioned as the cornerstone of sustainable transportation. Driven by growing environmental concerns, stringent emission regulations, and rapid advancements in clean energy technologies, EV adoption is accelerating worldwide. Market forecasts predict that EVs will surpass internal combustion engine (ICE) vehicles in global sales within the coming decades, supported by falling battery costs, expanding charging networks, and government incentives [1,2,3,4]. In this transformative shift, the performance, cost, and reliability of power electronic systems play a decisive role, as they directly influence critical EV metrics such as charging time, driving range, energy efficiency, and system compactness [5,6]. Power electronic converters, including on-board chargers (OBCs), DC-DC converters, and traction inverters, form the backbone of EV operation [7]. The traction inverters manage the bidirectional flow of electrical energy between the battery and motor, while the OBCs interface with external charging infrastructure. Their efficiency and power density, therefore, translate directly into extended vehicle range, faster charging capability, improved thermal management, and reduced system cost [8]. However, the traditional reliance on silicon (Si) power devices has reached a performance ceiling. While Si-based insulated gate bipolar transistors (IGBTs) and metal–oxide–semiconductor field-effect transistors (MOSFETs) have served as the workhorses of automotive power electronics, their inherent material limitations, like narrow bandgap, relatively low critical electric field, and modest thermal conductivity, limit the switching frequencies, efficiency, and scalability [9,10,11]. This bottleneck constrains further improvements in system miniaturization, energy density, and cost effectiveness.

Wide-bandgap (WBG) semiconductors have emerged as a disruptive alternative to Si in EV power electronics. Among these, Gallium Nitride (GaN) high-electron-mobility transistors (HEMTs) are particularly promising due to their exceptional material properties [12]. GaN offers a wide-bandgap (3.4 eV), high critical electric field, superior electron mobility, and strong polarization effects, enabling devices with high breakdown (BD) voltage, fast switching speed, and reduced conduction losses [13,14]. These characteristics allow GaN HEMTs to operate efficiently at higher switching frequencies, which in turn reduces the size of bulky passive components such as inductors and capacitors [15]. The resulting improvement in power density is especially critical for EV applications, where weight, space, and thermal constraints dictate design choices. Furthermore, GaN devices inherently improve thermal performance and reduce energy losses, contributing to overall system-level efficiency and reliability [16,17]. Beyond the technical advantages, GaN HEMTs align with the broader goals of EV manufacturers to deliver compact, lightweight, and cost-competitive solutions. For example, in traction inverters, GaN devices can facilitate higher inverter efficiencies and reduced cooling requirements [18]. In OBCs and DC-DC converters, their high-frequency capability allows for more compact designs, improving vehicle integration and reducing overall system weight [19]. These benefits collectively enable EVs with longer driving ranges, faster charging, and lower operational costs. However, challenges remain, including device reliability under harsh automotive conditions, packaging optimization for thermal management, and the cost competitiveness of GaN compared to Si and silicon carbide (SiC) devices [20,21]. The comparison of material properties of Si, SiC and GaN is given in

Table 1. Material properties of Si, SiC and GaN [22,23,24,25].

Symbol	Si	SiC	GaN
Bandgap energy (eV)	1.12	3.26	3.45
Melting point (×103 °C)	1.4	2.7	2.6
Thermal conductivity (W/m.K)	1.5	4.9	1.3
Critical electric field (MV/cm)	0.3	3.2	3.5
Electron saturation velocity (107 cm/s)	1	2	2.5
Electron mobility (×103 cm2 /Vs)	1.4	0.9	1.8

and Figure 1. In high-power-density EV platforms, where compact inverter and onboard charger designs demand elevated switching frequencies and tight thermal integration, the advantages of GaN HEMTs directly translate into reduced passive volume and higher system efficiency. However, these benefits simultaneously amplify challenges related to gate driving sensitivity, EMI, and dynamic reliability. Consequently, high-density EV implementation shifts the design focus from purely minimizing conduction losses to carefully balancing switching frequency, electromagnetic compatibility, thermal management, and long-term device reliability. From an industry perspective, this indicates that future EV power electronics will not simply pursue maximum switching speed, but rather optimized operating regimes supported by advanced gate driver design, improved packaging, and robust field plate engineering. GaN HEMTs are, therefore, expected to see increasing adoption in medium- to high-voltage EV subsystems if system-level challenges such as current collapse mitigation (Current collapse refers to the temporary reduction in drain current of a GaN HEMT following high-voltage off-state or switching stress, caused by charge trapping in surface or buffer states that partially deplete the channel during subsequent on-state operation. A simplified schematic illustration of this phenomenon and a detailed discussion of the underlying mechanisms are provided in Section 6.1.1.), gate robustness, and EMI compliance are addressed in parallel. These insights provide clearer guidance for device manufacturers and EV system designers in aligning technology development with the practical constraints of next-generation high-density EV platforms.

In Malaysia, the transition toward electric mobility is gaining momentum, driven by national initiatives such as the National Energy Transition Roadmap (NETR) and the Low Carbon Mobility Blueprint (LCMB) [26,27]. These frameworks emphasize reducing carbon emissions, promoting renewable energy integration, and fostering a sustainable transportation ecosystem. Efforts are underway to strengthen domestic EV assembly, enhance charging infrastructure, and develop localized supply chains for supporting technologies [28]. However, the Malaysian market faces unique challenges, including cost sensitivity among consumers [29], tropical climatic conditions that place additional stress on power electronic systems [30], and the need to develop skilled manpower and localized manufacturing capabilities [31]. In this context, GaN HEMTs present a strategic opportunity: their ability to improve efficiency, reduce cooling requirements, and enable compact system designs could address several of these market-specific challenges if cost and reliability barriers are adequately managed. Against this backdrop, this review provides a comprehensive analysis of GaN HEMT technology at the device level in the context of EV power electronics.

The scope of this review is limited by the availability of published literature within the 2021–2026 timeframe and by the reliance on publicly available technology roadmaps, which are largely reported up to 2020. Relevant literature was identified using major scientific databases, including IEEE Xplore, ScienceDirect, Web of Science, and Scopus, with keywords related to GaN HEMTs, EV power electronics, gate driving, reliability, and ultra-wide-bandgap semiconductors. The initial search yielded a broad set of publications, which were subsequently screened based on relevance to EV applications, device structure, system-level challenges, and reliability considerations. Review and experimental papers with significant technical contributions were prioritized.

Figure 2 illustrates the conceptual organization and logical progression of this review. This manuscript is organized into nine sections. Section 1 provides the introduction. Section 2 reviews the evolution of power semiconductor devices for electric vehicle applications. Section 3 discusses the system-level challenges of power electronics in EVs. Section 4 presents various GaN HEMT device structures developed for power electronic applications. Section 5 reviews the state-of-the-art GaN discrete devices and automotive qualification. Section 6 addresses the reliability and operational challenges of GaN HEMTs in EV applications. Section 7 explores opportunities beyond GaN, focusing on emerging ultra-wide-bandgap semiconductor technologies. Section 8 summarizes the open challenges and future research opportunities. Finally, Section 9 concludes the manuscript.

2. Evolution of Power Semiconductors in EVs

Power electronic devices constitute the technological backbone of modern EV systems. Figure 3a illustrates the EV powertrain, showing how high-, medium-, and low-power modules interface the battery, motor/generator, onboard charger, and auxiliary loads through DC/DC and DC/AC converters across 400 to 800 V and 14 V buses. In the EV powertrain, GaN HEMTs are most suitable for the on-board charger AC/DC stage and the high-frequency DC/DC converters (400–800 V to 14 V), where their superior switching speed and low losses enable higher power density, while SiC devices remain dominant in the main traction inverter. Power devices govern the entire energy pathway from charging infrastructure to propulsion. These devices manage the bidirectional flow of energy between the grid and the battery during charging, and between the battery and the motor during traction and regenerative braking. High-performance power electronics enable efficient energy conversion, precise control, and effective distribution, ensuring that energy losses are minimized at every stage. Beyond vehicle performance, they also influence broader aspects such as system cost, long-term durability, and user acceptance of EV technology [32,33,34,35,36].

At the core of every power electronic converter lies the semiconductor switch, typically realized as MOSFETs, IGBTs, or high-electron-mobility transistors (HEMTs). The physical and electrical properties of the semiconductor material fundamentally determine the operational limits of these switches. Key device characteristics such as voltage blocking capability, on-state resistance, and switching speed are dictated by intrinsic material properties, including bandgap energy, critical electric field, electron mobility, and thermal conductivity [39,40]. These parameters in turn govern conduction and switching losses, efficiency under high-frequency operation, maximum operating temperature, and the overall scalability of the power electronic system [41,42,43].

Over the last three decades, the semiconductor landscape for power devices has undergone a notable transition. Si dominated the industry due to its well-established fabrication technology, mature supply chain, and cost-effectiveness. However, Si-based devices are increasingly constrained by fundamental material limits, especially in applications requiring high voltages, high temperatures, and fast switching speeds [44,45]. To address these challenges, the industry has gradually shifted toward WBG semiconductors, particularly SiC and GaN. Figure 3b compares the application voltage ranges, highlighting GaN dominance in low- to medium-voltage systems, SiC suitability for medium- to high-voltage applications, and their coexistence around the 600 to 900 V range relevant to EV and renewable energy systems. The roadmap for GaN power devices, illustrating the projected growth in market adoption from low-power consumer electronics toward high-power applications, is illustrated in Figure 3b. These materials offer superior material properties, including wider bandgap, higher critical BD field, and enhanced thermal conductivity, that enable devices with higher power density, greater efficiency, and reduced cooling requirements. This transition is reshaping the design of EV power electronics, enabling faster chargers, more compact inverters, and more reliable traction systems [37,46,47].

2.1. Silicon: The Industry Standard with Fundamental Limits

For decades, Si-based devices, including insulated gate bipolar transistors (IGBTs) and metal–oxide–semiconductor field-effect transistors (MOSFETs), have formed the cornerstone of power electronics. Their dominance stems from the maturity of Si as a semiconductor, the highly optimized fabrication infrastructure, and the low cost per ampere of current handling, which made them attractive for mass market adoption [48,49,50]. These devices have been deployed extensively in traditional automotive electronics, industrial motor drives, renewable energy systems, and consumer power supplies, where reliability, cost effectiveness, and scalability were the primary design considerations. However, Si’s intrinsic material properties impose strict limitations on its long-term viability for advanced applications such as EVs. With a bandgap of only 1.1 eV, Si devices exhibit higher intrinsic carrier concentrations at elevated temperatures, which increases leakage currents and restricts their maximum operating temperature. The relatively low critical electric field (0.3 MV/cm) requires thicker drift layers in high-voltage devices, leading to higher on-resistances and larger chip sizes.

In addition, the moderate thermal conductivity (150 W/m·K) hampers heat dissipation compared to wide-bandgap materials, necessitating complex thermal management strategies [51,52,53]. In practical terms, these material constraints manifest as higher switching and conduction losses, especially in high-frequency and high-voltage operation. For instance, Si IGBTs, while capable of handling high voltages, suffer from significant tail currents during switching, which increases switching energy losses [54,55]. Si MOSFETs, though faster, face challenges in scaling higher voltages without dramatic increases in conduction losses. Consequently, both device types demand bulky cooling systems and oversized passive components, which increase the size, weight, and cost of power electronic modules [56,57,58].

As EV architecture evolves toward higher efficiency, compactness, and fast-switching capabilities, the shortcomings of Si become more pronounced. Traditional Si devices are no longer optimal for meeting the stringent demands of next-generation traction inverters, OBCs, and fast charging infrastructure, where wide-bandgap semiconductors such as SiC and GaN provide superior performance. Thus, while Si IGBTs and MOSFETs will likely continue to serve in cost-sensitive and legacy applications, their role in cutting-edge EV power electronics is gradually diminishing [59,60,61].

2.2. Silicon Carbide: The First Wide Bandgap Breakthrough

SiC represents the first major technological breakthrough in WBG semiconductors for power electronics. With a bandgap of approximately 3.2 eV, a critical electric field strength of 3 MV/cm, and a thermal conductivity of 490 W/m.K, SiC possesses intrinsic material properties that far surpass those of conventional Si. These attributes enable the fabrication of devices capable of handling significantly higher voltages, temperatures, and switching frequencies with reduced energy losses [62,63,64,65]. From a device engineering perspective, the high BD field allows for thinner drift layers and smaller chip sizes, resulting in lower on-resistance per unit area. Meanwhile, superior thermal conductivity facilitates more effective heat dissipation, which is critical for compact, high-power-density EV systems. The commercialization of SiC MOSFETs over the past decade has driven their adoption in key automotive subsystems. Today, leading EV manufacturers such as Tesla, Lucid Motors, Hyundai, and BYD deploy SiC MOSFETs in traction inverters, OBCs, and DC-DC converters [66,67]. In contrast to GaN, which is still emerging in automotive power electronics, SiC has already achieved large-scale commercial deployment in EV traction inverters, where voltage ratings, robustness, and long-term reliability are the primary design drivers. As the core switching technology in high-power propulsion systems, SiC MOSFETs have become the industry benchmark for evaluating efficiency, thermal performance, and system durability in modern EV platforms.

The main advantage lies in their ability to drastically cut switching and conduction losses, thereby increasing inverter efficiency to above 98% in some architectures [68]. This reduction in power loss translates directly into practical benefits such as extended driving range, reduced cooling system size, and improved reliability. In addition, SiC devices are uniquely positioned to support the automotive industry’s transition to 800 V battery architecture, which enables ultra-fast charging capabilities (e.g., 10–15 min to reach 80% state of charge). Operating reliably beyond 1200 V, SiC MOSFETs provide the robustness and performance margins required for these next-generation high-voltage platforms [69,70,71]. The dominance of SiC in traction inverter applications is further reinforced by its proven capability to operate reliably at voltage ratings of 1200 V and above, enabling compact inverter designs with reduced conduction losses under high current operation. This robustness makes SiC particularly well suited for high-torque acceleration, regenerative braking, and sustained high-load driving conditions encountered in real-world EV operation. From an industry perspective, SiC currently represents the most mature wide-bandgap solution for high-voltage EV powertrains, offering a well-established reliability track record and qualification standards that align with automotive lifetime requirements. As a result, SiC is expected to remain the dominant technology for traction inverters in the near to midterm, while GaN adoption continues to focus on medium voltage subsystems such as on-board chargers and DC-DC converters. Despite their advantages, the broader diffusion of SiC technology still faces barriers. The cost of SiC wafers remains considerably higher than that of Si, primarily due to the challenges in growing large-diameter, defect-free SiC crystals. Furthermore, fabrication processes such as ion implantation and high-temperature annealing are more complex and less mature compared to the Si ecosystem, leading to higher device production costs. Global supply chain bottlenecks, with a limited number of SiC wafer suppliers, exacerbate cost and availability issues [72,73,74,75]. These economic constraints are particularly significant in cost-sensitive EV markets across Asia, where affordability remains a key adoption factor. As a result, while premium EV manufacturers continue to leverage SiC for performance differentiation, mass market adoption may depend on future breakthroughs in wafer manufacturing, process optimization, and economies of scale [76,77,78].

2.3. Gallium Nitride: Toward Compact and High-Frequency EV Power Electronics

GaN high-electron-mobility transistors (HEMTs) represent the next leap forward in WBG semiconductor technology, offering device characteristics that directly address the demands of compact, high-frequency power conversion. With a wide bandgap of 3.4 eV, GaN devices exhibit a much higher BD strength than Si, enabling operation at higher electric fields and reduced leakage currents. More importantly, the polarization effects in AlGaN/GaN heterostructures give rise to a two-dimensional electron gas (2DEG) channel at the interface. This 2DEG, characterized by electron mobilities exceeding 1500 cm²/Vs and sheet charge densities > 10¹³ cm⁻², allows for extremely high current conduction at very low on-resistance [79,80,81]. These intrinsic advantages translate into ultrafast switching speeds and low conduction losses, making GaN devices ideally suited for high-frequency, high-efficiency power converters. In the EV domain, GaN is especially attractive for subsystems operating below 900 V, such as OBCs, DC-DC converters, and auxiliary power modules [82,83,84]. By enabling switching frequencies in the MHz range, GaN drastically reduces the size of passive components like inductors, capacitors, and transformers that typically dominate the volume and weight of power converters. This frequency scaling results in lighter, smaller, and more cost-effective systems, which directly improves the EV packaging flexibility and vehicle efficiency [85,86,87]. Additionally, GaN’s inherently low switching losses reduce heat generation, which in turn lowers cooling requirements, simplifying thermal management and enabling the use of more compact cooling systems [88,89,90]. Several commercial demonstrations already highlight GaN’s promise in EV applications. For instance, leading Tier-1 suppliers and semiconductor manufacturers have reported GaN-based OBCs achieving efficiencies >96%, while offering up to 40% reduction in size and weight compared to Si- or SiC-based solutions [91,92,93,94]. Such improvements align perfectly with automakers’ push toward higher power density and lightweight platforms. Nevertheless, challenges remain for widespread GaN adoption in EVs. Most GaN devices are currently limited to blocking voltages below 900 V, restricting their applicability in traction inverters that require robust operation at ≥1200 V, where SiC currently dominates [95,96,97]. Although recent studies have demonstrated GaN HEMTs with blocking voltages up to 1200 V, these devices are still at an early stage of commercialization, and their adoption in 800 V EV traction inverters is limited compared to the well-established SiC platform. Figure 4 illustrates the evolution of commercial GaN power device voltage ratings, highlighting key milestones in practical technology adoption rather than laboratory-scale demonstrations [98]. Early commercial GaN devices were limited to sub 300 V operation, followed by the introduction of 600–650 V devices that enabled widespread deployment in offline power converters and EV auxiliary systems. More recently, the emergence of 900 V and early-stage 1200 V GaN products reflects ongoing efforts to extend GaN technology toward higher voltage automotive powertrain applications. Restricting the timeline to commercially released devices provides a clear and unambiguous view of GaN technology maturation and industrial readiness.

Furthermore, GaN reliability under long-term automotive stressors such as high junction temperatures, repeated thermal cycling, and electrical overstress remains an active area of research. Packaging also poses significant challenges, as GaN devices generate high thermal flux densities due to their small die size, requiring advanced substrates, interconnects, and cooling strategies to ensure robust performance [99,100,101,102]. Cost competitiveness is another limiting factor; although GaN-on-Si substrates have improved manufacturability, large-area, defect-free GaN epitaxy remains more expensive compared to mature Si and even SiC processes [103,104,105,106,107].

In summary, the evolution of power semiconductors for EVs reveals a clear application-driven trade-off as shown in

Table 2. Comparison of Si, SiC and GaN devices for EV application.

Parameter	Silicon (Si: MOSFET, IGBTS)	Silicon Carbide (SiC: MOSFETs, Schottky Diodes)	Gallium Nitride (GaN: HEMTs)
Switching Speed	Moderate [54,55,56,57,58]	High [66,67,68]	Very high (MHz range) [82,83,84]
Voltage range in EVs	Low–Medium (<1200 V) [54,55,56,57,58]	High (≥1700 V, 800 V) [69,70,71]	Medium (<900 V, OBC/DC-DC) [82,83,84,85]
Efficiency	Moderate (limited by conduction and switching losses) [56,57,58]	Very high (>98% in traction inverters) [66,67,68]	Very high (>96% in OBCs, DC-DCs) [85,86,87]
Thermal Management	Requires bulky cooling [56,57,58]	Better heat dissipation [62,63,64,65]	Easier cooling, but high thermal flux density [88,89,90]
Main EV applications	Legacy modules, cost-sensitive systems [48,49,50]	Traction inverters, fast chargers, high-voltage OBCs [66,67,68,69,70,71]	OBC, DC-DC converters, auxiliary modules [85,86,87]
Advantages	Mature, low-cost, well-established ecosystem [48,49,50]	High voltage capability, robustness, supports 800 V EVs [66,67,68,69,70,71]	High-frequency switching, compact/lightweight systems [82,83,84,85,86,87]
Limitations	High losses at high-voltage/frequency, bulky passive components [52,53,54,55,56,57,58]	High wafer/device cost, limited supply chain [72,73,74,75]	Voltage limited (<900 V), reliability and packaging challenges [95,96,97,98,99,100,101,102]
Commercial Adoption	Older EV platforms, low-voltage parts [48,49,50,51,52,53,54,55,56,57,58,59]	Tesla, Lucid, Hyundai, BYD (traction inverters, OBCs) [66,67,68]	Tier-1 suppliers in OBCs, DC-DC (size/weight reduced by 40%) [91,92,93,94]

. Si remains the most cost-effective but suffers from fundamental physical limitations. SiC has become the material of choice for high-voltage traction inverters and 800 V architectures, offering efficiency and robustness at a premium cost. GaN, with its superior switching performance, high frequency capability, and compactness, is emerging as the enabling technology for OBCs, DC-DC converters, and auxiliary systems in mid-voltage EV applications. To fully harness the advantages, it is essential to review the fundamental structure, operating principles, and performance metrics of GaN HEMTs, which will serve as the basis for evaluating their role in shaping the next generation of EV subsystems.

While the material- and device-level advantages of wide-bandgap semiconductors, particularly GaN HEMTs, clearly enable higher efficiency and power density in EV subsystems, their adoption also introduces new challenges that extend beyond the device itself. The ultra-fast switching behavior, low gate voltage margin, and strong sensitivity to parasitics fundamentally alter the interaction between the power device, gate driver, packaging, and surrounding system components. As EV power electronics move toward higher levels of integration and increased operating frequencies, these interactions become critical determinants of overall system reliability, electromagnetic compatibility, and long-term performance. Consequently, a comprehensive evaluation of GaN HEMTs must extend from device evolution to the associated system-level challenges, which are discussed in the following section.

3. System-Level Challenges of Power Electronics in Electric Vehicles

Electric vehicles rely on advanced power electronics to manage energy between the battery, motor, and auxiliary systems. WBG devices offer higher efficiency, faster switching, and greater power density, but realizing these benefits introduces system-level challenges, including thermal management, efficiency frequency trade-offs, EMI (electromagnetic interference) mitigation, reliability, compact packaging, and cost. Addressing these requires coordinated device and system design to meet EV performance, durability, and safety requirements.

3.1. Thermal Management and Power Density

The drive toward compact, high-power-density power modules in EVs stresses thermal management capabilities. As power converters and inverters shrink in size and increase in power, the heat flux per unit area rises, making it difficult for conventional substrates and cooling methods to keep junction and case temperatures within safe limits. Indeed, conventional molding compounds, die attaches, and solder joints degrade under the sustained high temperatures typical of wide-bandgap (WBG) devices, causing reliability risks such as solder fatigue, die attach creep, bond wire lift off, and package delamination [108]. WBG devices help by enabling higher thermal conductivity and higher tolerated junction temperatures compared to silicon, which reduces conduction and switching losses and eases part of the cooling burden. However, even with these materials, heat dissipation in compact EV power modules remains a major bottleneck, particularly under high-power or high-duty cycle conditions [109]. Thus, advanced cooling strategies (e.g., integrated cold plates, optimized heat spreaders, and liquid or two-phase cooling) and careful thermal modeling (e.g., thermal forecasting methods) [110] are crucial for sustaining reliability and extending lifetime in EV power electronics.

3.2. Efficiency Versus Switching Frequency Trade-Off

One of the major motivations for using WBG semiconductors in EV power electronics is their ability to support higher switching frequencies, which enables the reduction in passive component size (inductors and capacitors) and overall module volume, which is a key requirement for compact, high-power-density EV [111]. However, increasing switching frequency introduces a trade-off: higher dv/dt and di/dt at switching instants cause elevated switching losses and higher thermal stress, which undermines efficiency gains and can exacerbate thermal management challenges [112]. Moreover, maintaining very high efficiency across varying load conditions typical of EV operation (acceleration, regenerative braking, partial load, and idle) is non-trivial. This calls for sophisticated gate-drive design, optimized switching strategies, and robust control algorithms to minimize losses while sustaining performance under dynamic conditions [113].

3.3. Electromagnetic Interference (EMI) and Parasitic Effects

The fast switching enabled by WBG devices, while advantageous for efficiency and size, significantly increases ringing, voltage overshoot, and switching transients (high dv/dt, di/dt). These lead to electromagnetic interference (EMI) and common-mode noise, which can interfere with sensitive control electronics, sensors, communication buses, and degrade overall system stability [114]. Additionally, packaging and module design, especially if traditional wire bonding and molding are used, can introduce parasitic inductance and capacitance. These parasitics exacerbate EMI, leading to switching inefficiencies (overshoot or ringing), and may cause reliability issues (e.g., dielectric stress or gate driver stress) [115]. One of the major drawbacks associated with GaN HEMTs in high-frequency EV power converters is their susceptibility to false turn-on caused by EMI. The extremely high dv/dt and di/dt during switching events induce strong Miller coupling through the gate to drain capacitance, which can unintentionally raise the gate voltage above the threshold level, particularly in half-bridge configurations. This issue is further exacerbated by the low threshold voltage and absence of an intrinsic body diode in enhancement-mode GaN devices. To mitigate EMI induced false turn-on, several strategies have been widely adopted, including the use of active Miller clamp circuits, negative gate bias during turn-off, optimized gate resistance, and careful PCB layout to minimize gate loop inductance and parasitic coupling. Among these, active Miller clamp techniques are particularly effective in suppressing unintended gate voltage excursions without significantly compromising switching speed, making them well suited for high-density EV power electronics. Mitigating EMI and parasitics thus becomes a key system-level challenge, requiring careful PCB/layout design, advanced packaging techniques (e.g., low inductance module packaging or embedded substrates), shielding strategies, and EMI filters, all of which can counteract the size/weight advantages sought from WBG devices [116].

3.4. Reliability Under Automotive Conditions

Reliability remains a central hurdle for WBG devices in EVs because automotive environments impose multiple, simultaneous stresses that are more severe and varied than in typical industrial applications. EV power converters are routinely subjected to frequent power cycling due to acceleration, regenerative braking, and charging cycles. These repeated transitions cause thermal cycling, where large temperature swings (from cold startup to high junction temperatures during high load) induce mechanical fatigue in materials with differing coefficients of thermal expansion, such as solder, die attach, substrate, and wire bonds. This mismatch leads to delamination, cracking, and solder joint fatigue, which are primary failure mechanisms in packaged power modules [117]. In addition to mechanical stress, electrical stress mechanisms unique to WBG devices further complicate reliability. In GaN HEMTs, dynamic charge trapping, threshold voltage instability, and gate leakage can degrade performance over time, especially under high-frequency switching and high electric field operation typical of EV converters. These effects not only change key performance metrics like on-resistance and threshold voltage but can ultimately lead to device failure if not properly managed. Environmental conditions such as humidity and temperature cycling also affect reliability by accelerating the degradation of passivation and insulation layers, making traditional silicon-based qualification tests inadequate for WBG devices. For this reason, rigorous, WBG-specific qualification procedures, including power cycling, thermal cycling, high-temperature operating life (HTOL), high-humidity reverse bias tests, and gate oxide stress tests, are essential to characterize and ensure long-term performance under automotive conditions [118]. Finally, while WBG semiconductors inherently offer higher breakdown fields and greater thermal capacity than silicon, the surrounding packaging materials (solder, encapsulants, die attach layers) often become the limiting factor for reliability unless packaging innovations also evolve. Without targeted improvements in materials and module design to handle these environmental and operational stresses, long-term reliability lags behind WBG’s inherent device capability.

3.5. System Integration, Packaging Complexity and Cost

Realizing the full advantage of WBG devices in EVs requires highly integrated power modules that embed semiconductors, gate drivers, sensors, bus bars, and cooling channels in a compact package. Such integration demands advanced packaging technologies, including low inductance substrates, sintered die attach, embedded gate drivers, and integrated thermal cooling features, which dramatically increase design complexity. Moreover, these advanced packaging and manufacturing methods come at a cost: material premiums (e.g., WBG substrates, silver/copper sinter die attach, and specialized substrates), specialized cleanroom fabrication, qualification cycles, and long development timelines create economic barriers, especially for smaller original equipment manufacturers (OEMs) or cost-sensitive vehicle segments [119]. The economics of scale, supply chain volatility, and required investment in validation/testing (power cycling, reliability, EMI, and thermal) further constrain widespread adoption, even though WBG offers superior technical performance.

3.6. Gate Driving and Control Challenges

Gate driving represents a critical system-level challenge in EV power electronics, particularly with the increasing adoption of WBG devices such as GaN HEMTs. Unlike conventional Si MOSFETs, GaN transistors exhibit ultra-fast switching speeds, low threshold voltages, and gate structures with limited voltage tolerance, which significantly narrows the safe operating margin for reliable gate control. As a result, gate drive design for GaN devices is far more sensitive to timing errors, voltage overshoot, and parasitic effects [120,121]. The extremely high switching slew rates (dv/dt and di/dt), often exceeding tens of V/ns and A/ns, impose stringent requirements on gate driver timing accuracy, common-mode transient immunity (CMTI), and isolation robustness. Inadequate CMTI or excessive gate loop inductance can induce severe gate ringing, false turn-on through Miller coupling, or unintended cross conduction in half-bridge configurations, leading to increased switching losses or device failure [122,123,124]. These issues are particularly pronounced in enhancement-mode GaN HEMTs due to their low threshold voltage and absence of a robust intrinsic body diode.

Furthermore, EV inverters and onboard chargers operate in harsh electromagnetic environments characterized by high power levels, compact layouts, and multi-phase operation. Under such conditions, precise dead time control becomes critical to avoid shoot-through while simultaneously minimizing reverse conduction losses. Gate drivers must, therefore, incorporate advanced protection and control features such as Miller clamps, active gate shaping, soft turn-off during fault conditions, and fast short-circuit or desaturation detection, even though GaN devices exhibit limited short-circuit withstand capability [125,126,127].

As EV systems continue to push toward higher switching frequencies to improve power density and efficiency, gate drivers are also subjected to increased thermal stress and tighter synchronization requirements across multi-phase converter architectures. Consequently, optimized gate-drive circuitry, careful PCB layout with minimized parasitics, Kelvin source connections, and device-specific driving strategies are essential to fully exploit the performance advantages of GaN HEMTs while maintaining system reliability [128,129]. Recent studies and reviews emphasize that gate-drive design is no longer a peripheral consideration but a core enabler for safe, high-performance GaN-based EV power converters [130,131].

Beyond discrete gate-drive circuit optimization, the emergence of GaN-specific gate driver ICs has become a critical factor in achieving reliable system-level operation in EV power converters. These ICs are designed to address the unique challenges of GaN HEMTs by offering ultra-high common-mode transient immunity (often exceeding 100–150 kV/µs), sub-nanosecond propagation delay matching, and tightly controlled gate voltage clamping to prevent overdrive and false turn-on. Automotive-grade GaN gate driver ICs increasingly integrate advanced features such as active Miller clamping, programmable dead time, fault reporting, soft turn-off under overcurrent events, and reinforced galvanic isolation compliant with AEC-Q100 and functional safety standards. The co-design of GaN HEMTs with such dedicated gate driver ICs is, therefore, essential for ensuring robustness, long-term reliability, and safe operation of high-frequency, high-power-density EV systems, including traction inverters, onboard chargers, and bidirectional DC–DC converters.

3.7. Challenges of Bidirectional Power Flow in V2G-Enabled EVs

With the increasing adoption of Vehicle-to-Grid (V2G) architectures, system-level challenges in EV power electronics are becoming more pronounced due to sustained bidirectional power flow. Unlike conventional unidirectional operation, bidirectional converters and inverters are subjected to frequent power reversals, asymmetric loading conditions, and extended operating durations in both rectification and inversion modes [132]. These operating conditions impose additional electrical stresses, including repeated high dv/dt switching, increased circulating currents, and enhanced electromagnetic interference, and elevated thermal cycling caused by continuous charge–discharge operation [133]. Furthermore, bidirectional operation tightens constraints on gate driver robustness, dead-time control, protection coordination, and long-term device reliability [134]. As V2G penetration increases in modern EV ecosystems, addressing these system-level stresses through improved converter topologies, advanced control strategies, and reliability-aware design becomes a critical research and industry priority.

Taken together, these challenges, as illustrated in Figure 5, reveal that transitioning to high-performance, high-density power electronics in EVs is not merely a matter of substituting silicon devices with WBG transistors. Rather, it requires a holistic system-level design approach encompassing thermal design, packaging materials, EMI mitigation, control strategies, test/qualification standards, and cost/volume economics. While WBG materials such as SiC and GaN promise lower losses, higher switching frequency, and compact form factors, thus supporting increased range, faster charging, and lighter motor inverter modules, realizing these gains depends strongly on concurrent advances in packaging, thermal engineering, reliability testing, and module integration. Thus, only through coordinated material-, device-, and system-level innovation can EV WBG power electronics deliver the performance, durability, and cost effectiveness demanded for widespread adoption.

4. GaN HEMT Structures for Power Electronics

GaN HEMTs have evolved through diverse structural innovations to meet the stringent requirements of modern power electronics, particularly in electric vehicles and high-efficiency power conversion. The electrical behavior of GaN HEMTs in power electronics can be described using a combination of analytical, physics-based, and equivalent circuit models. Compact models often adapt standard MOSFET equations (e.g., LEVEL 3 SPICE models) for static and dynamic characteristics, enabling efficient circuit simulation and parameter extraction [135]. Large signal models further incorporate nonlinear current sources and parasitic elements to capture real operating conditions [136]. Physics-based analytical models, derived from Schrodinger–Poisson formulations, provide fundamental expressions for two-dimensional electron gas (2DEG) charge density, capacitances, and current voltage relationships [137]. Electrostatic models that solve Poisson’s equation with polarization effects describe channel formation and field distributions in heterostructures. These modeling frameworks and their governing equations form the basis for understanding and designing GaN HEMTs for EV power conversion applications. Depending on the application demands, such as normally off operation, high breakdown voltage, thermal robustness, and minimized current collapse, different device architectures have been developed. These include conventional depletion-mode and enhancement-mode transistors, gate-engineered designs like gate recess HEMTs, hybrid structures such as cascode GaN HEMTs, and advanced epitaxial approaches including high-Al-content barriers, superlattice buffers, and polarization-engineered back barriers. Each of these structures offers unique advantages and trade-offs, forming the foundation for next-generation high-performance GaN power devices.

4.1. Normally on GaN HEMT (Depletion Mode)

Conventional AlGaN/GaN HEMTs are illustrated in Figure 6a. They operate in depletion mode (normally on) due to the strong spontaneous and piezoelectric polarization effects at the AlGaN/GaN heterojunction. The conduction band energy diagram is illustrated in Figure 6b. The thin AlGaN barrier induces a high density 2DEG at the interface, which enables a highly conductive channel with exceptional sheet carrier density (10¹³ cm⁻²) and high electron mobility (>1500 cm²/V·s). This results in ultra-low RON and excellent high-frequency performance, making these devices ideal for RF applications and an important baseline for later GaN innovations [138,139]. The 2DEG sheet carrier density at the AlGaN/GaN interface is given by Equation (1) [140],

$${\mathrm{n}}_{2\mathrm{DEG}}={\displaystyle \frac{{\mathrm{\sigma }}_{\mathrm{pol}}-{\mathrm{Q}}_{\mathrm{surf}}}{\mathrm{q}}}$$

(1)

where σ_pol is the net polarization charge (spontaneous + piezoelectric), Q_surf is the surface/interface trap charge and q is the elementary charge. When the polarization charge dominates over surface trap charges, a finite 2DEG density exists even at zero gate bias. As a result, the channel remains conductive at V_G = 0, yielding a negative threshold voltage and normally on operation, as illustrated in Figure 6b. Under low drain bias, the drain current I_D can be approximated by Equation (2) [140],

$${\mathrm{I}}_{\mathrm{D}}={\mathrm{qn}}_{2\mathrm{DEG}}\mathrm{\mu }\times {\displaystyle \frac{\mathrm{W}}{\mathrm{L}}}\times {\mathrm{V}}_{\mathrm{DS}}$$

(2)

where µ is the electron mobility, W is the gate width, and L is the gate length. This relation highlights the direct dependence of drain current on polarization-induced charge density, explaining the inherently conductive nature of normally on GaN HEMTs.

The gate structure is typically based on a Schottky metal–semiconductor junction; however, a thin gate dielectric could be added to improve the device reliability [141]. However, their inherent normally on characteristic presents a fundamental challenge for power switching in EVs. Since the device conducts current at zero gate bias, it requires a negative gate voltage to turn off. This “fail unsafe” condition means that if the gate driver fails, the transistor remains on, leading to uncontrolled current conduction, a critical safety hazard in EV power converters and traction inverters where isolation and fast fault response are mandatory [142,143].

In addition, conventional AlGaN/GaN HEMTs suffer from surface traps and interface states, which induce current collapse and dynamic RON increase under high-voltage switching transients. While passivation layers and field plate engineering can partially mitigate these effects, the dynamic performance degradation remains problematic for the stringent reliability standards of automotive applications. Consequently, although depletion-mode GaN HEMTs were historically significant in RF and early power device prototypes, they are considered unsuitable for EV power electronics. Modern EV systems demand normally off (enhancement-mode) GaN solutions such as p-GaN gate HEMTs, recessed gate structures, or cascode configurations, which provide inherent safety, reliable turn off, and compliance with automotive qualification standards.

4.2. Enhancement Mode (E-Mode, Normally Off) GaN HEMT

4.2.1. p-GaN Gate HEMT

The p-GaN gate HEMTs implement a thin, p-type GaN cap layer immediately beneath the gate contact to convert the native depletion-mode AlGaN/GaN HEMT into an enhancement-mode (normally off) device, as illustrated in Figure 7a. The incorporation of the p-GaN layer elevates the conduction band of the AlGaN, resulting in the depletion of the two-dimensional electron gas (2DEG) as shown in Figure 7b. The p-GaN cap establishes a built-in depletion region that counteracts the polarization-induced 2DEG beneath the gate, so that at zero gate bias, the channel beneath the gate is depleted and the device remains off. The resulting threshold voltage can be qualitatively described as in Equation (3) [144],

$${\mathrm{V}}_{\mathrm{th}}={\displaystyle \frac{{\mathrm{qn}}_{2\mathrm{DEG}}{\mathrm{d}}_{\mathrm{AlGaN}}}{{\mathrm{\epsilon }}_{\mathrm{AlGaN}}}}+{\displaystyle \frac{{\mathrm{\Phi }}_{\mathrm{p}-\mathrm{GaN}}}{\mathrm{q}}}$$

(3)

where ${\mathrm{d}}_{\mathrm{AlGaN}}$ is the AlGaN barrier thickness, ${\mathrm{\epsilon }}_{\mathrm{AlGaN}}$ is the permittivity of the barrier layer, and ${\mathrm{\Phi }}_{\mathrm{p}-\mathrm{GaN}}$ represents the effective potential introduced by the p-GaN gate. The presence of the p-GaN layer increases the gate depletion capability, shifting the threshold voltage toward positive values. Consequently, the 2DEG density under the gate is effectively reduced to near zero at V_G = 0, resulting in normally off behavior, as depicted in Figure 6b. Channel formation is restored only when a sufficient positive gate voltage is applied to overcome the depletion imposed by the p-GaN gate and re-establish the 2DEG.

A positive gate bias forward biases the p-GaN/metal junction and restores conduction, producing a practical positive threshold voltage in the range of +1.5 to +2.5 V for most commercial parts. This approach preserves the lateral 2DEG conduction path outside the gate area, so p-GaN devices retain the low RON and high frequency advantages of GaN while delivering the fail-safe normally off behavior required by power converters [145,146,147].

In practice, p-GaN HEMTs have become the industry standard for GaN power switching offered by multiple vendors and qualify for many automotive/industrial power applications, because they provide a straightforward, manufactural route to E-mode operation without the additional chip count of cascode designs. Leading vendors such as Infineon market their CoolGaN lateral p-GaN HEMTs as automotive-qualified power devices, having completed extensive reliability and qualification testing for EV and industrial applications [148]. While cascode GaN HEMTs mitigate several p-GaN gate reliability issues by relying on a Si MOSFET gate interface, they introduce additional parasitic effects, switching losses, and thermal complexity, making p-GaN and cascode architectures a fundamental trade-off between gate robustness and high-frequency performance.

Furthermore, multiple sources confirm GaN HEMTs are now commonly deployed in EV subsystems like OBCs and high-voltage DC-DC converters, thanks to their high efficiency, high switching frequency, and compact design [149,150]. However, p-GaN introduces its own materials and reliability challenges: threshold voltage (Vth) instability (bias and temperature dependent drift), limited gate drive window (forward gate bias and gate BD constraints), and dynamic Vth shifts under large drain bias or pulsed stress. Gate bias and temperature-dependent Vth instability (bias-temperature instability, BTI) can exceed 0.6 V under stress, complicating gate-drive design. The allowable gate drive window is constrained, thus aggressive forward biasing risks gate Schottky junction degradation and BD, while insufficient bias can propagate false turn-on. Moreover, dynamic effects under pulsed or high drain bias stress driven by charge trapping in the gate stack led to transient Vth shifts and variations in on-resistance, all of which undermine device stability in EV power systems [151,152,153].

Recent device engineering has therefore focused on raising Vth and expanding gate drive robustness through techniques such as optimized Mg doping and compensation in the p-GaN layer, insertion of thin oxidation or dielectric interlayers at the gate to mitigate electric field peaks, hybrid p-GaN/MIS gate stacks to suppress drain-induced threshold instabilities, and selective regrowth or cap engineering to reduce trap densities. These improvements have enabled p-GaN HEMTs to reach higher blocking voltages (many commercial parts in the 650–900 V class and recent research demonstrations approaching and exceeding 900 V are listed in

Table 3. Reported studies on p-GaN Gate GaN HEMT.

Ref 1	Year	Vth (V)	BD (V)	Key Results	Main Limitations	EV Relevance
[144]	2022	1.73	1205	Demonstrated p-NiO gate on AlGaN/GaN HEMT, achieving normally off operation with stable Vth and very small Vth shift under stress. High BD voltage >1200 V on Si substrate.	Thermal conductivity of Si substrate inferior to SiC; p-NiO integration still in early research stage; long-term stability not fully validated.	Highly relevant: Shows potential of alternative p-NiO gate designs for >1 kV class HEMTs on Si, offering cost-effective solutions for EV power electronics.
[146]	2021	3.9	1200	Introduced a drain-side thin p-GaN structure that reduces peak electric fields and suppresses dynamic RON degradation. Achieved stable high-voltage operation with BV = 1200 V, demonstrating EV suitable robustness.	Fabricated on sapphire substrate, which limits thermal conductivity vs. SiC; long-term stress reliability data limited.	Highly relevant: shows that optimized p-GaN design can combine normally off behavior with >1 kV BD voltage, directly applicable to EV inverters and chargers.
[147]	2023	1.5	776	Introduced an active passivation scheme that dynamically screens surface traps, reducing current collapse and dynamic RON. Demonstrated stable switching and improved gate robustness under stress.	The work does not push BD voltage > 1 kV; the study focuses mainly on surface/reliability engineering.	Important for EV since dynamic RON stability and suppression of trapping are critical under high frequency hard switching.
[154]	2024	7.1	1980	Demonstrates very high Vth and nearly 2 kV off-state BV in a p-GaN gated device, promising gate robustness and blocking.	Limited public experimental detail in summary; long-term reliability and reproducibility need verification.	Directly relevant: shows p-GaN can be engineered for near 2 kV class blocking when combined with appropriate epi and geometry.
[155]	2024	0.9	2655	Introduced super junction charge balance to achieve record high BV and stable dynamic performance	Fabrication complexity; needs precise charge balance control	Highly relevant: BV > 2.5 kV makes it suitable for EV traction inverters and onboard chargers requiring >1200 V devices

¹ Studies within the same technology report comparable trends; representative works are listed individually for clarity.

. Thus, progressively improving gate reliability and dynamic on-resistance stability; nevertheless, careful gate drive design, thermal management, and robust qualification remain essential for automotive deployment [154,155].

4.2.2. Gate Recess HEMT

Gate recess HEMTs (recessed gate high-electron-mobility transistors) are enhancement-mode GaN devices in which part of the AlGaN barrier layer is locally etched (recessed) under the gate region, thereby reducing or removing the polarization-induced two-dimensional electron gas (2DEG) under zero gate bias, as illustrated in Figure 8. By adjusting how deeply and uniformly the AlGaN is recessed, one can tune the threshold voltage Vth to a positive value, making the device normally off. This approach has the advantage of being relatively simple in concept and fabrication (avoids needing a full p-GaN cap) and gives good controllability of Vth by varying recess depth or etch profile.

However, this simplicity comes with significant drawbacks: the etching process typically introduces damage at the AlGaN surface or sidewalls, causes interface roughness, increases trap densities, and degrades electron mobility under the gate region. These imperfections lead to reliability issues such as threshold voltage instability (especially under stress or temperature), increased gate leakage, lower maximum drain current, and worse dynamic behavior under high-frequency switching. Because of these concerns, recess gate GaN HEMTs are less common in commercial power modules; they are more often found in research prototypes, where careful process control (low damage etching, wet/chemical cleanings, surface treatments, and dielectric passivation) can partially mitigate the damage. Recent research has demonstrated promising results, which are listed in

Table 4. Reported studies on gate recess GaN HEMT.

Ref 1	Year	Vth (V)	BD (V)	Key Results	Main Limitations	EV Relevance
[156]	2021	1.5	1447	Introduced ZrOx trapping layer in gate stack + partial recess; achieved normally off operation with low RON, reduced gate leakage, and stable threshold.	Threshold stability over long-term stress still under evaluation, potential reliability concerns with ZrOx trapping dynamics under high temperature.	Strong candidate for EV inverters and converters, since it combines low RON and >1.4 kV BV with normally off operation.
[157]	2025	2.6	830	Demonstrated that thinner AlGaN barriers improve normally off operation (higher Vth) but reduce 2DEG density, impacting RON. Optimized design achieved a balance between positive Vth, low RON, and reasonable BV.	BD voltages below 1.2 kV limit direct EV traction inverter use; experimental validation limited compared to simulations.	Relevant for EV converters/OBCs where normally off operation + reliability are critical, though BV needs further enhancement for >1200 V class
[158]	2023	2	1190	Demonstrated precise recessed gate formation by atomic layer etching (ALE) plus a gate field plate. Achieved high drain current (608 mA/mm), low surface damage, improved threshold control, and BV = 1190 V at 1 mA/mm.	Long-term reliability and performance under hard switching not fully characterized. Process complexity (ALE + field-plate alignment) may affect manufacturability.	Highly relevant, shows a practical recessed gate MIS-HEMT route to reach 1.2 kV class blocking with normally off operation and low RON, pending reliability and large-area manufacturability validation.

¹ Studies within the same technology report comparable trends; representative works are listed individually for clarity.

, for example, atomic layer etching (ALE) methods yielding recess gates with minimal surface roughness and high BD voltage (1.1–1.2 kV) in MOS-HEMT/MIS-HEMT structures, and threshold voltages of +2.0 V or more with good on/off current ratio [156,157,158]. But despite this progress, achieving consistently reliable devices under automotive stress (thermal cycling, high drain bias swings, etc.) remains a challenge [159].

4.2.3. Cascode GaN HEMT

Cascode GaN HEMTs use a composite structure pairing a normally on lateral GaN HEMT (depletion mode) in series with a low-voltage Si MOSFET, as depicted in Figure 9. The MOSFET serves as the gate drive interface when the MOSFET is off. It effectively pulls the GaN gate to a negative or zero potential, turning the GaN device off. When the MOSFET is on, it allows the GaN device to conduct. This yields a normally off overall switch, combining the high electron mobility, low RDS(on) fast switching, and high critical field of GaN (for the power device portion) with the robust and well-understood drive and safety behavior of Si MOSFETs (for the gate control). Traditional cascode GaN devices have been commercially available in the 600 V to 900 V range. More recently, research and industry prototypes have pushed cascode GaN devices toward 1200 V and higher. For example, ref. [160] shows a device with a collapse voltage of 1200 V, using a high-voltage GaN HEMT connected in cascode with a low-voltage Si MOSFET to achieve normally off operation with good on-resistance and threshold behavior. The cascode structure enables using existing depletion-mode GaN HEMT wafers with minimal changes in device growth, avoiding the complexity of p-GaN or gate recess processes. Also, it offers improved safety (normally off) without requiring negative gate voltages, can achieve high BD voltage when the MOSFET is rated appropriately, and offers margin in gate drive and thermal design. Some of the latest works on cascode GaN HEMT are listed in

Table 5. Reported studies on cascode GaN HEMT.

Ref 1	Year	Vth (V)	BD (V)	Key Results	Main Limitations	EV Relevance
[160]	2025	2	1200	Introduced polarization super junction (PSJ) concept in GaN, using cascode to achieve normally off operation. Device shows BV = 1200 V, low dynamic RON, and stable switching. Highlights better electric field distribution due to PSJ design.	Cascode introduces parasitics and packaging complexity; BV capped at 1.2 kV, which may not be sufficient for traction inverters (>1.7 kV)	Strong EV relevance for OBC, 400–800 V and DC–DC converters, but less suitable for main drive inverters without scaling to higher BV.
[161]	2019	1.2	1200	Achieved 1200 V BV on cascode by combining GaN E-mode control with SiC high-voltage handling.	Hybrid structure; higher parasitics from SiC JFET; integration challenges.	Compatible with EV fast chargers and traction inverters requiring >1 kV operation.
[162]	2025	1.3	970	Cascode achieved higher BV than standalone p-GaN HEMT (784 V), improved switching, stable +1.3 V Vth	BV < 1.2 kV, needs optimization for EV traction	Promising for 650–900 V EV applications (onboard chargers, auxiliary systems)

¹ Studies within the same technology report comparable trends; representative works are listed individually for clarity.

[161,162].

Parasitic inductances and capacitances due to the two-chip arrangement (GaN + Si MOSFET + packaging interconnects) degrade switching speed, increase switching losses, and make layout more challenging. The MOSFET often must endure voltage stress (its drain source must be rated for the full device voltage), so its design becomes non-trivial. Heat dissipation and thermal management must address both parts; thermal coupling and mismatch between GaN and MOSFET can affect reliability. Vendors like Transphorm and other GaN power semiconductor manufacturers utilize cascode designs to deliver normally off behavior for applications including OBCs, DC-DC converters, and converters for power supplies where safety, reliability, and EV/industrial qualification are needed.

4.3. Advanced Barrier/Buffer Design

Barrier engineering plays a critical role in enhancing the performance, reliability, and scalability of GaN HEMTs for power electronics. The barrier layer directly influences the two-dimensional electron gas (2DEG) density, threshold voltage stability, gate control, and overall device robustness. Conventional AlGaN/GaN heterostructures rely on polarization-induced charge at the AlGaN/GaN interface to form a high-density 2DEG, but face limitations such as current collapse, gate leakage, and threshold voltage instability under high-voltage switching. Advanced barrier designs have therefore emerged to address these challenges and push GaN HEMTs toward automotive-grade and high-power switching applications.

4.3.1. High-Al-Content AlGaN Barriers

Barriers with elevated Al mole fraction (AlxGa1-xN with x = 0.25–0.40 or even higher) are increasingly explored in GaN HEMTs to enhance device performance. The reasons, trade-offs, and mitigation strategies are well documented in the recent literature. Higher Al content increases both spontaneous and piezoelectric polarization in the AlGaN layer, which boosts the sheet charge of the 2DEG at the AlGaN/GaN interface. This raises 2DEG density, leading to higher channel current and lower on-resistance. Recent studies have explored AlGaN barriers with significantly higher Al mole fractions to enhance BD performance. For instance, Al0.64Ga0.36N channel HEMTs with field plate structures have demonstrated BD voltages exceeding 3 kV prior to passivation and sustaining around 2 kV after passivation, while maintaining a low dynamic RON increase (<10%) during switching stress [163]. These results highlight the potential of ultra-high-Al-content barriers for kV class power switching applications, though at the expense of reduced channel mobility. In the paper [164], the authors designed an AlGaN barrier stack without Au metallurgy, using Al₀.₄Ga₀.₆N for the barrier and Al₀.₁Ga₀.₉N as a lower layer, grown on a Si substrate. The HEMTs show high reverse blocking voltage (2 kV) and demonstrate that Al% around 40–60% in the barrier layers can yield the required blocking in power devices when properly engineered. The use of an Au-free process improves compatibility and cost. However, achieving such blocking voltages required relatively large gate to drain spacing and careful device layout; also, on-resistance was higher compared to lower-voltage, lower-Al AlGaN devices, and thermal robustness under EV-type load cycling was not extensively characterized.

The study in [165] demonstrated the potential of ultra-thin GaN channel structures for achieving exceptionally high BD voltages. For the thin channel device (8 nm GaN channel with an Al0.9Ga0.1N barrier), a lateral BD voltage exceeding 10 kV was achieved with a large contact spacing of 96 µm. Importantly, even at very short spacing (2 µm), the device maintained a BD voltage slightly above 1 kV, corresponding to a BD field of 5 MV/cm. These results highlight the benefit of using high-Al-content barriers to strengthen polarization fields and suppress leakage, while thin channels improve field distribution. Such characteristics are highly relevant for EV power electronics, where both compact layouts (short gate to drain distance (L_GD)) and high blocking voltages are critical. The paper [166] demonstrated the effectiveness of regrown ohmic contacts in enabling high-performance Al-rich AlGaN channel devices. Using a 50% Al content AlGaN channel and a gate drain spacing of 40 µm, the device achieved a BD voltage of 4300 V, while maintaining low leakage current. The regrown n⁺ GaN ohmic regions significantly reduced the otherwise high contact resistance associated with Al-rich channels, thereby improving current drive and lowering on-resistance. This result highlights how careful contact engineering can overcome material limitations of AlGaN channels, making them strong candidates for high-voltage applications. For EV power electronics, such devices combine high BD capability with reduced conduction losses, directly addressing the requirements of traction inverters and onboard converters. These results are tabulated in

Table 6. Reported studies on high-Al-content AlGaN barrier GaN HEMT.

Ref 1	Year	Barrier (Al%)	Key Results	Main Limitations	EV Relevance
[163]	2024	64%	BV > 3 kV (pre passivation), 2 kV (post passivation), dynamic RON increase <10%, strong 2DEG confinement	Very high Al → large lattice mismatch, mobility penalty and dislocation risk, requires field-plate and passivation to manage peak E field.	Demonstrates path to kV class GaN for traction/medium voltage power electronics
[164]	2021	40%	2.0 kV reverse blocking reported (device/variant dependent).	Large LGD/field-plate needed for multi kV, trade-offs in area and parasitics for power modules.	Directly relevant—shows 2 kV class blocking on Si substrate (OBC/some inverter roles).
[165]	2019	90%	>1000 V at 2 µm spacing	Mobility penalty (µ =340 cm2/V·s) due to high Al% and thin channel, reduced drive current compared to conventional GaN	Demonstrates feasibility of using high Al barrier thin channel structures for >1 kV operation, relevant for high-voltage EV power conversion
[166]	2021	50%	Demonstrated record high off-state BV (>4 kV) with leakage < 1 µA/mm, high BD field = 5.5 MV/cm, regrown ohmic contacts improved current injection	Relatively low drain current density (=0.1 A/mm); fabrication complexity due to regrown ohmics, scalability to large wafers not yet proven	Promising for high-voltage EV power converters (OBCs, inverters) where >1200 V class is needed, high Al content offers thermal stability at elevated junction temperatures

¹ Studies within the same technology report comparable trends; representative works are listed individually for clarity.

, and the plot comparing the Al % in the barrier vs. BD voltage is given in Figure 10.

4.3.2. Superlattice Buffer

Superlattice (SL) buffers, typically alternating thin AlN and GaN layers, have emerged as an effective strategy to address the limitations of conventional GaN buffer layers in high-voltage HEMTs. By dividing the total buffer thickness into multiple thin periodic layers, as illustrated in Figure 11, the strain is more evenly distributed, reducing dislocation propagation, wafer bowing, and crack formation. This structural engineering not only improves crystal quality but also lowers buffer leakage, both critical for high-voltage, low-loss power switching. Recent work demonstrating the effectiveness of this approach is listed in

Table 7. Reported studies on superlattice buffers for GaN HEMT.

Ref 1	Year	SL/Buffer Configuration	2DEG Density	Mobility	Outcomes
[167]	2023	AlN/GaN SL buffer, 2.2 µm thick	1.04 × 1013 cm−2	1760 cm2/V·s	Improved crystal quality and reduced buffer leakage compared to non-SL buffer, better surface roughness, and BD performance improved.
[168]	2023	The 1.84 µm thick SL buffer structure features 80 periods of AlN/GaN (2/21 nm)	8.2 × 1012 cm−2	1770 cm2/V·s	BD/leakage and dynamic performance (e.g., trapping during off-state stress) improved, SL buffer thickness/period ratio shown to critically affect leakage and field distribution beneath the buffer and barrier layers.
[169]	2020	SL-based buffer with 3.8 µm AlN/GaN SL (140 periods)	1.30 × 1013 cm−2	1600 cm2/V·s	Lower trapping, improved temperature behavior and BD voltage, leakage/trapping metrics significantly improved for SL buffer designs.
[170]	2024	SL-based buffer with 1.15 µm AlN/GaN SL (37 periods)	1.02 × 1013 cm−2	1700 cm2/V·s	BD voltage improved relative to non-SL buffer control, leakage currents lower, contact resistance improved, SL + back barrier combination helps electric field spread and isolation.

¹ Studies within the same technology report comparable trends; representative works are listed individually for clarity.

. For example, an AlN/GaN SL buffer of 2.2 µm grown underneath an AlGaN/GaN HEMT on Si yielded a 2DEG concentration of 1.04 × 10¹³ cm⁻², mobility 1760 cm²/V·s, and low on-resistance while suppressing buffer leakage and enhancing overall device robustness [167].

Similarly, thin SL interlayers (SL-ILs) inserted between the substrate and GaN buffer have been shown to mitigate strain accumulation, suppress cracks, and improve surface morphology. Devices with SL-ILs still maintained strong 2DEG properties (1.2 × 10¹³ cm⁻², 1500 cm²/V·s mobility) even with thinner overall buffer thicknesses, which is highly attractive for wafer cost reduction and manufacturability [168]. Beyond improving electrical isolation, SL buffers enhance reliability by redistributing vertical electric fields more uniformly under off-state bias. This effect reduces peak electric fields at localized defects and lowers vertical leakage current, translating to higher BD voltages and better high-temperature reverse bias stability. Optimization of SL period thickness and total stack thickness is crucial, too few periods offer limited strain relief, while excessively thick SL stacks may increase thermal resistance or complicate growth. Overall, superlattice buffer engineering represents one of the most effective and mature techniques for improving the structural quality, leakage suppression, and BD strength of GaN HEMTs grown on large-area substrates such as Si, while maintaining favorable 2DEG properties for power switching. These designs offer useful trade-offs for high-voltage GaN HEMTs, especially when combined with field plates and buffer/back barrier engineering.

4.3.3. Polarization-Engineered Back Barrier

Polarization-engineered back barriers (such as AlN or AlGaN back barrier layers beneath the GaN channel) have become an effective method to raise BD voltage, reduce leakage, and improve channel confinement in GaN HEMTs. Figure 12a illustrates the cross section of an AlGaN/GaN HEMT incorporating a polarization-engineered back barrier. The conduction band profiles with and without the back barrier are illustrated in Figure 12b, demonstrating that the back barrier introduces a potential barrier that reduces vertical carrier leakage and improves breakdown performance. By creating a conduction band offset under the channel and pushing the peak electric field away from weak buffer regions, back barriers help suppress punch-through and buffer leakage under high drain biases. For example, a hybrid AlGaN back barrier HEMT (HBB-HEMT) with two distinct Al compositions (Al0.25Ga0.75 N and Al0.1Ga0.9N) showed a simulated BD voltage of 1640 V, more than double that of the conventional HEMT, while maintaining low on-resistance [171].

A recent experimental study reported a breakthrough in back barrier engineering by introducing iron (Fe) dopants into the buffer together with a polarization-engineered AlGaN back barrier, achieving a measured BD voltage of roughly 1.7 kV for lateral devices. The Fe dopants act as deep acceptors in the buffer, compensating residual donors and strongly suppressing buffer leakage paths, while the AlGaN back barrier creates a conduction band offset that spatially separates the 2DEG from the lossy buffer. Together, these effects reduce vertical punch-through and relocate peak fields away from defect-rich regions, enabling substantially higher off-state blocking without excessively increasing gate-to-drain spacing. This Fe-doped back barrier strategy is highly promising for traction inverter and onboard charger applications because it raises BV without the large area penalty of extreme L_GD scaling, but integration challenges like buffer contamination control, thermal budget, and process repeatability must be addressed before volume deployment [172]. The work [173] provides an in-depth analysis of how a thin AlGaN back barrier can significantly influence electric field distribution and device reliability. By inserting the AlGaN back barrier beneath the AlN buffer on SiC, the authors achieved a lateral BD voltage of approximately 1230 V at a gate drain spacing of 10 µm, while still maintaining high-frequency operation suitable for mm-wave applications.

The thin back barrier effectively redistributes the vertical electric field, suppressing buffer leakage and shifting peak field intensity away from critical buffer regions. This design insight highlights that even a modest back barrier can substantially improve BV without excessive scaling of device dimensions. Although primarily targeted at mm-wave devices, the findings are highly relevant for EV power electronics, where scaling such designs with longer gate drain distances and field plating could extend the BD voltage well beyond the 1–3 kV range required for inverter and converter applications. These examples suggest back barrier engineering is one of the most promising strategies to achieve EV-level BV (≥1–2 kV) while preserving conduction performance and thermal reliability. Some of the latest reports and studies on the polarization-engineered back barrier HEMT are listed in

Table 8. Reported studies of polarization-engineered back barrier GaN HEMT.

Ref 1	Year	Structure	LGD (µm)	BD (V)	Key results	Main limitations	EV Relevance
[171]	2024	Design Optimization of HBB-HEMT with Neural Networks	6	1640	Excellent BV vs. Ron trade-off in simulation, field modulation and interface position well explored.	Requires precise epitaxy, simulated, not yet reported experimentally.	Strong candidate for EV switching and traction inverter design, suggests path to >1.6 kV with manageable Ron.
[172]	2024	Fe-doped back barrier AlGaN/GaN HEMT	15	1700	Achieved 1700 V BV with effective suppression of buffer leakage and improved field distribution. Fe doping enhanced charge compensation and improved thermal reliability.	Doping process complexity, higher interface states may affect mobility if not optimized.	Directly relevant to EV power converters where BV > 1.2 kV is needed, Fe-doping gives robust trade-off between BV and reliability.
[173]	2023	AlN/GaN-on-SiC with thin AlGaN back barrier	10	1230	Thin AlGaN back barrier redistributes vertical electric field, reduces leakage, shifts peak field away from buffer, enabling >1 kV BV while retaining mm-wave frequency capability.	BV limited by short LGD, study optimized mainly for mm-wave performance, not EV-scale high-voltage operation.	Demonstrates back barrier engineering potential. With larger LGD + field plates, similar approaches could scale BV into the 1–3 kV EV range.

¹ Studies within the same technology report comparable trends; representative works are listed individually for clarity.

.

4.4. Substrate Engineered GaN HEMT

4.4.1. GaN-on-Si

GaN HEMTs on Si substrates remain highly attractive for EV power electronics due to their scalability, low cost, and compatibility with large wafer processing, despite intrinsic challenges in thermal conductivity and buffer reliability [174,175]. In [174], the device uses a p-GaN cap to achieve normally off behavior (Vth = +1.4 V), together with a buffer composed of a 6 µm AlN/GaN superlattice with carbon doping (5 × 10¹⁸ cm⁻³), grown on a 6-inch Si substrate. Vertical BD voltage (VGS = 0 V) reaches 1.45 kV, corresponding to an average vertical field >2.4 MV/cm, while maintaining low leakage up to 1.2 kV and very low buffer trapping (assessed by substrate ramp measurements) even at sweep voltages up to 1.4 kV. Though the on-state current density is modest (150 mA/mm) and RON relatively high (32 mΩ cm²), these devices still mark an important benchmark: they show that GaN-on-Si with superlattice buffers can simultaneously deliver >1.2 kV BV, normally off operation, and low trap-induced dynamic degradation. This makes them strong candidates for EV applications such as OBCs, DC-DC converters, or inverter pre-stages, particularly where cost and wafer scalability are essential.

4.4.2. GaN-on-SiC

GaN-on-SiC delivers the clearest short-term path to high-power, high-reliability GaN for EV traction because SiC substrates combine good lattice/thermal match with excellent thermal conductivity and low defectivity [173,176]. Devices on SiC show superior thermal stability, higher continuous power capability, and generally higher experimentally demonstrated BD voltages for a given lateral geometry compared with GaN-on-Si. For high-voltage/thermal stress applications (traction inverters and heavy-duty converters), GaN-on-SiC permits more aggressive L_GD scaling and higher current density while keeping junction temperatures manageable, a critical advantage in dense EV inverter modules. The downside is substrate cost: SiC wafers remain more expensive and smaller in diameter than Si, which raises per-die cost and constrains economies of scale, although this is improving with growing SiC capacity. The work [173] demonstrated how careful back barrier engineering on SiC substrates can significantly enhance BD performance while maintaining RF potential. By inserting a thin AlGaN back barrier beneath the AlN/GaN heterostructure, the device achieved a lateral BD voltage of 1230 V at a gate to drain spacing of 10 µm, corresponding to a BD field exceeding 1.2 MV/cm. The thin back barrier redistributed the electric field away from the channel buffer interface, effectively suppressing leakage pathways and improving device robustness. Although originally motivated by millimeter-wave applications, the demonstrated >1 kV BD voltage on a SiC platform directly underscores the relevance of this approach for EV power electronics, where both high-voltage operation and thermal reliability are critical.

4.4.3. GaN-on-GaN

GaN-on-GaN HEMTs, in which the active device layers are grown homoepitaxially on native GaN substrates, are widely regarded as a promising pathway toward achieving superior material quality due to the elimination of lattice mismatch and a significant reduction in threading dislocation density compared to heteroepitaxial GaN on foreign substrates [177,178]. These advantages translate into improved breakdown voltage, higher current capability, and enhanced thermal stability, making GaN-on-GaN devices attractive for high-performance power and RF applications in advanced EV systems. However, despite these intrinsic benefits, device performance can still be strongly influenced by interface and buffer-related phenomena. The work [177] investigates GaN-on-GaN HEMTs and reveals that a parasitic conductive interface between the GaN substrate and active layers severely degrades both DC and RF performance. This layer increases leakage and dynamic R_on, while reducing gain and power-added efficiency (dropping from 50% to 15%). The study highlights that even in homo epitaxial GaN structures, interface engineering is critical to fully exploit GaN-on-GaN’s potential for high-efficiency power and RF applications such as EV systems.

4.4.4. GaN-on-QST

GaN-on-QST (Qromis Substrate Technology) represents a promising intermediate pathway between GaN-on-Si and GaN-on-SiC for high-voltage EV applications. QST is an engineered substrate designed to closely match the lattice and thermal expansion coefficients of GaN, thereby reducing wafer bowing, cracking, and dislocation density during high-temperature epitaxy [179,180]. This improved structural integrity translates into higher device yield, improved thermal dissipation, and scalable BD voltage (approaching and even exceeding the 1.2–1.5 kV class, which makes GaN-on-QST devices attractive for applications like traction inverters that have traditionally been dominated by SiC. Unlike costly SiC, QST enables large-diameter wafers (200–300 mm), fully compatible with standard CMOS fabs, thereby lowering processing costs and aligning GaN with high-volume manufacturing roadmaps. Demonstrations of >1200 V and even 1500 V blocking capability in GaN-on-QST devices highlight its potential to extend GaN into high-voltage EV domains [179]. However, the ecosystem around QST is still maturing epi recipes, foundry flows, and long-term reliability data (including thermal cycling under AEC automotive standards) are under active development. Nonetheless, industry reports already place GaN-on-QST on the EV and industrial power electronics roadmap as a pragmatic, lower-cost alternative to SiC with significant potential for future adoption.

4.4.5. GaN-on-Diamond

GaN-on-diamond aims at the ultimate thermal solution: diamond’s extraordinary thermal conductivity (orders of magnitude above Si/SiC) can dramatically reduce self-heating and enable much higher power density per die [181,182]. In ref. [183], a simulation study on h-BN (Hexagonal Boron Nitride) passivation combined with a lift off transfer of GaN HEMT layers onto a diamond substrate demonstrates a practical route to dramatically reduce self- heating in power devices. By introducing a two part thermal management strategy, a thin h-BN passivation layer that improves thermal coupling at the GaN surface and reduces surface related scattering, and a lift off transfer that places the active AlGaN/GaN stack onto a high thermal conductivity diamond heat spreader, the authors show in electrothermal TCAD that peak channel temperatures and thermal boundary resistance can be substantially lowered compared with conventional GaN-on-Si or GaN-on-SiC layouts. The simulations further indicate improved current-carrying capability and reduced temperature induced mobility degradation under high-power-density operation, implying longer lifetime and higher continuous power capability for inverter and onboard charger transistors. Although the results are simulation-based and therefore sensitive to assumed TBC and material defect models, the work highlights a promising materials process pathway, h-BN passivation plus diamond integration for overcoming thermal limits in GaN power HEMTs targeted at EV applications.

Recent reviews and experiments demonstrate two main integration routes, direct growth and wafer bonding, and show significant reductions in hotspot temperature and improved thermal boundary conductance when diamond is integrated carefully. This thermal advantage could enable GaN power stages with much higher continuous power or allow aggressive L_GD/RON trade-offs while maintaining junction temperature limits required in EV traction inverters. The remaining technical hurdles are large-area, low-TBR (thermal boundary resistance) integration, the cost of high-quality diamond substrates or synthetic diamond layers, and process maturity. These are active research and patenting areas, but not yet mainstream for high-volume EV devices. In short, GaN-on-diamond is extremely promising for future ultra-high-power GaN modules, but commercialization for EVs will depend on solving TBR and cost challenges.

Table 9. Reported studies of GaN HEMT on different substrates.

Substrate	Ref	Year	BD (kV)	Thermal Conductivity (W/m·K)	Dynamic RON	Substrate Cost/Scalability	Industry Status	EV Relevance (OBC/Traction Inverter/DC-DC)
Si	[174]	2022	>1.2	150	Low buffer trapping → stable RON under high VDS	Low-cost, large wafer (200 mm) → scalable	Pre-commercial/Pilot lines	Suitable for OBCs and DC/DC converters in EVs due to 1.2 kV capability
	[175]	2025	-
SiC	[173]	2023	1.5–2.0	400	Back barrier design reduces leakage, improves VBR stability	More expensive, wafer size limited (≤150 mm)	Mature R&D, some commercial	Relevant for traction inverters and high-power OBCs, where high VBR and thermal stability are required
	[176]	2021	1.2
Diamond	[177]	2024	>1.5	1800– 2000	Reduced self-heating → lower RON degradation under stress	Very high cost, scalability limited	Early-stage R&D	Long-term traction inverter candidate due to extreme thermal management, but not yet manufacturable at scale
	[178]	2025	-
QST	[179]	2024	1.5	500	Stable dynamic RON due to low stress/warpage	Moderate cost, scalable to 200 mm	Emerging/Pilot Production	Promising for 650–1200 V EV applications (OBC, DC/DC, traction)
	[180]	2022	1.2
GaN	[181]	2025	150	130	Increased effective dynamic Ron	High Cost	Emerging/Pilot Production	OBC/DC-DC (near-term research use)
	[182]	2025	755

lists the latest reported work of GaN HEMT on different substrates discussed above.

In summary, the wide spectrum of GaN HEMT structures, from mode of operation variants to advanced epitaxial and polarization-engineered designs, demonstrates the continuous effort to optimize reliability, switching performance, and voltage capability for demanding power applications. Given the diversity of GaN HEMT structures and material engineering approaches,

Table 10. Comparison of GaN HEMT architectures for power electronics applications.

Architecture	Key Structural Feature	Main Advantages	Key Limitations	EV Power Electronics Relevance
Depletion-Mode GaN HEMT	Standard Heterostructure	High mobility simple structure	Safety concerns, complex gate drives	Limited (research, cascode use)
p-GaN Gate GaN HEMT	p-GaN cap under gate	Enhancement mode	Gate reliability, Threshold instability	OBC, DC to DC converters
Gate Recess GaN HEMT	Etched AlGaN under gate	Low gate leakage, Fast switching	Process control sensitivity	Medium-voltage EV sub system
Cascode GaN HEMT	Depletion-mode GaN HEMT + Si MOSFET	Easy drive compatibility	Added parasitics, lower speed	Early EV adoption
High Al AlGaN Barrier	Increased Al mole fraction	Higher 2DEG density	Increased strain, Reliability issues	High-voltage operation
Superlattice Buffer	Multi-layer strain Management	Reduced leakage, better breakdown	Growth complexity	High-voltage EV inverters
Polarization Back Barrier	Engineered Polarization Layer	Reduced current collapse	Added epitaxial complexity	High-reliability EV system
GaN-on-Si	Si Substrate	Low cost, large wafers	Thermal and breakdown limits	Cost-sensitive EV electronics
GaN-on-SiC	SiC substrate	Excellent thermal performance	High cost	Traction Inverters
GaN-on-Diamond	Diamond Heat spreader	Ultra-high thermal conductivity	Immature very costly	Future high-power-density EVs
GaN-on-QST	Engineered composite substrate	Reduced stress improved yield	Limited maturity	Emerging EV platform
GaN-on-GaN	Native GaN substrate	Lowest defect density	Extremely expensive	Research, premium EV technology

presents a consolidated comparison of normally on and normally off devices, advanced barrier and buffer designs, and substrate-engineered GaN HEMTs, highlighting their respective trade-offs for power electronics applications. Each structural innovation addresses specific limitations in conventional GaN devices and contributes to improving overall efficiency and robustness. These advancements collectively establish a solid foundation for the next generation of high-performance power switches. Building on this understanding, the following section explores the state-of-the-art GaN discrete transistors that incorporate these structural advancements to deliver high performance in next-generation EV power electronics.

Future progress in GaN HEMT structures for power electronics is expected to center on structural co-optimization of the barrier, channel, buffer, and field management layers to simultaneously achieve high breakdown voltage, low dynamic on-resistance, and robust normally off operation. Continued refinement of polarization engineering, ultra-thin barrier designs, and multi field plate architectures will be critical for suppressing electric-field crowding and mitigating trapping effects under high-voltage switching conditions. In parallel, advances in buffer design, such as graded, compensated, and carbon-engineered buffers, are anticipated to play a decisive role in improving leakage control and long-term reliability. As power applications move toward higher voltages and power densities, scalable and manufacturable GaN HEMT structures that balance performance, reliability, and process complexity will remain a key research focus, reinforcing the importance of structure-driven innovation in next-generation power devices

5. State-of-the-Art GaN Discrete Devices and Automotive Qualification

5.1. Commercial and Emerging GaN HEMTs for EV Power Electronics

As GaN HEMT structures continue to advance at the material and device levels, these innovations are increasingly reflected in commercially available power transistors designed for electric vehicle applications. The industry has rapidly matured, with several manufacturers now offering high-performance discrete GaN devices optimized for efficiency, switching speed, and thermal reliability. To understand the current technological landscape and benchmark practical device capabilities, it is essential to review the latest discrete GaN HEMTs developed specifically for high-efficiency EV power electronics.

Table 11. State-of-the-art GaN HEMT discrete transistor for high-efficiency EV power electronics.

Vendor	VDS (V)	IDS (A)	RDS (ON) mΩ	Power Dissipation (W)
TP65H015G5WS (Renesas/Transphorm Gen-V)	650	93	15–18	266
GS66516T (GaN Systems)	650	60	25	450
GS66508T (GaN Systems)	650	30	50	250
TP65H035G4WS (Renesas/Transphorm Gen-IV)	650	46	35	119
TP65H050G4WS (Transphorm Gen-IV)	650	30	50	119
IGLT65R035D2 (Infineon CoolGaN G5)	650	47	35	154
IGLD65R110D2 (Infineon CoolGaN G5)	650	14	110	51
CG65050TAD/CG65050DAD (CloudSemi)	650	40	39	236

summarizes a selection of the latest high-performance GaN discrete power transistors available from leading industry manufacturers. These 650 V devices developed by Transphorm (Renesas), GaN Systems, and Infineon demonstrate strong potential for next-generation EVs. With continuous drain currents exceeding 90 A and low on-resistance values in the 15–35 mΩ range, they offer excellent power density and switching efficiency suitable for 400 V and emerging 800 V EV architectures. Their compact, thermally enhanced packages and superior switching characteristics make them well suited for high-frequency, high-efficiency power conversion systems such as onboard chargers (OBCs), DC-DC converters, and traction inverters.

5.2. Standardization and Qualification Frameworks for Automotive GaN HEMTs

While Table 11 compares the electrical performance of state-of-the-art commercial GaN HEMTs,

Table 12. Reliability, qualification status, and automotive readiness of commercial GaN HEMTs based on publicly available manufacturer datasheets, reliability reports, and qualification standards.

Ref	Vendor/ Platform	Device Family	Qualification Status	Max TJ (°C)	Reliability Information	Automotive Adoption Status
[183]	Infineon	CoolGaN™ G5	JEDEC qualified; AEC-Q101 targeted	175	HTOL, HTRB, power cycling reported	Automotive programs ongoing
[184]	Transphorm	Gen-IV/Gen-V	JEDEC qualified; automotive-grade variants available	175	Long-term reliability and field data reported	Used in automotive OBCs
[185]	GaN Systems	GS-650 V series	JEDEC qualified; not AEC-Q101	150–175	Accelerated lifetime testing reported	Evaluation/pilot adoption

provides a complementary comparison focusing on reliability ratings, qualification status, and current automotive adoption, offering a clearer perspective on the industrial readiness of GaN devices for EV applications. The reliability and qualification of power semiconductor devices are commonly benchmarked using industry-standard stress test frameworks defined by JEDEC and the Automotive Electronics Council (AEC). JEDEC (Joint Electron Device Engineering Council) provides widely adopted qualification guidelines, such as JESD47, which specify stress-test-driven methodologies including high-temperature operating life (HTOL), temperature cycling, highly accelerated stress testing (HAST), and bias-temperature stress to assess intrinsic device reliability and failure mechanisms. These standards are broadly applied across commercial and industrial semiconductor technologies. In contrast, AEC-Q101 represents a more stringent qualification standard specifically developed for discrete semiconductor devices intended for automotive applications. AEC-Q101 imposes harsher operating conditions, extended stress durations, and tighter acceptance criteria to ensure long-term reliability under the severe thermal, electrical, and environmental stresses encountered in automotive systems. Consequently, while JEDEC qualification demonstrates baseline device robustness, compliance or targeting of AEC-Q101 is generally regarded as a key indicator of automotive readiness for power devices such as GaN HEMTs.

In summary, the latest generation of discrete GaN HEMTs demonstrates significant progress in performance, efficiency, and packaging maturity, positioning them as strong candidates for high-power EV applications. While these advancements highlight the considerable potential of GaN technology at the device level, they also underscore the need to address remaining challenges that impact long-term reliability and robustness. The following section, therefore, examines the key device-level limitations and reliability concerns that must be overcome for widespread adoption of GaN HEMTs in demanding automotive environments.

6. Reliability and Operational Challenges of GaN HEMTs in EV Applications

6.1. Device-Level Challenges and Reliability Issues

Despite their promising advantages, the widespread adoption of GaN HEMTs in EV systems is limited by several technological and reliability concerns. Understanding these challenges is essential for evaluating their readiness for large-scale deployment, particularly in Malaysia, where high humidity, heat, and cost-sensitive markets present additional barriers.

6.1.1. Current Collapse and Trapping Effects

One of the most critical reliability concerns in GaN HEMTs is current collapse, a transient degradation phenomenon primarily caused by electron trapping in surface states, buffer-related defects, or at the AlGaN/GaN heterointerface. During high-voltage or high-frequency switching, these traps capture carriers, leading to a temporary increase in on-resistance (RON) and a corresponding reduction in drain current under pulsed operation, as illustrated in Figure 12 [179,186,187]. While the effect is partially recoverable once the traps are released, its recurrence under repetitive switching cycles severely impacts device consistency and stability. In the context of EV power electronics, where GaN devices are expected to operate under high-frequency (>100 kHz), high-voltage (>600 V), and thermally demanding environments, current collapse becomes particularly detrimental. The rise in RON not only reduces conversion efficiency but also causes excessive self-heating, which can accelerate device degradation mechanisms such as hot electron injection, threshold voltage shifts, and long-term trap generation. As a result, unresolved current collapse directly threatens the reliability, lifetime, and certification readiness of GaN HEMTs for automotive-grade applications. To address this issue, several mitigation strategies have been extensively studied. Surface passivation using SiN or AlN layers effectively reduces surface-state trapping by neutralizing dangling bonds and suppressing electric field crowding near the gate edge [188]. Advanced buffer engineering, such as carbon doping, Fe doping, or superlattice-based GaN/AlN stacks, has been shown to suppress buffer-induced trapping and improve vertical leakage control. Similarly, optimized field plate structures, including dual field plates and source-connected field plates, help redistribute the electric field, thereby lowering hot carrier injection into traps [170].

Among the reported approaches, advanced buffer engineering combined with optimized field-plate design currently offers the most robust pathway toward automotive-grade GaN HEMTs, as it addresses bulk trapping mechanisms that dominate under high-voltage, high-temperature, and long-term bias stress. Surface passivation is effective in reducing near-surface traps but is more sensitive to process variation and environmental stress, making it insufficient as a standalone solution for automotive qualification. These approaches have significantly improved dynamic RON stability in laboratory conditions. However, despite these advances, a universal solution that ensures robustness under automotive-specific stressors, including wide temperature cycling (−40 °C to 175 °C), high humidity, mechanical vibration, and long-term bias stress, remains elusive. This gap underscores the urgent need for standardized reliability testing, physics of failure models for trapping dynamics, and co-optimization of device design, passivation chemistry, and packaging technology to fully suppress current collapse in EV environments.

6.1.2. Gate Reliability and Gate Leakage

Threshold voltage instability in p-GaN gate HEMTs arises primarily from charge trapping at multiple locations, including the gate interface, AlGaN barrier, surface, and buffer, as shown in Figure 13. Under electrical and thermal stress, electrons or holes become trapped in these defect sites, reducing the 2DEG density and causing a positive shift in Vth. At the same time, high electric fields at the gate electrode can induce vertical gate-to-channel tunneling and trap-assisted tunneling (TAT) through defect states in the AlGaN barrier, resulting in increased gate leakage. Together, these mechanisms contribute significantly to GaN HEMT performance degradation and reliability concerns in high-voltage power applications. The geometry concentrates electric fields at the gate edge, enhancing Fowler–Nordheim tunneling and trap-assisted leakage through surface and interface states. Over time, such leakage pathways not only increase static gate current but also degrade dynamic switching behavior, limiting the device’s safe operating area in EV power converters. When subjected to sustained positive gate bias stress (as in repetitive switching of traction inverters and OBCs), hole injection into the p-GaN layer and the creation of defect states within the p-GaN or at the p-GaN/AlGaN interface can cause measurable threshold voltage shifts [189]. Such drifts reduce the predictability of gate control, leading to unstable drive conditions under automotive duty cycles. Additionally, the relatively high gate charge in p-GaN devices increases stress per switching cycle, making long-term reliability assurance even more complex.

To address these issues, extensive research in gate engineering is underway. Recessed gate structures with high-k dielectrics reduce peak electric field concentration and suppress tunneling leakage. Dielectric optimization, such as Al2O3, HfO2, or stacked oxides, can improve gate insulation and interface quality. Meanwhile, fluorine plasma treatments are being explored to modulate local charge distribution and stabilize threshold voltage over extended operation. Despite these advances, achieving a gate stack that simultaneously delivers low leakage, stable Vth, and robust endurance under the high switching frequencies and harsh thermal cycles of EV environments remains a central challenge for GaN HEMT technology.

6.1.3. Self-Heating and Thermal Management

Self-heating has emerged as one of the most critical reliability bottlenecks in high-power GaN HEMTs. While GaN offers outstanding electrical characteristics, high electron mobility, wide bandgap, and strong critical field strength, the intrinsic thermal conductivity of GaN (130–200 W/m·K) and AlGaN barrier layers (120 W/m·K) is modest when compared to alternatives such as SiC (370 W/m·K) or diamond (>2000 W/m·K). As a result, during high-voltage switching and large current densities typical of EV power electronics, significant localized self-heating occurs within the channel region. The most severe thermal stress is observed near the drain side gate edge, where electric field crowding and current crowding overlap. These hotspots accelerate several degradation pathways, including trap activation in surface states, defect generation in the buffer, and increased dynamic RON due to temperature-enhanced carrier trapping [190]. Over time, repeated thermal cycling in this region can induce crack propagation, dislocation climb, and electron migration, undermining both static performance and long-term device robustness. In the context of EV converters, inverters, and OBCs, the risk is magnified since these applications require continuous high-power operation under harsh thermal conditions, often with minimal cooling margins. The consequence is a higher probability of thermal runaway, where local heating increases leakage and trapping, which in turn generates further heating, a feedback loop that can lead to catastrophic failure. To address this, research and industry are pursuing several thermal management strategies. Substrate transfer techniques such as GaN-on-diamond or GaN on quasi substrate, which drastically enhance thermal spreading while maintaining lattice compatibility. Advanced heat spreaders, including embedded diamond films, graphene interlayers, and high-conductivity metal caps, which reduce peak junction temperatures. Optimized thermal vias and package-level solutions, such as copper pillars, microfluidic cooling, or double-sided cooling structures, which provide efficient heat extraction from both the top and bottom surfaces of the die.

In recent years, advanced packaging strategies have emerged as a highly effective and scalable solution to mitigate self-heating in GaN HEMTs for EV applications. Double-sided cooling architectures, enabled by flip-chip mounting, substrate thinning, or backside metallization, allow heat to be extracted simultaneously from both the top and bottom of the device, significantly reducing junction to ambient thermal resistance and peak channel temperature. Complementary approaches, such as embedded die packaging, where GaN devices are integrated directly into high thermal conductivity substrates or printed circuit boards, further enhance thermal spreading while minimizing parasitic inductance. These embedded and co-packaged solutions enable compact layouts, improved electrical performance, and more uniform temperature distribution, making them particularly attractive for high-power-density traction inverters and onboard chargers. When combined with optimized substrates and heat spreaders, advanced packaging and double-sided cooling represent a critical pathway toward achieving automotive-grade thermal reliability in next-generation GaN-based EV power converters. Despite these advances, integrating cost-effective and scalable thermal solutions into automotive-grade GaN devices remains a significant challenge. Ensuring low thermal resistance without sacrificing manufacturability, yield, or electrical performance will be a decisive factor in establishing GaN HEMTs as the dominant device technology for EV power electronics.

6.1.4. Hot Carrier Degradation

Hot carrier effects represent another major reliability concern in GaN HEMTs. When devices operate under large drain bias, carriers in the channel can gain substantial kinetic energy, becoming “hot electrons.” These energetic carriers may be injected into the gate dielectric, AlGaN barrier, or deep-level buffer traps, where they initiate defect generation and charge trapping. The consequences include permanent increases in RON, reduced electron mobility, threshold voltage instability, and, in extreme cases, catastrophic device breakdown [187,191]. In fast-switching EV inverters, which operate with high dv/dt and frequent voltage transients, these hot carrier processes are especially damaging because repetitive stress accelerates trap creation and structural degradation. This not only reduces efficiency but also shortens the overall device lifetime under automotive qualification standards. To better understand and quantify these degradation pathways, several characterization methods have been widely applied. Techniques such as deep-level transient spectroscopy (DLTS), low-frequency noise analysis, and time-resolved, or transient I-V measurements provide insight into the dynamics of hot carrier trapping and their correlation with performance drift. Collectively, these studies reinforce the view that hot carrier reliability is a fundamental barrier to long-term GaN deployment in EV power electronics, driving continued research into channel engineering, field plate optimization, and defect passivation strategies.

6.1.5. Cost, Substrate, and Scalability Trade-Offs

While GaN-on-Si technology benefits from low-cost, large-diameter wafers (200 mm and beyond), making it attractive for mass production, its high threading dislocation density and associated trapping effects limit device performance and long-term reliability compared to GaN-on-SiC platforms [190]. These crystal defects exacerbate current collapse, increase leakage, and reduce lifetime under the demanding stress conditions of EV power electronics. On the other hand, GaN-on-SiC substrates deliver superior thermal conductivity and a lower trap density, translating to higher efficiency and better robustness in high-power converters and traction inverters. However, the significantly higher wafer cost of SiC hinders large-scale adoption for cost-sensitive EV markets, especially in regions prioritizing affordability. To bridge this gap, engineered substrates such as QST (Qromis Substrate Technology) have emerged as a promising alternative. QST wafers mitigate wafer bowing, provide better thermal expansion matching, and enable higher BD voltages (>1200 V), all while supporting Si-compatible wafer diameters for scalability. This makes them attractive for EV applications that demand both performance and manufacturability. Nevertheless, the QST ecosystem remains in its early stages, with challenges in epitaxy optimization, foundry integration, and long-term AEC-Q automotive qualification [190]. Meanwhile, GaN-on-diamond represents the cutting edge of thermal management. Diamond’s ultra-high thermal conductivity (>2000 W/m·K) allows exceptional heat spreading from the GaN channel, drastically reducing hotspot formation and enabling higher current density operation without thermal runaway. For EV converters and inverters, this directly translates to improved power density and reliability under continuous stress. However, widespread adoption of GaN-on-diamond is currently constrained by wafer size limitations, complex and expensive transfer processes, and the need for reliable large-scale manufacturing routes. If these challenges are resolved, GaN-on-diamond could redefine the upper performance limits of GaN devices for high-power automotive applications. The reliability bottleneck and solutions are summarized in Figure 14. Beyond intrinsic device-level reliability mechanisms, GaN HEMTs deployed in EV power converters are subjected to complex and highly dynamic operating conditions that further influence degradation behavior and long-term robustness.

6.2. Impact of Realistic EV Operating Condition on GaN HEMT

While this review concentrates on device-level metrics such as breakdown voltage and RON, a full evaluation of GaN HEMTs for EV power electronics must also address reliability under realistic stress conditions, for instance, surge events, humidity, thermal cycling, and mechanical vibration. At the device level, this requires optimized epitaxy, passivation, and packaging, robust gate dielectrics and field plate or edge termination designs to tolerate surge and high field events, high conductivity substrates or heat spreader approaches (e.g., GaN-on-diamond, h BN passivation) to reduce self-heating and improve thermal management [177]. Humidity-resistant passivation layers and sealed or hermetic packaging to limit moisture ingress and packaging/attach schemes (e.g., sintered die attach, compliant interlayers, low-stress lead frames or lead frame-free packages) that minimize thermomechanical strain under thermal cycling and absorb mechanical stresses from vibration or shock. Future research should systematically pursue accelerated stress testing (e.g., high-temperature reverse bias (HTRB), thermal cycling, humidity plus bias, surge current or unclamped inductive switching (UIS), mechanical vibration/shock tests) on representative GaN HEMTs to quantify degradation mechanisms, lifetime limits, and operational margins in EV-relevant conditions [192,193].

Table 13. Recent quantitative device-level reliability results for GaN HEMTs.

Ref 1	Device	Stress\Conditions	Metrics Reported
[193]	TP65H035WS (Group D1) 2 650 V cascode GaN HEMT	H3TRB test (humidity + high-temp + high-voltage reverse bias) 85 °C, 85% RH (relative humidity), VDS = 520 V, Duration: 1000 h	Average leakage current during H3TRB: 10–20 µA
[194]	1200 V lateral p-GaN HEMTs on 9 μm GaN	HTRB (high-temperature reverse bias), 1200 V reverse-bias, high-temperature, 1000 h	Drain leakage: < 10 µA, Vth shift: negligible. RON: no measurable change. Breakdown voltage: remains 1.8 kV.
[195]	AlGaN/GaN HEMT with dual-layer surface structure	Pulsed test: VG = −6 V, VDS = 20 V (pulsed)	Reported negligible current collapse ≈ 3% under the stated pulsed conditions
[196]	p-GaN gate AlGaN/GaN on Si	Off-state drain stress	Vth drift up to 40% under off state drain bias

¹ Studies within the same technology report comparable trends; representative works are listed individually for clarity. ² Group D1 denotes the device classification used in [194] to identify a specific package and qualification test group.

summarizes representative quantitative device-level reliability results recently reported for GaN HEMTs. The data show a wide spread: some engineered 1200 V p-GaN lateral devices survive 1000 h HTRB (1200 V, 150 °C) with no measurable shift in Vth or dynamic RON (Imec), while other studies report non-trivial current collapse magnitudes (3–19% depending on passivation, doping, and pulse protocol) or degraded blocking in high humidity reverse-bias tests. Where studies report ‘no measurable change’, this is quoted with the test conditions and measurement resolution; conversely, reported % changes are for the specific pulsed or bias protocol used by each group. This heterogeneity underscores the need for harmonized, EV-relevant stress protocols (standardized pulse shapes, HTRB conditions, and vibration profiles) to enable direct engineering comparisons across device types.

Future research on the reliability of GaN HEMTs in EV applications is expected to increasingly focus on the interaction between intrinsic device degradation mechanisms and realistic automotive operating conditions. As EV powertrains adopt higher voltages, faster switching, and bidirectional power flow, understanding the coupled effects of high electric fields, repetitive hard switching, thermal cycling, and transient overstress on trapping phenomena, dynamic on-resistance, and threshold voltage stability will become critical. Reliability evaluation methodologies are likely to evolve beyond conventional steady state stress tests toward mission profile-based qualification that better reflects real EV drive cycles. In parallel, advances in device design, passivation, and buffer engineering, together with physics-based lifetime models, are anticipated to improve predictability and robustness under long-term operation. These developments will be essential to bridge the gap between laboratory-level reliability demonstrations and full automotive qualification of GaN HEMTs for next-generation EV power electronics.

7. Ultra-Wide-Bandgap Semiconductors: Opportunities Beyond GaN

Beyond GaN, several emerging ultra-wide-bandgap (UWBG) semiconductors, particularly β-Ga₂O₃ and single-crystal diamond, offer promising pathways for future high-voltage EV power electronics. β-Ga₂O₃ exhibits an exceptionally high critical electric field (8–8.5 MV/cm), enabling a theoretical specific on-resistance nearly an order of magnitude lower than GaN at comparable voltages [197]. However, its extremely low thermal conductivity (10–27 W/m·K) leads to severe self-heating, and the absence of p-type doping and reliable ohmic contact technologies limits practical device architectures [198]. Recent research efforts in β-Ga₂O₃ have increasingly focused on mitigating its severe self-heating limitations through advanced thermal management strategies, including heterogeneous integration on high-thermal-conductivity substrates such as SiC and diamond, substrate thinning, and novel heat-spreading architectures. While these approaches have demonstrated partial thermal performance improvements, interface thermal resistance and mechanical reliability remain critical challenges for high-power and high-duty-cycle EV applications. Diamond offers the highest known critical electric field (~10 MV/cm) and outstanding thermal conductivity (>2000 W/m·K) [199], enabling ultra-high-power operation. Yet, challenges including controlled doping, surface termination stability, high defect sensitivity, and limited wafer-scale availability restrict immediate adoption [200]. In addition to β-Ga₂O₃ and diamond, other ultra-wide-bandgap materials such as aluminum nitride (AlN) and boron nitride (BN) have attracted increasing research interest due to their exceptionally large bandgaps and critical electric fields [201]. AlN, with a bandgap of approximately 6.2 eV and a critical field exceeding 11 MV/cm, offers strong potential for ultra-high-voltage power devices; however, challenges related to doping efficiency, contact resistance, and large-area substrate availability currently limit practical device realization. Similarly, BN-based materials exhibit extremely wide bandgaps and excellent thermal stability, but their integration into power electronic devices remains at an early research stage due to difficulties in controlled crystal growth and device fabrication. Compared to these UWBG materials, GaN currently provides the most mature balance between performance, manufacturability, and reliability for near term EV applications. Nevertheless, advances in β-Ga₂O₃ epitaxy, thermal management, and diamond device engineering are expected to significantly influence the long-term roadmap of high-voltage power devices.

Although UWBG semiconductor materials such as β-Ga₂O₃, AlN, BN and diamond offer superior theoretical breakdown fields and the potential for low specific on-resistance, their integration with mature GaN HEMT technology faces significant limitations. These limitations include difficulties in achieving controllable and stable p-type and n-type doping, which restricts device architectures and performance, complex substrate and lattice mismatches that induce defects and strain, thermal management challenges stemming from low thermal conductivity (in the case of Ga₂O₃) and interface thermal resistance, and immature processing technologies with limited substrate availability and scalability. Material availability, production costs, and long-term reliability also remain barriers to industry adoption. These factors currently constrain the practical integration of GaN and emerging UWBG devices, suggesting that near term industrial trends will likely favor incremental improvement of GaN and SiC systems rather than wholesale hybridization with UWBG materials [201,202].

8. Open Challenges and Future Research Opportunities

Despite extensive GaN HEMT development for high-frequency, high-efficiency converters, reliability under dynamic EV conditions, such as trap formation, threshold voltage instability, and thermal stress effects, remains an open challenge [203,204]. Additionally, system-level co-optimization of GaN devices with gate drivers, packaging, and thermal management is limited in the current literature [205]. Emerging ultra-wide-bandgap materials, including β-Ga₂O₃ and diamond, present promising high-field and high-temperature characteristics, but face key obstacles such as doping difficulty, substrate compatibility, and processing immaturity that constrain practical integration with GaN platforms [201,202].

9. Conclusions

Next-generation wide-bandgap (WBG) device architectures are essential for advancing high-efficiency power electronics in electric vehicles, and GaN high-electron-mobility transistors (HEMTs) represent a mature and promising technology in this domain due to their superior switching performance, high breakdown voltage, and reduced conduction and switching losses. This review has shown that advances in GaN HEMT device architectures and discrete transistor technologies enable compact, high-frequency, and high-power-density EV converter designs. Nevertheless, reliable deployment requires addressing critical device-level phenomena such as current collapse, self-heating, and gate degradation, which are influenced by material quality, device geometry, and operational stress conditions. In this context, physics-based modeling and technology computer-aided design (TCAD) simulations play an increasingly important role in predicting reliability and guiding the design of GaN HEMTs for EV applications. Advanced TCAD frameworks enable coupled electrothermal and trap-assisted transport analysis, allowing the investigation of self-heating, electric field crowding, current collapse, and dynamic on-resistance degradation under realistic operating and stress conditions. By incorporating material parameters, interface trap distributions, buffer leakage paths, and packaging-related thermal boundary conditions, TCAD simulations provide valuable insight into failure precursors such as hotspot formation, gate degradation, and long-term parametric drift. When combined with experimental characterization, these simulation-driven approaches offer a powerful pathway for accelerating device optimization, reducing costly trial-and-error fabrication cycles, and improving confidence in automotive-grade reliability qualification of GaN-based power devices. Looking forward, the integration of GaN HEMTs with emerging ultra-wide-bandgap (UWBG) semiconductor devices offers significant potential to further enhance efficiency, robustness, and thermal performance, positioning WBG devices as enablers of next-generation, energy-efficient electric vehicle power electronic systems.