The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash. The relationship between the drain-to-body potential (Vdb) of G...
In this article, an experimental study on the gate-induced drain leakage (GIDL) current repairing worst hot carrier degradation (HCD) in Si p-FinFETs is investigated with the aid of an ultra-fast measurement (UFM) technique (~30 μs). It is found t...
In this study, we have analyzed the optimal bias condition of dummy WL for the sub-block gate induced drain leakage (GIDL) erase operation in 16-layer 3D NAND flash memory. Three-dimensional NAND flash memory performs an erase operation in units of p...
Polycrystalline silicon (poly-Si) thin film transistors (TFT) with a tri-gate fin-like structure and wide drain were designed and simulated to improve gate-induced drain leakage (GIDL), ON-state current, and breakdown voltage. The GIDL of fin-like TF...
To address the severe gate-induced drain leakage (GIDL) issue in fully depleted germanium-on-insulator (FD-GeOI) multi-subchannel tunneling field-effect transistors (MS TFETs), this paper proposes a stepped gate oxide (SGO) structure. In the off-stat...
The program disturbance characteristics of three-dimensional (3D) vertical NAND flash cell array architecture pose a critical reliability challenge due to the lower unselected word line (WL) pass bias (Vpass) window. In other words, the key contradic...
Three-dimensional NAND Flash has adopted the cell-over-peripheral (COP) structure to increase storage density. Unlike the conventional structure, the COP structure cannot directly increase the channel potential via substrate bias during the erase ope...
In this paper, a Silicon-Pillar (SP) structure, a new structure to improve the erase speed in the 3D NAND flash structure to which ferroelectric memory is applied, is proposed and verified. In the proposed structure, a hole is supplied to the channel...
In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of a dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in ter...
In this study, the operation method of the proposed ferroelectric memory structure as a method to overcome the limitations of the existing Charge Trap Flash (CTF) memory Vertical NAND (V-NAND) structure was presented and verified through device simul...
In this study, we developed a V-NAND with an improved IGZO-P type (IP) floating filler (FF) structure based on an IGZO channel verified in previous studies and demonstrated that it has a very fast erase speed through device simulation. The proposed F...
In this paper, we extensively analyzed the drain-induced barrier lowering (DIBL) and leakage current characteristics of the proposed partial isolation field-effect transistor (PiFET) structure. We then compared the PiFET with the conventional planar...
In this paper we present a systematic approach to sort out different types of random telegraph noises (RTN) in CMOS image sensors (CIS) by examining their dependencies on the transfer gate off-voltage, the reset gate off-voltage, the photodiode integ...
In this paper, we propose a new buried channel array transistor structure to solve the problem of current leakage occurring in the capacitors of dynamic random-access memory (DRAM) cells. This structure has a superior off current performance compared...
Through detailed experimental and modeling activities, this paper investigates the origin of the temperature dependence of the Erase operation in 3D nand flash arrays. First of all, experimental data collected down to the cryogenic regime on both cha...
This paper proposes an optimized program operation method for ferroelectric NAND (FE-NAND) flash memory utilizing the gate-induced drain leakage (GIDL) program and validated through simulations. The program operation was performed by setting the time...
This work presents an analysis about the influence of the gate and source/drain underlap length (LUL) on UTBB FDSOI (UltraThin-Body-and-Buried-oxide Fully-Depleted-Silicon-On-Insulator) devices operating in conventional (VB = 0 V), dynamic threshold...
Carbon nanotube field-effect transistors (CNTFETs) are becoming a strong competitor for the next generation of high-performance, energy-efficient integrated circuits due to their near-ballistic carrier transport characteristics and excellent suppress...
In this study on multi-nanosheet field-effect transistor (mNS-FET)—one of the gate-all-around FETs (GAAFET) in the 3 nm technology node dimension—3D TCAD (technology computer-aided design) was used to attain optimally reduced substrate le...