Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash

The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash. The relationship between the drain-to-body potential (Vdb) of GIDL transistors and the increasing number of layers was studied to explain the reason for the self-adaption of the GIDL erase. The dynamics controlled by the drain-to-body and drain-to-gate potential contribute to the self-adaption of the GIDL erase. Increasing the number of layers leads to a longer duration of the maximum value of Vdb (Vdb_max), combined with the increased drain-to-gate potential, which enhances the GIDL current and further boosts channel potential to reach the same value at different positions of the NAND string. We proposed a method based on the correlation between the duration of Vdb_max and the number of layers to obtain the limited layers of the GIDL erase. The limited layers allowed are more than four times the number of layers used in the current simulation. Combining the novel method of dividing the channel into multi-regions with the asynchronous GIDL erase method will be useful for further stacking more layers in 3D NAND Flash.


Introduction
With the continuous development of smartphones, 5G, artificial intelligence, and cloud computing, the demand for higher bit density in the market has grown rapidly. The bit density is generally increased by stacking more layers in 3D NAND Flash [1][2][3][4][5][6][7][8][9]. However, the connection scheme of using a body contact spacer (BCS) between channel polysilicon and the array common source line faces challenges during the process of removing the bottom of the gate stack, especially when stacking more than two stacks due to the overlap problem [10]. The novel connection scheme of the channel-hole sidewall ONO butting (CSOB) scheme was proposed to boost the storage density by using the sidewall connection scheme between channel polysilicon and the array common source line [10]. The erase method was changed from body erase in the BCS scheme to GIDL erase in the CSOB scheme. Therefore, holes needed to be generated by gate-induced drain leakage (GIDL) to increase the channel potential and achieve the erase operation. The first challenge for GIDL erase is the control of the doping profile in GIDL transistors, especially when it is first used in Bit Cost Scalable (BiCS). Since the manufacturing process of the bottom select gate is formed prior to the memory cell, the memory cell requires processes with a high thermal budget to achieve a large memory window and better performance. However, this leads to the problem of doping in the bottom select gate, as it can spread from the heavily doped source diffusion during the high thermal budget process [11]. To solve this problem, the manufacturing process of the bottom select gate was changed in Pipe-BiCS, placing it after the memory cell and adopting a shallower and steeper select gate channel doping profile with the low thermal budget [12]. Since then, the GIDL erase has faced challenges related to the variability and uniformity of the erase potential due to the indirect bias of GIDL erase caused by the potential drop for band-to-band tunneling. Caillat et al. proposed an optimization method for GIDL erase with dual-side (bottom select gate side and top select gate side) GIDL injection, which led to better erase effectiveness and more effective tail control of the erase threshold voltage distribution for variability improvement [13]. Malavena et al. studied the GIDL erase dynamics process in the vertical channel NAND Flash, focusing on the increase in channel potential, and proposed a compact model for the dynamic process of the GIDL erase to explore the directions for continuous optimization [14,15]. Nowadays, most of the advanced manufactured 3D NAND Flash structures in production use the GIDL erase method. The industry expects that the cost-effective manufacturing of 3D NAND Flash can achieve over 1000 stack layers via innovations in processes and novel materials [16]. Meanwhile, combining these innovative solutions with file-system and firmware-level optimizations can greatly improve memory performance and expand the application market of 3D NAND Flash memory [17]. GIDL erase is a critical enabler for the future development of 3D NAND Flash. However, the challenge of GIDL erase is the limitation layer, as more holes are required to boost the channel potential with stacking more layers. This has become a potential risk for the realization of thousands of layers in 3D NAND Flash.
In this work, we have investigated the correlation between GIDL erase and the number of layers (N Layers ) based on TCAD simulation. The relationship between the drain-to-body potential (V db ) and N Layers was studied. We found self-adaption of the GIDL current (I gidl ) with an increase in the N Layers . As the N Layers increased, the duration of the maximum value of V db (V db_max ) also increased, resulting in a longer duration of maximum GIDL current. The self-adaption of the GIDL erase is achieved through the dynamic control by the drain-to-body and drain-to-gate potential. At the end of the duration of V db_max , which leads to maximum I gidl , the same potential can be reached at different positions of the NAND string. The proposed method enables the determination of the limited number of layers for the GIDL erase based on the correlation between the duration of V db_max and the number of layers. Finally, we propose to divide the channel into multi-regions and implement an asynchronous GIDL erase method to overcome the limitation of GIDL erase and enable the stacking of more layers in 3D NAND Flash. Figure 1a shows the schematic of the 3D NAND Flash structure. The Synopsys Sentaurus Sdevice simulator (Synopsys, Mountain View, CA, USA) was used for the simulation. The simulation structure of this device is shown in Figure 1b, with one top select gate (TSG), one bottom select gate (BSG), and more than two dummy cells (DMY) between the select gate and memory cells, and the number of memory cells will be dynamically adjusted according to the N Layers . The TSG and BSG function as GIDL transistors. The parameters of the simulation structure are based on the current technology products. Furthermore, the drift-diffusion model, Coulomb scattering mobility model, thermionic emission, Shockley-Read-Hall recombination, and band-to-band-tunneling (BTBT) model were introduced in the polysilicon channel, which was well-calibrated based on our previous works [18] and GIDL current experiments. The inset shows the detailed structure of the GIDL transistors. The BTBT current occurs in the virtual PN junction around the GIDL transistors, and it follows the channel conduction direction through the BTBT path. Meanwhile, the electric field in the virtual PN junction is controlled by the drain-to-gate potential and the drain-to-body potential. GIDL transistors at the top and bottom of the strings can be applied as a negative bias to the gate relative to the drain. The erase voltage can be transferred to the channel via hole injection generated by the BTBT during the erase operation.   Figure 2 shows the GIDL current during the GIDL erase operation for various NLayers. 99 There is a significant dependence of the Igidl on the NLayers, which can be divided into four 100 regions. Region I is before Igidl reaches the maximum value. Region II is before the voltage 101 of GIDL transistors starts to increase (Trise), Region III is before the end time of the ramp-102 up of the drain voltage, and Region IV is the main erase region with constant erase volt-103 age. In Region I, the maximum Igidl value for larger NLayers occurs later than the maximum 104 value for small NLayers. As the NLayers increase, there is a time delay in the appearance of the 105 maximum value of the Igidl. Once the Igidl reaches the maximum value, it rapidly begins to 106 decrease. In Region II, the larger NLayers exhibit a steeper decrease in the Igidl from the max-107 imum value. In Region III, the Igidl remains relatively constant after the voltage of the GIDL 108 transistors starts to increase. The larger NLayers result in a higher Igidl. In Region IV, the Igidl 109 also decreases rapidly, which shows an obvious dependence on the NLayers. Finally, the 110 GIDL current tends to be the same value regardless of the NLayers in the main erase region. 111 The reason why the Igidl depends on the number of layers is that the capacitance of the 112 channel increases as more layers are stacked, requiring more holes to be injected to boost 113 the channel potential for GIDL erase. Then, we extracted the maximum value of the Igidl 114 for each of the NLayers. As shown in Figure 3, there is a clear correlation between the maxi-115 mum value of Igidl and the NLayers in a log scale. The Igidl generated by the BTBT has increas-116 ing self-adaption with an increase in the NLayers.   Figure 2 shows the GIDL current during the GIDL erase operation for various N Layers . There is a significant dependence of the I gidl on the N Layers , which can be divided into four regions. Region I is before I gidl reaches the maximum value. Region II is before the voltage of GIDL transistors starts to increase (T rise ), Region III is before the end time of the ramp-up of the drain voltage, and Region IV is the main erase region with constant erase voltage. In Region I, the maximum I gidl value for larger N Layers occurs later than the maximum value for small N Layers . As the N Layers increase, there is a time delay in the appearance of the maximum value of the I gidl . Once the I gidl reaches the maximum value, it rapidly begins to decrease. In Region II, the larger N Layers exhibit a steeper decrease in the I gidl from the maximum value. In Region III, the I gidl remains relatively constant after the voltage of the GIDL transistors starts to increase. The larger N Layers result in a higher I gidl . In Region IV, the I gidl also decreases rapidly, which shows an obvious dependence on the N Layers . Finally, the GIDL current tends to be the same value regardless of the N Layers in the main erase region. The reason why the I gidl depends on the number of layers is that the capacitance of the channel increases as more layers are stacked, requiring more holes to be injected to boost the channel potential for GIDL erase. Then, we extracted the maximum value of the I gidl for each of the N Layers . As shown in Figure 3, there is a clear correlation between the maximum value of I gidl and the N Layers in a log scale. The I gidl generated by the BTBT has increasing self-adaption with an increase in the N Layers .

Results and Discussion
98 Figure 2 shows the GIDL current during the GIDL erase operation for various NLayers. 99 There is a significant dependence of the Igidl on the NLayers, which can be divided into four 100 regions. Region I is before Igidl reaches the maximum value. Region II is before the voltage 101 of GIDL transistors starts to increase (Trise), Region III is before the end time of the ramp-102 up of the drain voltage, and Region IV is the main erase region with constant erase volt-103 age. In Region I, the maximum Igidl value for larger NLayers occurs later than the maximum 104 value for small NLayers. As the NLayers increase, there is a time delay in the appearance of the 105 maximum value of the Igidl. Once the Igidl reaches the maximum value, it rapidly begins to 106 decrease. In Region II, the larger NLayers exhibit a steeper decrease in the Igidl from the max-107 imum value. In Region III, the Igidl remains relatively constant after the voltage of the GIDL 108 transistors starts to increase. The larger NLayers result in a higher Igidl. In Region IV, the Igidl 109 also decreases rapidly, which shows an obvious dependence on the NLayers. Finally, the 110 GIDL current tends to be the same value regardless of the NLayers in the main erase region. 111 The reason why the Igidl depends on the number of layers is that the capacitance of the 112 channel increases as more layers are stacked, requiring more holes to be injected to boost 113 the channel potential for GIDL erase. Then, we extracted the maximum value of the Igidl 114 for each of the NLayers. As shown in Figure 3, there is a clear correlation between the maxi-115 mum value of Igidl and the NLayers in a log scale. The Igidl generated by the BTBT has increas-116 ing self-adaption with an increase in the NLayers.  The electric field that drives the BTBT in the junction is controlled both by the drain-124 to-gate potential (Vdg) and the drain-to-body potential (Vdb). In the experimental test, the 125 Vdg can be easily monitored. However, monitoring the changes in the drain-to-body po-126 tential is difficult. To investigate the reason for the self-adaption of Igidl with increasing 127 NLayers, we used Sentaurus TCAD simulation tools to study the relationship between Vdb 128 and the NLayers. Figure 4 shows the dependence of Vdb on the NLayers. Before Vdb reaches the 129 maximum value (Vdb_max), the trend of Vdb is independent of the NLayers. This is due to the 130 small Igidl, resulting in a slower rise in the channel potential in the body area after the hole 131 injection compared to the ramp speed of the drain voltage. However, once Vdb reaches 132 Vdb_max, the duration of Vdb_max exhibits a clear dependence on the NLayers. The increase in 133 the NLayers leads to a longer duration of Vdb_max. The appearance of Vdb_max is attributed to 134 the equal rise rate of the GIDL transistors' body potential and the external drain voltage 135 ramp speed (shown in Figure 5), which allows Vdb to remain in the Vdb_max state. This can 136 be explained by the fact that the capacitance of the channel increases with an increase in 137 the NLayers, which requires a larger Igidl to affect the far-end channel potential and needs 138 more time to meet the demand of Igidl. Therefore, keeping Vdb at Vdb_max between the drain-139 to-body and Vdg will create a further increase, promoting a significant increase in the GIDL 140 current to meet the demand for higher layers. 141 Figure 6 illustrates the band diagram at various times with the Vdb_max. With an in-142 crease in time, a larger Vdg reduces the BTBT distance, leading to a higher Igidl. At the final 143 time of Vdb_max, Igidl reaches its maximum value. After that, Vdb starts to decrease sharply 144 from the maximum value, and this region is closely related to the NLayers. The final Vdb 145 increases with the number of layers. At this time, the Vdg remains constant, and the junc-146 tion is affected by Vdb to dynamically generate Igidl to meet the demand for a higher number 147 of layers. The dynamics controlled by the drain-to-body and drain-to-gate potential con-148 tribute to the self-adaption of the GIDL erase, which enables one to stack more layers in 149 3D NAND Flash. The electric field that drives the BTBT in the junction is controlled both by the drain-togate potential (V dg ) and the drain-to-body potential (V db ). In the experimental test, the V dg can be easily monitored. However, monitoring the changes in the drain-to-body potential is difficult. To investigate the reason for the self-adaption of I gidl with increasing N Layers , we used Sentaurus TCAD simulation tools to study the relationship between V db and the N Layers . Figure 4 shows the dependence of V db on the N Layers . Before V db reaches the maximum value (V db_max ), the trend of V db is independent of the N Layers . This is due to the small I gidl , resulting in a slower rise in the channel potential in the body area after the hole injection compared to the ramp speed of the drain voltage. However, once V db reaches V db_max , the duration of V db_max exhibits a clear dependence on the N Layers . The increase in the N Layers leads to a longer duration of V db_max . The appearance of V db_max is attributed to the equal rise rate of the GIDL transistors' body potential and the external drain voltage ramp speed (shown in Figure 5), which allows V db to remain in the V db_max state. This can be explained by the fact that the capacitance of the channel increases with an increase in the N Layers , which requires a larger I gidl to affect the far-end channel potential and needs more time to meet the demand of I gidl . Therefore, keeping V db at V db_max between the drain-to-body and V dg will create a further increase, promoting a significant increase in the GIDL current to meet the demand for higher layers. 121 Figure 3. The correlation between the maximum value of the Igidl and the NLayers extracted using 122 Sentaurus TCAD. 123 The electric field that drives the BTBT in the junction is controlled both by the drain-124 to-gate potential (Vdg) and the drain-to-body potential (Vdb). In the experimental test, the 125 Vdg can be easily monitored. However, monitoring the changes in the drain-to-body po-126 tential is difficult. To investigate the reason for the self-adaption of Igidl with increasing 127 NLayers, we used Sentaurus TCAD simulation tools to study the relationship between Vdb 128 and the NLayers. Figure 4 shows the dependence of Vdb on the NLayers. Before Vdb reaches the 129 maximum value (Vdb_max), the trend of Vdb is independent of the NLayers. This is due to the 130 small Igidl, resulting in a slower rise in the channel potential in the body area after the hole 131 injection compared to the ramp speed of the drain voltage. However, once Vdb reaches 132 Vdb_max, the duration of Vdb_max exhibits a clear dependence on the NLayers. The increase in 133 the NLayers leads to a longer duration of Vdb_max. The appearance of Vdb_max is attributed to 134 the equal rise rate of the GIDL transistors' body potential and the external drain voltage 135 ramp speed (shown in Figure 5), which allows Vdb to remain in the Vdb_max state. This can 136 be explained by the fact that the capacitance of the channel increases with an increase in 137 the NLayers, which requires a larger Igidl to affect the far-end channel potential and needs 138 more time to meet the demand of Igidl. Therefore, keeping Vdb at Vdb_max between the drain-139 to-body and Vdg will create a further increase, promoting a significant increase in the GIDL 140 current to meet the demand for higher layers. 141 Figure 6 illustrates the band diagram at various times with the Vdb_max. With an in-142 crease in time, a larger Vdg reduces the BTBT distance, leading to a higher Igidl. At the final 143 time of Vdb_max, Igidl reaches its maximum value. After that, Vdb starts to decrease sharply 144 from the maximum value, and this region is closely related to the NLayers. The final Vdb 145 increases with the number of layers. At this time, the Vdg remains constant, and the junc-146 tion is affected by Vdb to dynamically generate Igidl to meet the demand for a higher number 147 of layers. The dynamics controlled by the drain-to-body and drain-to-gate potential con-148 tribute to the self-adaption of the GIDL erase, which enables one to stack more layers in 149 3D NAND Flash.   Figure 6. The band diagram of GIDL transistors at various times with the Vdb_max, Time2 > Time1. 157 Next, the channel potential at different positions of the string during the GIDL erase 158 operation was studied, as shown in Figure 7. Malavena et al. assumed that the channel 159 potential remains as a constant channel potential due to uniform hole accumulation [15]. 160 To investigate the channel potential position dependence of the GIDL erase, we used a 161 verified channel length longer than 5 um. However, our results show an interesting phe-162 nomenon. There is an apparent channel position dependence on the channel potential be-163 fore the GIDL current reaches its maximum value. When the GIDL current reaches the 164 maximum value, the channel potential starts to reach the same potential, and Igidl becomes 165 large enough to boost the total channel potential. Then, the channel potential and the po-166 sition potential of the GIDL transistors become the same. It is clear that the Igidl reaches the 167 maximum value during the GIDL erase process, and the same potential can be reached at 168 different positions along the NAND string.
169 Figure 5. The correlation between drain and body potential. Figure 6 illustrates the band diagram at various times with the V db_max . With an increase in time, a larger V dg reduces the BTBT distance, leading to a higher I gidl . At the final time of V db_max , I gidl reaches its maximum value. After that, V db starts to decrease sharply from the maximum value, and this region is closely related to the N Layers . The final V db increases with the number of layers. At this time, the V dg remains constant, and the junction is affected by V db to dynamically generate I gidl to meet the demand for a higher number of layers. The dynamics controlled by the drain-to-body and drain-to-gate potential contribute to the self-adaption of the GIDL erase, which enables one to stack more layers in 3D NAND Flash.  Figure 6. The band diagram of GIDL transistors at various times with the Vdb_max, Time2 > Time1. 157 Next, the channel potential at different positions of the string during the GIDL erase 158 operation was studied, as shown in Figure 7. Malavena et al. assumed that the channel 159 potential remains as a constant channel potential due to uniform hole accumulation [15]. 160 To investigate the channel potential position dependence of the GIDL erase, we used a 161 verified channel length longer than 5 um. However, our results show an interesting phe-162 nomenon. There is an apparent channel position dependence on the channel potential be-163 fore the GIDL current reaches its maximum value. When the GIDL current reaches the 164 maximum value, the channel potential starts to reach the same potential, and Igidl becomes 165 large enough to boost the total channel potential. Then, the channel potential and the po-166 sition potential of the GIDL transistors become the same. It is clear that the Igidl reaches the 167 maximum value during the GIDL erase process, and the same potential can be reached at 168 different positions along the NAND string. 169 Figure 6. The band diagram of GIDL transistors at various times with the V db_max , Time2 > Time1.
Next, the channel potential at different positions of the string during the GIDL erase operation was studied, as shown in Figure 7. Malavena et al. assumed that the channel potential remains as a constant channel potential due to uniform hole accumulation [15]. To investigate the channel potential position dependence of the GIDL erase, we used a verified channel length longer than 5 um. However, our results show an interesting phenomenon. There is an apparent channel position dependence on the channel potential before the GIDL current reaches its maximum value. When the GIDL current reaches the maximum value, the channel potential starts to reach the same potential, and I gidl becomes large enough to boost the total channel potential. Then, the channel potential and the position potential of the GIDL transistors become the same. It is clear that the I gidl reaches the maximum value during the GIDL erase process, and the same potential can be reached at different positions along the NAND string. To explore the limitation of the maximum stacking layers along the NAND string of 172 the GIDL erase operation, it is essential to determine the time when maximum Igidl occurs 173 to achieve a consistent channel potential at different positions. Based on the relationship 174 between Vdb and the NLayers, as the NLayers increase, the duration of Vdb_max also increases, 175 and the subsequent Igidl is determined by Vdg. The maximum Vdg value is determined by 176 the ramp of the GIDL transistor voltage, which affects the Vdg voltage jointly with the drain 177 or source of the GIDL transistors. Therefore, the time when the GIDL transistor voltage 178 increases determines the longest duration of Vdb_max during the GIDL erase operation. By 179 extracting the duration of Vdb_max for lower layers and the longest duration of Vdb_max, a 180 linear correlation between the duration of Vdb_max and the number of layers is obtained. In 181 order to verify the extensibility of the correlation, we simulated the GIDL erase by stack-182 ing more layers, and extracted the duration of Vdb_max, finding that it still follows this cor-183 relation (red square). Finally, the limited layers of the GIDL erase were obtained using the 184 proposed method, as shown in Figure 8. The limited layers allowed for more than four 185 times the number of layers used in the current simulation. To achieve stacking more layers 186 in 3D NAND Flash, the GIDL erase method needs further optimization. The current GIDL 187 erase method erases the entire channel simultaneously, that is, the synchronous GIDL 188 erase operation. Therefore, reducing the capacitance of each erase will effectively break 189 the limitation of the synchronous GIDL erase method. By dividing the channel into mul-190 tiple regions and applying the asynchronous GIDL erase method, the stacking of more 191 layers in 3D NAND Flash can be achieved. To explore the limitation of the maximum stacking layers along the NAND string of the GIDL erase operation, it is essential to determine the time when maximum I gidl occurs to achieve a consistent channel potential at different positions. Based on the relationship between V db and the N Layers , as the N Layers increase, the duration of V db_max also increases, and the subsequent I gidl is determined by V dg . The maximum V dg value is determined by the ramp of the GIDL transistor voltage, which affects the V dg voltage jointly with the drain or source of the GIDL transistors. Therefore, the time when the GIDL transistor voltage increases determines the longest duration of V db_max during the GIDL erase operation. By extracting the duration of V db_max for lower layers and the longest duration of V db_max , a linear correlation between the duration of V db_max and the number of layers is obtained. In order to verify the extensibility of the correlation, we simulated the GIDL erase by stacking more layers, and extracted the duration of V db_max , finding that it still follows this correlation (red square). Finally, the limited layers of the GIDL erase were obtained using the proposed method, as shown in Figure 8. The limited layers allowed for more than four times the number of layers used in the current simulation. To achieve stacking more layers in 3D NAND Flash, the GIDL erase method needs further optimization. The current GIDL erase method erases the entire channel simultaneously, that is, the synchronous GIDL erase operation. Therefore, reducing the capacitance of each erase will effectively break the limitation of the synchronous GIDL erase method. By dividing the channel into multiple regions and applying the asynchronous GIDL erase method, the stacking of more layers in 3D NAND Flash can be achieved. To explore the limitation of the maximum stacking layers along the NAND string of 172 the GIDL erase operation, it is essential to determine the time when maximum Igidl occurs 173 to achieve a consistent channel potential at different positions. Based on the relationship 174 between Vdb and the NLayers, as the NLayers increase, the duration of Vdb_max also increases, 175 and the subsequent Igidl is determined by Vdg. The maximum Vdg value is determined by 176 the ramp of the GIDL transistor voltage, which affects the Vdg voltage jointly with the drain 177 or source of the GIDL transistors. Therefore, the time when the GIDL transistor voltage 178 increases determines the longest duration of Vdb_max during the GIDL erase operation. By 179 extracting the duration of Vdb_max for lower layers and the longest duration of Vdb_max, a 180 linear correlation between the duration of Vdb_max and the number of layers is obtained. In 181 order to verify the extensibility of the correlation, we simulated the GIDL erase by stack-182 ing more layers, and extracted the duration of Vdb_max, finding that it still follows this cor-183 relation (red square). Finally, the limited layers of the GIDL erase were obtained using the 184 proposed method, as shown in Figure 8. The limited layers allowed for more than four 185 times the number of layers used in the current simulation. To achieve stacking more layers 186 in 3D NAND Flash, the GIDL erase method needs further optimization. The current GIDL 187 erase method erases the entire channel simultaneously, that is, the synchronous GIDL 188 erase operation. Therefore, reducing the capacitance of each erase will effectively break 189 the limitation of the synchronous GIDL erase method. By dividing the channel into mul-190 tiple regions and applying the asynchronous GIDL erase method, the stacking of more 191 layers in 3D NAND Flash can be achieved.

Conclusions
The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler for the future development of 3D NAND Flash. We have investigated the correlation between GIDL erase and the number of layers based on TCAD simulation. By studying the relationship between the drain-to-body potential of GIDL transistors and increasing the number of layers, we have explained the reason for the self-adaption of the GIDL erase. The self-adaption of the GIDL erase is achieved through the dynamic control via the drain-to-body and drain-togate potential. As the number of layers increases, the duration of V db_max also increases, which, in combination with increased drain-to-gate potential, enhances the GIDL current dynamically. This leads to the same potential being reached at different positions of the NAND string. Based on the correlation between the duration of V db_max and the number of layers, we obtained the limited layers of the GIDL erase using the proposed method. The limited layers allowed are more than four times the number of layers used in the current simulation. Furthermore, by combining the novel method of dividing the channel into multi-regions using the asynchronous GIDL erase method, 3D NAND Flash can stack more layers. We expect that the GIDL erase will contribute to the further development of 3D NAND Flash.