Insight into over Repair of Hot Carrier Degradation by GIDL Current in Si p-FinFETs Using Ultra-Fast Measurement Technique

In this article, an experimental study on the gate-induced drain leakage (GIDL) current repairing worst hot carrier degradation (HCD) in Si p-FinFETs is investigated with the aid of an ultra-fast measurement (UFM) technique (~30 μs). It is found that increasing GIDL bias from 3 V to 4 V achieves a 114.7% VT recovery ratio from HCD. This over-repair phenomenon of HCD by UFM GIDL is deeply discussed through oxide trap behaviors. When the applied gate-to-drain GIDL bias reaches 4 V, a significant electron trapping and interface trap generation of the fresh device with GIDL repair is observed, which greatly contributes to the approximate 114.7% over-repair VT ratio of the device under worst HCD stress (−2.0 V, 200 s). Based on the TCAD simulation results, the increase in the vertical electric field on the surface of the channel oxide layer is the direct cause of an extraordinary electron trapping effect accompanied by the over-repair phenomenon. Under a high positive electric field, a part of channel electrons is captured by oxide traps in the gate dielectric, leading to further VT recovery. Through the discharge-based multi-pulse (DMP) technique, the energy distribution of oxide traps after GIDL recovery is obtained. It is found that over-repair results in a 34% increment in oxide traps around the conduction energy band (Ec) of silicon, which corresponds to a higher stabilized VT shift under multi-cycle HCD-GIDL tests. The results provide a trap-based understanding of the transistor repairing technique, which could provide guidance for the reliable long-term operation of ICs.


Introduction
DRAM (dynamic random access memory) is one of the core components of electronic equipment, and it has become increasingly important in terms of the development of the information society [1]. For higher memory density, the downscaling of transistor size has become an inevitable trend. Fin Field-Effect Transistors (FinFETs) are recognized as one of the most promising structures for Future DRAM Peripheral Circuits and have been proposed for low-power and high-performance applications beyond 22-nm technology nodes [2,3].
With continuous channel length scaling, hot carrier degradation (HCD) has emerged as a major reliability issue in FinFETs [4]. From the trap-based research in HCD, both interface and oxide traps contribute to the overall degradation [5]. A modified compact model and trap spatial distribution investigations facilitate the accurate characterization

Device Fabrication
The replacement metal gate (RMG) Si bulk p-FinFETs are fabricated using a fully-gatelast process. The equivalent oxide thickness (EOT) is 0.92 nm. The major steps for gate stack formation are shown in Figure 1a

Electrical Measurements
Devices are stressed under the worst HCD condition (VG,STR = VD,STR) [6]; then, a GIDL voltage is applied to the stressed devices using a synchronized pulse of specified gate (VG,GIDL) and drain GIDL biases (VD,GIDL). In this article, the Keysight B1530 semiconductor analyzer is utilized to perform UFM of ID-VG characteristics using pulse-IV measurements with a duration of 30 μs [22]. Time evolutions of threshold voltage shift (ΔVT) are obtained in measure-stress-measure (MSM) mode [25]. VT is extracted through the constant current method with the target linear drain current (ID,LIN) of 100 nA × W/L [26]; here, W and L are the gate width and length, respectively.
The DMP experiments are performed to investigate the energy distribution of generated oxide traps during GIDL repair. Figure 2 shows the DMP test procedure used in this work. After 200 s HCD stress, 1 ks GIDL bias is applied to repair the aged device. Afterward, the repaired device is applied with the same HCD stress again; then, VG is sequentially decreased to multiple gate discharge voltage (VG,DIS) levels, while VD remains at the stress bias. Each discharge period lasts for only 1 s; then, a pulse-IV is performed to extract ΔVT. The overdrive voltage (VOV) is calculated by VOV = VG,DIS-VT; then, the ΔVT ~ VOV relationship is obtained to extract the energy distribution of oxide traps. All of the test results are averaged by a group of three devices at 125 °C.

Electrical Measurements
Devices are stressed under the worst HCD condition (V G,STR = V D,STR ) [6]; then, a GIDL voltage is applied to the stressed devices using a synchronized pulse of specified gate (V G,GIDL ) and drain GIDL biases (V D,GIDL ). In this article, the Keysight B1530 semiconductor analyzer is utilized to perform UFM of I D -V G characteristics using pulse-IV measurements with a duration of 30 µs [22]. Time evolutions of threshold voltage shift (∆V T ) are obtained in measure-stress-measure (MSM) mode [25]. V T is extracted through the constant current method with the target linear drain current (I D,LIN ) of 100 nA × W/L [26]; here, W and L are the gate width and length, respectively.
The DMP experiments are performed to investigate the energy distribution of generated oxide traps during GIDL repair. Figure 2 shows the DMP test procedure used in this work. After 200 s HCD stress, 1 ks GIDL bias is applied to repair the aged device. Afterward, the repaired device is applied with the same HCD stress again; then, V G is sequentially decreased to multiple gate discharge voltage (V G,DIS ) levels, while V D remains at the stress bias. Each discharge period lasts for only 1 s; then, a pulse-IV is performed to extract ∆V T . The overdrive voltage (V OV ) is calculated by V OV = V G,DIS -V T ; then, the ∆V T~VOV relationship is obtained to extract the energy distribution of oxide traps. All of the test results are averaged by a group of three devices at 125 • C. 4

TCAD Simulation Setup
To bring a further physical explanation, Sentaurus TCAD tools are employed to solve the electric field distribution of p-FinFETs under GIDL repair. The 3-D simulation structure of p-FinFETs with the same Fin shape in TEM is shown in Figure 3a. As shown in Figure 3b, the simulated ID-VG curve with GIDL is in good agreement with measured data within 1 m VT. The key simulation parameters, such as work function, stress, and the S/D distribution resistance, are concluded in Table 1. Here, the Nonlocal-Path model is used as a band-to-band physical model to accurately match GIDL characteristics in TCAD simulation [27].

TCAD Simulation Setup
To bring a further physical explanation, Sentaurus TCAD tools are employed to solve the electric field distribution of p-FinFETs under GIDL repair. The 3-D simulation structure of p-FinFETs with the same Fin shape in TEM is shown in Figure 3a. As shown in Figure 3b, the simulated I D -V G curve with GIDL is in good agreement with measured data within 1 m V T . The key simulation parameters, such as work function, stress, and the S/D distribution resistance, are concluded in Table 1. Here, the Nonlocal-Path model is used as a band-toband physical model to accurately match GIDL characteristics in TCAD simulation [27].   Figure 4 shows that p-FinFETs with 100 nm gate length are subjected to a −2 V HCD stress for 200 s, resulting in a VT degradation of approximately 170 mV and a shift of 8 mV/dec in subthreshold swing (SS). Subsequently, the UFM GIDL repairing process is   Figure 4 shows that p-FinFETs with 100 nm gate length are subjected to a −2 V HCD stress for 200 s, resulting in a V T degradation of approximately 170 mV and a shift of 8 mV/dec in subthreshold swing (SS). Subsequently, the UFM GIDL repairing process is implemented for 1 ks with different repairing biases. Under moderate GIDL bias of V GD = 3 V (V G,GIDL = 0.5 V, V D,GIDL = −2.5 V), the V T shift is reduced to 60 mV, and the SS shift is negligible, corresponding to a 62.7% recovery ratio, as shown in Figure 4a. In Figure 4b, under a high GIDL bias of V GD = 4 V (V G,GIDL = 1.5 V, V D,GIDL = −2.5 V), the V T recovery ratio is increased to 114.7%, which indicates that the degraded device is overrepaired by GIDL repair. However, this improvement comes at the cost of degradation in SS of 9 mV/dec. Considering that SS degradation reflects the generation rate of interface traps [28], excessive gate-to-drain electric field may result in extraordinary interface damage to the device [29].  Figure 4 shows that p-FinFETs with 100 nm gate length are subjected to a −2 V HCD stress for 200 s, resulting in a VT degradation of approximately 170 mV and a shift of 8 mV/dec in subthreshold swing (SS). Subsequently, the UFM GIDL repairing process is implemented for 1 ks with different repairing biases. Under moderate GIDL bias of VGD = 3 V (VG,GIDL = 0.5 V, VD,GIDL = −2.5 V), the VT shift is reduced to 60 mV, and the SS shift is negligible, corresponding to a 62.7% recovery ratio, as shown in Figure 4a. In Figure 4b, under a high GIDL bias of VGD = 4 V (VG,GIDL = 1.5 V, VD,GIDL = −2.5 V), the VT recovery ratio is increased to 114.7%, which indicates that the degraded device is over-repaired by GIDL repair. However, this improvement comes at the cost of degradation in SS of 9 mV/dec. Considering that SS degradation reflects the generation rate of interface traps [28], excessive gate-to-drain electric field may result in extraordinary interface damage to the device [29].

Physical Explainations of GIDL Repairing Mechanism
To explain the over-repair phenomenon that occurs at high GIDL biases, a group of fresh devices is subjected to 1 ks GIDL biases, as shown in Figure 5. When a moderate GIDL bias (V G,GIDL = 0.5 V, V D,GIDL = −2.5 V) is applied, the recovery of V T is relatively low, measuring approximately 27 mV. However, under high GIDL biases (by either increasing V G,GIDL or V D,GIDL ), the recovery of V T exceeds 100 mV. It can be seen that at high gate-to-drain electric fields, a large number of electrons are injected into the gate oxide, which greatly contributes to V T recovery [30]. Moreover, after applying a high GIDL bias, a degradation of approximately 12 mV/dec in SS can be observed. However, no SS degradation is observed at a moderate GIDL bias.
To explain the over-repair phenomenon that occurs at high GIDL biases, a group of fresh devices is subjected to 1 ks GIDL biases, as shown in Figure 5. When a moderate GIDL bias (VG,GIDL = 0.5 V, VD,GIDL = −2.5 V) is applied, the recovery of VT is relatively low, measuring approximately 27 mV. However, under high GIDL biases (by either increasing VG,GIDL or VD,GIDL), the recovery of VT exceeds 100 mV. It can be seen that at high gate-todrain electric fields, a large number of electrons are injected into the gate oxide, which greatly contributes to VT recovery [30]. Moreover, after applying a high GIDL bias, a degradation of approximately 12 mV/dec in SS can be observed. However, no SS degradation is observed at a moderate GIDL bias. Furthermore, a physical explanation is given with the aid of TCAD simulation. The electric field distributions of the device under different GIDL biases are simulated. Cutting vertically the center of gate along the channel direction, the 2-D view of the electric field distributions is shown in Figure 6. As VGD increases from 3 V to 4 V, the channel electric field changes significantly at two positions: one near the drain region, and the other along the channel surface. The 1-D electric field, cut along the surface of oxide layer in 2-D view in Figure 6, is shown in Figure 7a. It is shown that the electric field peaks near the drain region. Then, this peak electric field and the channel center electric field are extracted in Figure 7b and named as Ex = 50 and Ex = 0 according to their positional coordinates.
Pulse-IV curves of fresh p-FinFETs before and after 1 ks GIDL biases for (a) V GD = 3 V: Furthermore, a physical explanation is given with the aid of TCAD simulation. The electric field distributions of the device under different GIDL biases are simulated. Cutting vertically the center of gate along the channel direction, the 2-D view of the electric field distributions is shown in Figure 6. As V GD increases from 3 V to 4 V, the channel electric field changes significantly at two positions: one near the drain region, and the other along the channel surface. The 1-D electric field, cut along the surface of oxide layer in 2-D view in Figure 6, is shown in Figure 7a. It is shown that the electric field peaks near the drain region. Then, this peak electric field and the channel center electric field are extracted in Figure 7b and named as E x = 50 and E x = 0 according to their positional coordinates. fresh devices is subjected to 1 ks GIDL biases, as shown in Figure 5. When a moderate GIDL bias (VG,GIDL = 0.5 V, VD,GIDL = −2.5 V) is applied, the recovery of VT is relatively low, measuring approximately 27 mV. However, under high GIDL biases (by either increasing VG,GIDL or VD,GIDL), the recovery of VT exceeds 100 mV. It can be seen that at high gate-todrain electric fields, a large number of electrons are injected into the gate oxide, which greatly contributes to VT recovery [30]. Moreover, after applying a high GIDL bias, a degradation of approximately 12 mV/dec in SS can be observed. However, no SS degradation is observed at a moderate GIDL bias. Furthermore, a physical explanation is given with the aid of TCAD simulation. The electric field distributions of the device under different GIDL biases are simulated. Cutting vertically the center of gate along the channel direction, the 2-D view of the electric field distributions is shown in Figure 6. As VGD increases from 3 V to 4 V, the channel electric field changes significantly at two positions: one near the drain region, and the other along the channel surface. The 1-D electric field, cut along the surface of oxide layer in 2-D view in Figure 6, is shown in Figure 7a. It is shown that the electric field peaks near the drain region. Then, this peak electric field and the channel center electric field are extracted in Figure 7b and named as Ex = 50 and Ex = 0 according to their positional coordinates. As V GD increases from 3 V to 4 V, E x = 50 and E x = 0 increase by 1.26 and 6.89 times, respectively. As shown in Figure 8, the influences of these two electric fields will be discussed separately. During HCD stress, the channel hot holes near the drain region are captured by the oxide traps in gate dielectric, resulting in the V T degradation. When a GIDL bias is applied, the strong positive electric field near the drain region promotes the trapped holes to be released, which results in V T recovery [31]. The higher E x = 50 at V GD = 4 V corresponds to the higher V T recovery ratio (114.7%) in Figure 4. While a high V GD is also like applying a PBTI stress to the device, part of electrons in the channel are captured by the HfO 2 traps, which also results in the recovery in V T [32]. The higher E x = 0 at V GD = 4 V is the main cause of over 100 mV V T recovery in Figure 5. More discharged holes and trapped electrons directly lead to the over-recovery phenomenon observed at high GIDL biases. As VGD increases from 3 V to 4 V, Ex = 50 and Ex = 0 increase by 1.26 and 6.89 times, respectively. As shown in Figure 8, the influences of these two electric fields will be discussed separately. During HCD stress, the channel hot holes near the drain region are captured by the oxide traps in gate dielectric, resulting in the VT degradation. When a GIDL bias is applied, the strong positive electric field near the drain region promotes the trapped holes to be released, which results in VT recovery [31]. The higher Ex = 50 at VGD = 4 V corresponds to the higher VT recovery ratio (114.7%) in Figure 4. While a high VGD is also like applying a PBTI stress to the device, part of electrons in the channel are captured by the HfO2 traps, which also results in the recovery in VT [32]. The higher Ex = 0 at VGD = 4 V is the main cause of over 100 mV VT recovery in Figure 5. More discharged holes and trapped electrons directly lead to the over-recovery phenomenon observed at high GIDL biases.   As VGD increases from 3 V to 4 V, Ex = 50 and Ex = 0 increase by 1.26 and 6.89 times, respectively. As shown in Figure 8, the influences of these two electric fields will be discussed separately. During HCD stress, the channel hot holes near the drain region are captured by the oxide traps in gate dielectric, resulting in the VT degradation. When a GIDL bias is applied, the strong positive electric field near the drain region promotes the trapped holes to be released, which results in VT recovery [31]. The higher Ex = 50 at VGD = 4 V corresponds to the higher VT recovery ratio (114.7%) in Figure 4. While a high VGD is also like applying a PBTI stress to the device, part of electrons in the channel are captured by the HfO2 traps, which also results in the recovery in VT [32]. The higher Ex = 0 at VGD = 4 V is the main cause of over 100 mV VT recovery in Figure 5. More discharged holes and trapped electrons directly lead to the over-recovery phenomenon observed at high GIDL biases.

Oxide Trap Behaviors during GIDL Repairing
To further analyze the trap behaviors during the GIDL repairing process, DMP experiments are carried out. A group of fresh p-FinFETs is subjected to −2 V HCD stress for 200 s, followed by a 1 ks GIDL repairing process at different GIDL biases. The repaired devices are again applied with the same HCD stress and then discharged following the waveform in Figure 2. Additionally, ∆V T~VOV relationships under different GIDL biases are obtained in Figure 9a. Then, ∆V T is converted into the effective trap density (∆N T ) following the equation ∆N T = |∆V T | × C ox / q [23]. V OV is converted into the corresponding energy level E f relative to E v , i.e., E f -E v . Additionally, the ∆N T~( E f -E v ) relationships under different GIDL biases are obtained in Figure 9b. Finally, the energy density of ∆N T (∆D T ) is Nanomaterials 2023, 13, 1259 8 of 12 obtained by differentiating ∆N T against E f -E v , and the results are shown in Figure 10a. The detailed processing flow can be seen in the previous research [10]. For comparison, a group of devices under the same HCD stress are directly discharged without GIDL repair. Additionally, the energy density of pre-existing traps (∆D HT ) is extracted through the multi-DMP method separately, which is represented by a black curve [24]. 200 s, followed by a 1 ks GIDL repairing process at different GIDL biases. The repaired devices are again applied with the same HCD stress and then discharged following the waveform in Figure 2. Additionally, ΔVT ~ VOV relationships under different GIDL biases are obtained in Figure 9a. Then, ΔVT is converted into the effective trap density (ΔNT) following the equation ΔNT = |ΔVT| × Cox / q [23]. VOV is converted into the corresponding energy level Ef relative to Ev, i.e., Ef-Ev. Additionally, the ΔNT ~ (Ef-Ev) relationships under different GIDL biases are obtained in Figure 9b. Finally, the energy density of ΔNT (ΔDT) is obtained by differentiating ΔNT against Ef-Ev, and the results are shown in Figure 10a. The detailed processing flow can be seen in the previous research [10]. For comparison, a group of devices under the same HCD stress are directly discharged without GIDL repair. Additionally, the energy density of pre-existing traps (ΔDHT) is extracted through the multi-DMP method separately, which is represented by a black curve [24].   s, followed by a 1 ks GIDL repairing process at different GIDL biases. The repaired devices are again applied with the same HCD stress and then discharged following the waveform in Figure 2. Additionally, ΔVT ~ VOV relationships under different GIDL biases are obtained in Figure 9a. Then, ΔVT is converted into the effective trap density (ΔNT) following the equation ΔNT = |ΔVT| × Cox / q [23]. VOV is converted into the corresponding energy level Ef relative to Ev, i.e., Ef-Ev. Additionally, the ΔNT ~ (Ef-Ev) relationships under different GIDL biases are obtained in Figure 9b. Finally, the energy density of ΔNT (ΔDT) is obtained by differentiating ΔNT against Ef-Ev, and the results are shown in Figure 10a. The detailed processing flow can be seen in the previous research [10]. For comparison, a group of devices under the same HCD stress are directly discharged without GIDL repair. Additionally, the energy density of pre-existing traps (ΔDHT) is extracted through the multi-DMP method separately, which is represented by a black curve [24].  As can be seen from Figure 10a, the overall degradation of HCD can be divided into three components: pre-existing traps below E v , and two types of generated oxide traps in the bandgap. Generated trap 1 is at 0.2 eV below the mid-gap of silicon, and trap 2 is located around E c of silicon. The pre-existing traps are mainly induced by the fabrication process and cannot be repaired by GIDL bias. While generated traps show clear dependence with applied GIDL biases. At a moderate GIDL bias of V GD = 3 V, when a new round of HCD stress is applied, the ∆D T of both trap 1 and trap 2 are reduced by 48% and 9% compared to that under HCD, respectively. While at a high GIDL bias of V GD = 4 V, the ∆D T of trap 2 is 34% higher than that under HCD. In addition, the energy position of trap 1 tends to approach E c after repair, while the position of trap 2 remains unchanged. To make a clear comparison, ∆D T was integrated between E v and E c to extract ∆N T , as shown in Figure 10b. As V GD increases from 3 V to 4 V, ∆N T is increased by 46%. It can be seen that, after applying a moderate GIDL bias, the oxide trap density is effectively reduced in the next round of HCD stress. However, at high GIDL biases, although more generated oxide traps are discharged after repair, they are re-charged in the next round of HCD stress, which results in the further generation of oxide trap 2.
To verify the effectiveness of different GIDL biases on long-term HCD recovery, multiple cycles of HCD and GIDL are applied, and the results are shown in Figure 11a. At a high GIDL bias of V GD = 4 V, the repaired device exhibits a lower V T (below the pre-stress value) but shows more severe degradation in the next round of HCD stress. As the HCD/GIDL cycle progressed, the degraded ∆V T and recovered ∆V T in each cycle gradually tended to be the same. As can be seen from Figure 11b, the stabilized ∆V T at high GIDL bias is almost 99.4% higher than that at moderate GIDL bias, which corresponds to the higher ∆N T at high GIDL bias in Figure 10b. The consistent trends between ∆N T and ∆V T illustrate that the cyclic charge-discharge behavior of oxide traps results in the dynamic equilibrium between V T degradation and recovery. To ensure the reliable operation of p-FinFETs under long-term HCD stress, moderate GIDL bias is recommended to ensure the minimum ∆V T under cyclic stress.
As can be seen from Figure 10a, the overall degradation of HCD can be divided into three components: pre-existing traps below Ev, and two types of generated oxide traps in the bandgap. Generated trap 1 is at 0.2 eV below the mid-gap of silicon, and trap 2 is located around Ec of silicon. The pre-existing traps are mainly induced by the fabrication process and cannot be repaired by GIDL bias. While generated traps show clear dependence with applied GIDL biases. At a moderate GIDL bias of VGD = 3 V, when a new round of HCD stress is applied, the ΔDT of both trap 1 and trap 2 are reduced by 48% and 9% compared to that under HCD, respectively. While at a high GIDL bias of VGD = 4 V, the ΔDT of trap 2 is 34% higher than that under HCD. In addition, the energy position of trap 1 tends to approach Ec after repair, while the position of trap 2 remains unchanged. To make a clear comparison, ΔDT was integrated between Ev and Ec to extract ΔNT, as shown in Figure 10b. As VGD increases from 3 V to 4 V, ΔNT is increased by 46%. It can be seen that, after applying a moderate GIDL bias, the oxide trap density is effectively reduced in the next round of HCD stress. However, at high GIDL biases, although more generated oxide traps are discharged after repair, they are re-charged in the next round of HCD stress, which results in the further generation of oxide trap 2.
To verify the effectiveness of different GIDL biases on long-term HCD recovery, multiple cycles of HCD and GIDL are applied, and the results are shown in Figure 11a. At a high GIDL bias of VGD = 4 V, the repaired device exhibits a lower VT (below the pre-stress value) but shows more severe degradation in the next round of HCD stress. As the HCD/GIDL cycle progressed, the degraded ΔVT and recovered ΔVT in each cycle gradually tended to be the same. As can be seen from Figure 11b, the stabilized ΔVT at high GIDL bias is almost 99.4% higher than that at moderate GIDL bias, which corresponds to the higher ΔNT at high GIDL bias in Figure 10b. The consistent trends between ΔNT and ΔVT illustrate that the cyclic charge-discharge behavior of oxide traps results in the dynamic equilibrium between VT degradation and recovery. To ensure the reliable operation of p-FinFETs under long-term HCD stress, moderate GIDL bias is recommended to ensure the minimum ΔVT under cyclic stress. Finally, the energy level diagrams of the two generated traps are given in Figure 12. As described in the As-grown-generation (AG) model [33], two types of oxide traps with different discharge characteristics have been observed in the silicon energy band. One of them captures a hole without energy level changing, which corresponds to trap 2 around E c . Due to the shallow energy level of trap 2, it will be charged first during the second round of HCD stress, which corresponds to the higher ∆D T peak observed in Figure 10a. While trap 1 is a type of energy alternating defects (EADs), the energy position shifts towards E c after capturing a hole. Trap 1 is located at a relatively deep level (0.2 eV below mid-gap of silicon), which will be fully charged only after a complete discharge. Therefore, under a moderate GIDL bias of V GD = 3 V, the ∆D T of trap 1 shows a 48% decrease compared to HCD. For the convenience of reading, all abbreviations and notations frequently used in this article can be seen in Table 2.
Ec. Due to the shallow energy level of trap 2, it will be charged first during the second round of HCD stress, which corresponds to the higher ΔDT peak observed in Figure 10a. While trap 1 is a type of energy alternating defects (EADs), the energy position shifts towards Ec after capturing a hole. Trap 1 is located at a relatively deep level (0.2 eV below mid-gap of silicon), which will be fully charged only after a complete discharge. Therefore, under a moderate GIDL bias of VGD = 3 V, the ΔDT of trap 1 shows a 48% decrease compared to HCD. For the convenience of reading, all abbreviations and notations frequently used in this article can be seen in Table 2.

Conclusions
In this article, the GIDL repairing process is carried out with the UFM technique, and trap generations during GIDL repair are experimentally investigated. At a high GIDL bias of VGD = 4 V, the VT recovery ratio reaches 114.7%. With a 6.89 times increase in the channel electric field, more PBTI components are introduced at high VGD, which are responsible for additional electron trapping and interface trap generation. At a moderate GIDL bias of VGD = 3 V, the effective density of generated oxide trap 1 (at 0.2 eV below mid-gap of silicon) and trap 2 (around Ec of silicon) are reduced by 48% and 9% in the next round of HCD stress. However, a high GIDL bias will lead to 34% further generation of trap 2. Furthermore, two generated traps show different charge-discharge properties, which corresponds to two types of oxide traps described in AG model. After multiple cycles of HCD/GIDL tests, the degraded and recovered VT reaches the same. The dynamic equilibrium between VT degradation and recovery can be attributed to the cyclic charge-discharge behaviors of oxide traps. To ensure long-term HCD reliability, a moderate GIDL bias is recommended.   Channel electric field peak near the drain region (at x = 50) E x = 0 Channel center electric field (at x = 0) ∆N T Effective trap density ∆D T Energy density of ∆N T E v / E c Valance/conduction energy band of silicon

Conclusions
In this article, the GIDL repairing process is carried out with the UFM technique, and trap generations during GIDL repair are experimentally investigated. At a high GIDL bias of V GD = 4 V, the V T recovery ratio reaches 114.7%. With a 6.89 times increase in the channel electric field, more PBTI components are introduced at high V GD , which are responsible for additional electron trapping and interface trap generation. At a moderate GIDL bias of V GD = 3 V, the effective density of generated oxide trap 1 (at 0.2 eV below mid-gap of silicon) and trap 2 (around E c of silicon) are reduced by 48% and 9% in the next round of HCD stress. However, a high GIDL bias will lead to 34% further generation of trap 2. Furthermore, two generated traps show different charge-discharge properties, which corresponds to two types of oxide traps described in AG model. After multiple cycles of HCD/GIDL tests, the degraded and recovered V T reaches the same. The dynamic equilibrium between V T degradation and recovery can be attributed to the cyclic chargedischarge behaviors of oxide traps. To ensure long-term HCD reliability, a moderate GIDL bias is recommended.