Search Results (57)

In this paper, complementary metal-oxide semiconductor (CMOS) circuit realization of a low-pass elliptic filter of order (1 + α) is realized using the inverse follow-the-leader feedback (IFLF) topology. The transfer functions to approximate the passband and stopband ripple characteristics of the second-order elliptic low-pass filter are synthesized using the nonlinear least squares (NLS) optimization routine. The elliptic filters of orders 1.4, 1.6, and 1.8 are designed using a cross-coupled operational transconductance amplifier (OTA) in the United Microelectronics Corporation (UMC) 180 nm CMOS process. The dynamic range of the filter was found to be 49.7 dB, 52.08 dB, and 54.02 dB for an order of 1.4, 1.6, and 1.8, respectively. The circuit simulation results such as magnitude, phase, transient, and group delay plots, are validated with the MATLAB simulation plots. Monte Carlo and PVT analyses have demonstrated the accuracy and robustness of the design. The proposed approach supports quality education and industry, innovation, and infrastructure. Full article

The proposed work introduces a sizing algorithm to achieve a desired linear transconductance in the optimization of operational transconductance amplifiers (OTAs) by applying the $g_m/I_D$ method to find the initial width (W) and length (L) sizes of the transistors. These size values are used to run the non-dominated sorting genetic algorithm (NSGA-II) to perform a multi-objective optimization of three OTA topologies. The $g_m/I_D$ method begins with transistor characterization using MATLAB R2024a generated look-up tables (LUTs), which map normalized transconductance of the transistor channel dimensions, and key performance metrics of a complementary metal–oxide–semiconductor (CMOS) technology. The LUTs guide the initial population generation within NSGA-II during the optimization of OTAs to achieve not only a desired transconductance but also accuracy alongside linearity, high DC gain, low power consumption, and stability. The feasible W/L size solutions provided by NSGA-II are used to enhance the CMOS design of a memristor emulator, where the OTA with the desired transconductance is adapted to tune the behavior of the memristor, demonstrating improved pinched hysteresis loop characteristics. In addition, process, voltage and temperature (PVT) variations are performed by using TSMC 180 nm CMOS technology. The memristor-based on optimized OTAs is used to design a Leaky Integrate-and-Fire (LIF) neuron, which produces identical spike counts (seven spikes) under the same input conditions, though the time period varied with a CMOS inverter scaling. It is shown that increasing transistor widths by 100 in the inverter stage, the spike quantity is altered while changing the spiking period. This highlights the role of device sizing in modulating LIF neuron dynamics, and in addition, these findings provide valuable insights for energy-efficient neuromorphic hardware design. Full article

This paper presents a new operational transconductance amplifier (OTA) design for batteryless biomedical front-ends. The proposed OTA operates in the subthreshold region and utilizes self-cascode devices to achieve ultra-low power, low noise, and a high common-mode rejection ratio ($CMRR$). Post-layout simulations in Cadence, using 45 nm CMOS technology with 0.9 V supply voltage, show a power consumption of 49.3 nW, a $CMRR$ of 144.9 dB, an input-referred noise of 4.51 $\mathsf{\mu }{\mathrm{V}}_{\mathrm{rms}}$ integrated over 0.5–208 Hz, and a noise efficiency factor of 1.023 with a core silicon area of 0.00138 mm². Using the proposed OTA, we implemented a 10-channel neural recording amplifier for Local Field Potentials (LFPs) based on a capacitively coupled, capacitive-feedback (CC-CF) topology with a body-driven pseudo-resistor high-pass path. The system achieves a total $CMRR$ ≥ 70 dB and an estimated power of 494.2 nW for 10 channels. Compared with prior art, the proposed OTA offers competitive noise efficiency and common-mode rejection at lower power, making it a viable building block for batteryless neural and biomedical sensing front-ends. Full article

Parallel-type slew-rate enhancers (PSREs) improve the driving capability of operational transconductance amplifiers (OTAs) for large capacitive loads. While capacitive-boosting (CB) techniques enhance PSRE efficiency in fully-differential designs, their application to single-ended configurations—common in off-chip load driving—remains unexplored. This work identifies a critical limitation of standard CB in single-ended unity-gain buffers: severe slew-rate degradation due to large common-mode input swings. To overcome this, we propose a novel split CB (SCB) technique for single-ended PSREs that strategically divides the boosting capacitance. Simulated in a 0.18-µm CMOS process, the proposed method achieves a ×5.53 reduction in settling time compared to standard CB when driving a 1-nF load. With only 4 µA quiescent current under a 3.3-V supply, it attains a 1% settling time of 2.56 µs for 2.64-V steps, demonstrating robust performance across process-voltage-temperature variations. This technique enables low-power, high-speed interfaces for drivers of off-chip devices. Full article

Energy-efficient integrated circuits require scaled-down supply voltages, posing challenges for analog design, particularly for operational transconductance amplifiers (OTAs) essential in high-accuracy CMOS feedback systems. Below 1 V, gate-driven OTAs are limited in common-mode input range and minimum supply voltage. This work investigates CMOS Bulk-Driven (BD) sub-threshold techniques as an efficient alternative for ultra-low voltage (ULV) and ultra-low power (ULP) designs. Although BD overcomes MOS threshold voltage limitations, historical challenges like lower transconductance, latch-up, and layout complexity hindered its use. Recent advancements in CMOS processes and the need for ULP solutions have revived industrial interest in BD. Through theoretical analysis and computer simulations, we explore BD topologies for ULP OTA input stages, classifying them as tailed/tail-less and class A/AB, evaluating their effectiveness for robust analog design, while offering valuable insights for circuit designers. Full article

In this paper, we present a novel enhanced recycling folded cascode (ERFC) operational transconductance amplifier (OTA), which exhibits high efficiency and a fast transient response under weak inversion. Our innovative combination of adaptive biasing with nested local feedback (ABNLF) effectively enhances the input transconductance and slew rate (SR), thus improving the transient response. By incorporating coupling capacitors at the output stage, we achieve a stable operating region with large signal responses. Both the traditional RFC OTA and the proposed ERFC OTA were designed in a 0.18 $\mathsf{\mu }$m CMOS process, operating at a power supply of 1.8 V, with quiescent currents of 8 $\mathsf{\mu }$A and 10.4 $\mathsf{\mu }$A, respectively. Post-layout simulations reveal a remarkable enhancement in the proposed ERFC OTA over the traditional RFC OTA, with the SR and gain–bandwidth (GBW) surging by 120- and 5.95-fold, respectively. This advancement boosts the efficiency of the traditional RFC OTA and provides an impressive figure of merit (FoM) of 130.04 (V/$\mathsf{\mu }$s)·pF/$\mathsf{\mu }$A. Full article

In this paper, a novel multiple-input operational transconductance amplifier (MI-OTA) is proposed. The MI-OTA can be obtained by using the multiple-input bulk-driven MOS transistor (MIBD MOST) technique. The circuit structure is simple, can operate with a supply voltage of 0.5 V, and consumes 937 pW at a current setting of 625 pA. The proposed MI-OTA was used to implement a high-order multiple-input voltage-mode universal filter. The proposed filter can provide non-inverting and inverting low-pass, high-pass, band-pass, band-stop, and all-pass transfer functions to the same topology. In addition, it has a high input impedance and does not need any inverted input signals, so there is no additional buffering circuit. The proposed filter can be used for biological signal processing. The proposed MI-OTA and the second-order universal filter were simulated in Cadence using CMOS process parameters of 0.18 μm from TSMC to verify the functionality and performance of the new structures. Full article

This paper introduces a fully integrated memristive chaotic circuit, which is based on a voltage-controlled oscillator (VCO). The circuit employs a fully integrated architecture that offers reduced power consumption and a smaller footprint compared to the use of discrete components. Specifically, the VCO is utilized to generate the oscillatory signal, whereas the memristor emulator circuit serves as the nonlinear element. The memristor emulator circuit is constructed using a single operational transconductance amplifier (OTA), two transistors, and a grounded capacitor. This straightforward design contributes to diminished power usage within the chip’s area. The VCO incorporates a dual delay unit and implements current compensation to enhance the oscillation frequency and to broaden the VCO’s tunable range. Fabricated using the SMIC 180 nm CMOS process, this chaotic circuit occupies a mere 0.0072 mm² of chip area, demonstrating a design that is both efficient and compact. Simulation outcomes indicate that the proposed memristor emulator is capable of operating at a maximum frequency of 300 MHz. The memristive chaotic circuit is able to produce a chaotic oscillatory signal with an operational frequency ranging from 158 MHz to 286 MHz, powered by a supply of 0.9 V, and with a peak power consumption of 3.5553 mW. The Lyapunov exponent of the time series within the resultant chaotic signal spans from 0.2572 to 0.4341. Full article

This paper presents a low-voltage, low-power voltage-to-current converter (V-I Converter) implemented in TSMC 40 nm CMOS technology. Operating at a supply voltage of 0.45 V with an input range of 0.1 V to 0.3 V, the proposed circuit achieves a temperature coefficient of 54.68 ppm/°C, which is at least 2× better than prior works, ensuring stable performance across a wide temperature range (−20 °C to 80 °C). The design employs a three-stage operational transconductance amplifier (OTA) with a Q-reduction frequency compensation technique to produce programmable output currents while maintaining a power dissipation of less than 2.76 μW. With a bandwidth of 34.45 kHz and a total harmonic distortion (THD) of −56.66 dB at 1 kHz and 0.1 V_PP input signal, the circuit demonstrates high linearity and low power consumption under ultra-low voltage design scenarios. These features make the proposed V-I Converter highly suitable for energy-constrained applications such as biomedical sensors, energy harvesting systems, and IoT nodes, where low power consumption and temperature stability are critical parameters. Full article

This paper introduces shadow filters that employ multiple-input operational transconductance amplifiers (MI-OTAs) as the active component. Two configurations of shadow filters are proposed. The first configuration, in contrast to previous designs, enables the adjustment of the quality factor without affecting the passband gains of the BPF, LPF, and HPF, thus achieving optimal frequency responses for these filters. The second configuration allows for the variation of the natural frequency without impacting the passband gains of the HPF, LPF, and BPF, maintaining constant passband gains. Moreover, the natural frequency can be electronically controlled by modifying parameters of the original biquad filters, providing advantages in compensating for process, voltage, and temperature variations. The MI-OTA is designed to provide multiple-input differential terminals using the multiple-input bulk-driven MOS transistor (MIBD-MOST) technique, allowing differential input signals to be converted into current output through its transconductance gain. The OTA operates at a supply voltage of 450 mV and consumes 81 nW of power, with the MOS transistors operating in weak inversion. The OTA and shadow filters were designed and simulated using a 0.18 µm CMOS process to validate the functionality and performance of the proposed circuits. Full article

This paper presents the CMOS circuit realization of a low-pass Inverse Chebyshev fractional-order filter (FOF) of order (1 + α) using the inverse-follow-the-leader feedback (IFLF) topology. A nonlinear least squares optimization routine is used to determine the coefficients of the fractional-order transfer function to approximate the stop-band characteristics. The Inverse Chebyshev FOF of orders 1.3, 1.6, and 1.9 using cross-coupled operational transconductance amplifier (OTA) was designed in united microelectronics corporation (UMC) 180 nm complementary metal–oxide–semiconductor process. The MATLAB and Cadence Spectre simulations are used to validate the implementation of the fractional-order filter of orders 1.3, 1.6 and 1.9. The dynamic range (DR) of the filter is found to be 83.04 dB, 86.13 dB, and 84.71 dB, respectively, for order of 1.3, 1.6, and 1.9. The simulation results such as magnitude response, transient plot, Monte Carlo, and PVT plots, have justified the design accuracy. Full article

An approach to design analog building blocks based on digital standard cells is presented in this work. By ensuring that every CMOS inverter from a standard-cell library operates with a well-defined quiescent current and output voltage, the suggested method makes it possible to construct analog circuits that are resistant against PVT variations. The method uses the local supply voltages connected to the source terminals of the p-channel and n-channel MOS transistors of the standard-cell inverters as control inputs. It is based on adaptive supply voltage generator (ASVG) reusable blocks, which are comparable to those used in digital applications to handle process variations. All of the standard-cell inverters used for analog functions receive the local supply voltages produced by the ASVGs, which enable setting each cell’s quiescent current to a multiple of a reference current and each cell’s static output voltage to an appropriate reference voltage. Both the complete custom design of the ASVG blocks and a theoretical study of the feedback loop of the ASVG are presented. An application example through the design of a fully synthesizable two-stage operational transconductance amplifier (OTA) is also provided. The TSMC 180 nm CMOS technology has been used to implement both the OTA and the ASV generators. Simulation results have demonstrated that the proposed approach allows to accurately set the quiescent current of standard-cell inverters, dramatically reducing the effect of PVT variations on the pmain performance parameters of the standard-cell-based two-stage OTA. Full article

This paper presents the design, simulation, prototyping, and measurement results of a digitally tunable fourth order Gm-C low-pass filter (LPF) for multi-standard radio receivers. The LPF cut-off frequency can be tunned by digitally selecting the transconductance of the basic reconfigurable operational transconductance amplifiers (OTAs) that compose the circuit. Four operation modes allow for control of the OTA transconductances and, consequently, the scaling of power consumption. The filter was designed and prototyped in a 1.8 V 180 nm CMOS process. The measurement results indicate that the configurability provides a cutoff frequency of 1.90/3.56/6.07/8.15 MHz with a power consumption ranging from 9.9 to 13.1 mW. The designed filter achieves an IIP3 of 8.17 dBm for a signal bandwidth of 8.15 MHz. The performance, in terms of power dissipation, noise, and cut-off frequency, is at the same order of magnitude compared to recent related works reported in the literature. The advantages are a compact area, small sensitivity to component mismatches, and low design complexity. The proposed filter presents electrical characteristics suitable for the application in radio receivers for multi-carrier WCDMA signals. Full article

This paper presents a new multiple-input single-output voltage-mode universal filter employing four multiple-input operational transconductance amplifiers (MI-OTAs) and three grounded capacitors suitable for low-voltage low-frequency applications. The quality factor (Q) of the filter functions can be tuned by both the capacitance ratio and the transconductance ratio. The multiple inputs of the OTA are realized using the bulk-driven multiple-input MOS transistor technique. The MI-OTA-based filter can also offer many filtering functions without additional circuitry requirements, such as an inverting amplifier to generate an inverted input signal. The proposed filter can simultaneously realize low-pass, high-pass, band-pass, band-stop, and all-pass responses, covering both non-inverting and inverting transfer functions in a single topology. The natural frequency and the quality factors of all the filtering functions can be controlled independently. The natural frequency can also be electronically controlled by tuning the transconductances of the OTAs. The proposed filter uses a 1 V supply voltage, consumes 120 μW of power for a 5 μA setting current, offers 40 dB of dynamic range and has a third intermodulation distortion of −43.6 dB. The performances of the proposed circuit were simulated using a 0.18 μm TSMC CMOS process in the Cadence Virtuoso System Design Platform to confirm the performance of the topology. Full article

In this paper, we present a 0.3 V body-driven operational transconductance amplifier (OTA) that exploits a biasing approach based on the use of a replica loop with gain. An auxiliary amplifier is exploited both in the current mirror load of the first stage of the OTA and in the replica loop in order to achieve super-diode behavior, resulting in low mirror gain error, which enhances CMRR, and robust biasing. Common-mode feedforward, provided by the replica loop, further enhances CMRR. Simulations in a 180 nm CMOS technology show 65 dB gain with 2 kHz unity-gain frequency on a 200 pF load when consuming 9 nW. Very high linearity with a 0.24% THD at 90% full-scale and robustness to PVT variations are also achieved. Full article