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Article

A Low-Voltage Low-Power Voltage-to-Current Converter with Low Temperature Coefficient Design Awareness

School of Electrical and Electronics Engineering, Nanyang Technological University, Singapore 639798, Singapore
*
Author to whom correspondence should be addressed.
Sensors 2025, 25(4), 1204; https://doi.org/10.3390/s25041204
Submission received: 1 January 2025 / Revised: 9 February 2025 / Accepted: 14 February 2025 / Published: 16 February 2025
(This article belongs to the Special Issue Advanced Interface Circuits for Sensor Systems (Volume II))

Abstract

:
This paper presents a low-voltage, low-power voltage-to-current converter (V-I Converter) implemented in TSMC 40 nm CMOS technology. Operating at a supply voltage of 0.45 V with an input range of 0.1 V to 0.3 V, the proposed circuit achieves a temperature coefficient of 54.68 ppm/°C, which is at least 2× better than prior works, ensuring stable performance across a wide temperature range (−20 °C to 80 °C). The design employs a three-stage operational transconductance amplifier (OTA) with a Q-reduction frequency compensation technique to produce programmable output currents while maintaining a power dissipation of less than 2.76 μW. With a bandwidth of 34.45 kHz and a total harmonic distortion (THD) of −56.66 dB at 1 kHz and 0.1 VPP input signal, the circuit demonstrates high linearity and low power consumption under ultra-low voltage design scenarios. These features make the proposed V-I Converter highly suitable for energy-constrained applications such as biomedical sensors, energy harvesting systems, and IoT nodes, where low power consumption and temperature stability are critical parameters.

1. Introduction

As research advances in the areas of microsensors, biomedical implantable devices, portable electronic equipment, and other applications where speed is not of concern, there is an increasing demand for ultra-low voltage and low power consumption. Furthermore, the continuous down-scaling of the process results in the gate oxide becoming thinner. It is then more susceptible to breakdown, so the supply voltage needs to drop to ensure device stability [1]. To meet this demand, designing circuits with MOS transistors operating in the subthreshold region has emerged as a widespread approach since the mid-1970s [2]. Notably, the subthreshold CMOS circuits offer a high gm/ID ratio and exceptional energy efficiency [3].
The V-I Converter converts voltage signals to current signals, and this becomes a significant analog signal-processing block for different usages in integrated circuits and systems. Based on the function of the V-I Converter, a Gm-C filter, a data converter, a multiplier and a voltage-to-frequency converter, which are the basic circuits for use in sensors, can be built [4,5,6,7]. For biomedical sensors, the V-I Converter can be applied for the analog pre-processing of very low biomedical signals. It is also suitable for use as a low-frequency analog front-end for biomedical sensor interfaces [8]. In terms of portable devices, the V-I Converter adjusts the output current by feeding back current to the input voltage of a hearing aid device [9,10]. In a MEMS gyroscope, the V-I converter is used to precisely and dynamically adjust the temperature of the heater [11]. In addition, in the application of a VCO-based sensor, a voltage-to-current converter is needed to generate the feedback current in order to achieve a small noise variation at the output of the VCO [12]. Therefore, the V-I Converter can be considered a common basic block for sensor applications.
The V-I Converter has a universal expression, as follows:
Iout = K∙Vin,
where Iout is the output current, Vin is the input voltage and K is a constant.
In the typical design of a V-I Converter, designers focus more on linearity. Turning to very low-voltage applications, circuit designers also seek low power consumption. On top of that, trade-off parameters like bandwidth (BW), power supply rejection ratio (PSRR), common mode rejection ratio (CMRR), input-referred noise, total harmonic distortion (THD), rail-to-rail input range, and power consumption are also addressed. In previous research, temperature stability has been given little consideration. In very low-voltage circuits, temperature drift can have a significant effect on the precision. For example, the variation arising from temperature drift may be fed back or amplified and processed within the sensor system, resulting in an error in the output of the sensor. Temperature instability is particularly fatal in low-frequency, low-voltage sensor circuits because it consumes the available headroom under a limited supply voltage.
This raises the motivation of this work, which aims to design a very low-voltage voltage-to-current converter with design awareness for achieving a low temperature coefficient. In order to prepare the V-I Converter for application in a variety of scenarios, the output current is made programmable so as to yield flexibility and meet different requirements in terms of precision in the context of process variation. The following section of this paper is organized as follows. Section 2 reviews the previous design of the V-I Converter. Section 3 describes the design of the proposed 0.45 V V-I Converter with temperature-compensated output currents. Section 4 presents the simulation results and discussions. Section 5 gives the conclusion.

2. Review of V-I Converters

A traditional voltage-to-current circuit is implemented by OTA, as shown in Figure 1. In this conventional structure, OTA always drives a MOSFET and the resistor in a negative feedback loop [13]. Negative feedback can make the negative input of the OTA match closely to the output voltage, achieving an output current approximately equal to Vin/RS. In this topology, the driving transistor is either an NMOS or a PMOS. As shown in Figure 1a, the NMOS is used as the driving transistor, and the output current is copied through the PMOS current mirror. The minimum supply voltage is about Vin,max + VDS0 + VSG1. Instead, the supply voltage can be further reduced to Vin,max + VSD1 if the PMOS is used as the driver transistor, as shown in Figure 1b.
The topology shown in Figure 1b is extended to another improved topology (Figure 2) [7], which is called the feedback voltage-attenuated (FBVA) V-I Converter.
In the FBVA structure, the OTA permits VC = Vin under a high-gain feedback loop. With voltage dividing the function according to the feedback resistors R1 and R2 of the OTAaux-M1-M4 feedback loop, VA becomes αVin, where α = R2/(R1 + R2). Then, the output current will become Iout = αVin∙K/Rs. As CC2 and RC2 create a zero to cancel a pole, this permits the FBVA V-I Converter to extend the bandwidth. Through the attenuation provided by the negative feedback loop, the FBVA V-I Converter displays low distortion levels. Despite this, this topology achieves improved temperature compensation over that of the conventional V-I Converter. However, this structure, making use of multiple OTAs, increases the complexity. Of particularly note, since it uses a cascade of transistors, it leads to an increase in supply voltage requirements.
Another reported circuit [14] consists of a differential pair with two nested feedback loops, as depicted in Figure 3. The two main loops (loop 1 and loop 2) consist of M1 and M2 and M5 and M6, used for reducing the input impedance through negative feedback. M3, M4 and the current source I1 comprise a flipped voltage follower, which is used to reduce the source impedance of M4, M1, and M2 such that the voltages of node X1 and node X2 are close to VB1. This meets the condition of passing equal current. The third loop, which consists of M5, M7, and M9, and the fourth loop, which consists of M6, M8, and M10, are the high-gain negative feedback loops. They further reduce the impedance of nodes X1 and X2 whilst transferring the input current to the output without replication. Besides this, the high-gain feedback loop helps reduce the mismatch between each pair of transistors. Overall, the circuit achieves a high degree of linearity for voltage-to-current conversion. However, this circuit still relies on high supply voltage.
To allow very low-voltage operation, a bulk-driven CMOS inverter-based tunable transconductor has been proposed [15]. As depicted in Figure 4, M5M12 form a positive feedback loop, which aims to provide a relatively large DC gain. All transistors operating in the subthreshold region permit the circuit to operate at a voltage as low as 0.25 V. Through the subthreshold current equation and the threshold voltage equation [15], the output current is derived as
i o = i p i n I B 2 V T γ p 2 n p 2 ϕ F p V D D V C M + γ n 2 n n 2 ϕ F n V C M V i n .
From (2), the overall transconductance of the proposed circuit is obtained as I B 2 V T γ p 2 n p 2 ϕ F p V D D V C M + γ n 2 n n 2 ϕ F n V C M .
The advantage of this design is that it provides a good trade-off, offering ultra-low supply voltage with good linearity whilst providing tunable transconductance. However, the bulk-driven transistors also suffer from several disadvantages, such as the use of the triple-well CMOS technology in realization [15], a higher input noise, a higher offset voltage [16] and higher fabrication costs when compared to the single-well CMOS technology. Moreover, the substrate channel PN junction is likely to latch-up in cases of not being properly designed, causing reliability issues.
In order to avoid the undesirable effects of bulk driving, another reported work [17] focused on gate driving as shown in Figure 5. Due to the larger transconductance of the device, this circuit shows better noise performance when compared to that of bulk-driven transistors. It also optimizes the swing range of the output voltage. The circuit also generates sinking and sourcing currents and exhibits a large input common-mode voltage range. However, the current I1 = (VDDPVIN)/R may be subject to the offset arising from the matching between the sourcing current and the sinking current. The input impedance of the circuit depends on the effective output impedance of the current mirror.

3. Proposed V-I Converter

3.1. V-I Converter Architecture

Figure 6 illustrates the topology of the proposed circuit. The circuit operates in the subthreshold region. This circuit consists of peripheral resistors, level shifters, and the OTAo. The resistors R1R4 are formed by PMOS devices, which have small sizes and are known as pseudo-resistor (PR) devices [18]. These PR devices display very high impedance properties so that there is no loading effect on the input source and the output stage of OTAo. The function of the level shifter is to raise the input voltages V1 and V2 to higher voltages V3 and V4 in order to satisfy the input voltage range of the OTAo and to produce an intentional temperature coefficient in the circuit. The OTAo consists of an OTAi, which consists of two stages with active loads and a third stage formed by the PMOS driver transistor that drives the resistor array with the temperature compensation. The output current will be IOUT = VOUT/Rarray. With R1 = R2 = R3 = R4 = R, VOUT = VIN. By choosing R1 = R2 = R3 = R4, a symmetrical circuit structure can be procued, which offers a good common mode rejection ratio.

3.1.1. Design of Pseudo Resistor (PR)

PR, which was introduced by Delbrück in 1984 [18], usually uses a PMOS transistor as a diode connection to operate in the cutoff region to provide an extremely large resistance. It is well-known and widely used for the acquisition of bioelectrical signals [19,20,21]. For the connection shown in Figure 7, if V1 is greater than V2, this structure is equivalent to a PMOS using a diode connection. If V1 is less than V2, the structure behaves like a bipolar transistor due to the positively biased PN junction formed by the drain of PMOS and the substrate. In this design, V1 is greater than V2, with V1V2 < |VTHP|, to allow PR to be in the cutoff region.
PR has an exponential I-V characteristic, and therefore poor linearity and a strong dependence on temperature and process. Another limitation of PR is the problem of current leakage due to parasitic effects. In diode-connected PRs, intrinsic leakage currents can exist in the diode formed between the p-substrate and the n-well of the PMOS transistor, thus affecting the output offset of the OTA [22]. As shown in Figure 8, Ic represents the current during normal conduction, whereas il represents the reverse leakage current of the parasitic diode. If V1 is connected to the high voltage terminal and V2 is connected to the low voltage terminal, an extra voltage drop is generated by il due to the leakage current in the reverse-biased diode. This phenomenon causes the mismatch at the two input ports of the OTA, leading to an output DC voltage offset. This problem will be further pronounced if the circuit features high gain. In order to suppress such a DC offset, the symmetric topology, depicted in Figure 6, is utilized to match the resistances in the positive and negative branches of the OTA. As such, the leakage current is treated as the common-mode signal and is rejected by the converter in a form amplifier topology.

3.1.2. Design of Level Shifter

The level shifter depicted in Figure 9 contains a startup circuit that comprises MB1, MB2, CB1, and CB2, a bias circuit that comprises MB3MB6, RB1, and a source follower formed by MS1 and MS2.
The bias current IBIAS is calculated as
I B I A S = n V T I n M R B 1 ,
where M denotes the ratio of aspect ratio of MB3 with respect to that of MB4 and MB1.
When the power is on, V5 rises to VDD, forcing MB1 to turn on and causing the ac shorting V7 to GND, thus making MB2 on. As a result, V6 is pulled high, which in turn causes the bias circuit to generate the bias current. V7 is then pulled high due to MB1’s operation, which causes MB2 to be turned off. V5 is pulled low after the bias current has been established. Then, MB1 is turned off. When the capacitive-based startup circuit has completed its action, it is isolated and no longer contributes any additional current, hence reducing power consumption.
MS2 and MS1 form a source follower with the gate-bulk driving transistor MS2. To raise identical voltage potential, the PMOS with gate-bulk connection uses a smaller size when compared to the PMOS with source-bulk connection. It is observed that the input-referred noise decreases with the increase in bias current in the level shifter. Although it permits lower input-referred noise, it degrades the temperature coefficient. On the contrary, the gate-bulk-connected PMOS can optimize such a trade-off. This is mainly because of the change in threshold voltage, which leads to a change in temperature coefficient, which favors the temperature compensation case.

3.1.3. Design of OTAo

Due to the low supply voltage, the OTA can only operate in the subthreshold region, and the VDS needs to be greater than 100 mV in order to allow the MOSFETs to operate in a valid region. Besides this, the use of a cascode structure to increase the DC gain is not permitted under ultra-low-voltage design. Although the two-stage topology on the basis of a single Miller compensation capacitor is simple and efficient in terms of size, the overall DC gain may be not sufficient to meet precision requirements due to the intrinsic low output impedance of CMOS devices in the 40 nm technology node. Therefore, in order to obtain an OTA with a large gain whilst operating in the subthreshold region, this OTA design is based on the modification of the amplifier structure [23], as shown in Figure 10a. The main difference is that of the passive temperature compensation resistor array replacing the active load in this design of the final output stage.
The system block diagram is shown in Figure 11, where gm1 is the transconductance of the first stage, contributed by M1. gmcf is the transconductance of M3. gm2 is the transconductance of the second stage, contributed by M5. gm3 is the transconductance of the third stage, contributed by M9. gmf is the transconductance of the feedforward path, used to generate the left half-plane (LHP) zero, contributed by M1, M3, and M8. Rcf is the effective output resistance of M1 and is approximately equal to 1/gmcf. R1 is the output resistance of the first stage. R2 is the output resistance of the second stage. R3 is the output resistance of the third stage, consisting of Rarray and the equivalent output impedance of M9 in parallel. Cpcf is the equivalent capacitance at the output of M1. Cp1 is the output capacitance of the first stage. Cp2 is the output capacitance of the second stage. C3 is the output capacitance of the third stage. C1, together with M3 and M4, forms a current buffer to reduce the potential large Q generated by the non-dominant pole, thus slowing down the sharp changes in phase. C2 is a Miller capacitor used to achieve pole splitting and increase the phase margin.
To analyze the loop stability of this OTAo, the following assumptions are made: (1) C1, C2, and C3 are larger than the internal capacitances of the circuit; (2) gm3 is larger than gm1, gmcf, and gm2; and (3) the gain of each gain stage (gm1R1, gm2R2, and gm3R3) > 1, except for gmcfRcf 1. Thus the transfer function can be approximated as follows:
H s = A D C 1 + s C 2 g m f g m 1 g m 2 1 + p 1 s 1 + s C 1 C 3 + C 2 g m 3 R c f C 2 g m 3 + C p 2 + C 1 C 3 g m 2 g m 3 s 2 ,
where the DC gain is ADC = gm1gm2gm3gmcfR1R2R3Rcf ≈ gm1gm2gm3R1R2R3, and the dominant pole is p1 = 1/(C2gm2gm3R1R2R3). Thus the gain-bandwidth product (GBW) is obtained as
G B W = A D C p 1 = g m 1 C 2
From (4), this OTAo yields a zero, as
z 1 = g m 1 g m 2 C 2 g m f
which is designed for phase lead such that the circuit derives a better phase margin. The relationship in the denominator of the transfer function H(s) is
C 1 C 3 + C 2 g m 3 R c f C 2 g m 3 2 4 C p 2 + C 1 C 3 g m 2 g m 3 .
The pair of complex poles becomes
w O = C 1 C 3 + C 2 g m 3 R c f C 2 g m 3 ± i 4 C p 2 + C 1 C 3 g m 2 g m 3 C 1 C 3 + C 2 g m 3 R c f C 2 g m 3 2 2 C p 2 + C 1 C 3 g m 2 g m 3 = g m 2 g m 3 C p 2 + C 1 C 3 .
Due to the complex conjugate poles, excessive Q values can occur. This causes the amplitude–frequency curve to display an overshoot effect. When this large Q occurs near the GBW, a sharp drop in the phase margin [24] is observed. The Q value is obtained as
Q = C p 2 C 3 g m 2 g m 3 C 2 g m 3 C 1 C 3 + C 2 g m 3 R c f .
To reduce Q, it is apparent from (9) that C1, as well as Rcf, needs to be increased. Besides this, the phase margin [23] is given as follows:
P M = 180 ° tan 1 G B W p 1 tan 1 G B W / w O Q 1 G B W / w O 2 + tan 1 G B W z 1 = 90 ° tan 1 G B W / w O Q 1 G B W / w O 2 + tan 1 G B W z 1 .
To achieve programmable output current, the resistor array uses a combination of three branches, as shown in Figure 12. In the process library design file, the resistor is given by
R = R 0 1 + T C 1 T 300 + T C 2 T 300 2 ,
where TC1 and TC2 are the first-order temperature coefficient and the second-order temperature coefficient, respectively, and R0 is the magnitude of the resistance at the temperature of 300 K. Based on the resistor–temperature relationship, the output current needed for this circuit, the P+ poly resistor without salicide, and the P+ poly resistor with salicide are chosen for each branch of the resistor array. The types and sizes of each device of the proposed V-I Converter are shown in Table 1.

3.2. Temperature Compensation of Proposed V-I Converter

Temperature compensation is mainly realized by OTAo and the resistor array, and in conjunction with the thermal effect contributed by the level shifter. The bias circuit is shown in Figure 10b, where MB13, MB14, CB5 and CB6 comprise the capacitive startup circuit. This constant-gm current source provides the tail current of OTAo, and it is given as
I M 0 = n V T I n W / L M B 18 W / L M 0 R B 3 .
It is noted that for a P+ poly resistor without salicide, RB3 is given by (11), where TC1 is negative and TC2 is positive, with the relationship |TC1| >> |TC2|. Thus, RB3 shows the CTAT effect. Then, the derivation of IM0 is obtained as
I M 0 T = n k I n W / L M B 18 W / L M 0 q R B 3 > 0 ,
It can be seen that IM0 is proportional to the absolute temperature (PTAT) current. IM3 is equal to 0.5IM0 and therefore also the PTAT current.
The current equation of PMOS operating in the subthreshold region is
I S = μ p T 0 T 0 T m p C o x V T 2 W L e V S G T + V T H P T n V T 1 e V S D T V T 1 λ V S D T μ p T 0 T 0 T m p C o x V T 2 W L e V S G T + V T H P T n V T 1 λ V S D T ,
with the electron mobility given as
μ p T = μ p T 0 T 0 T m p
and the threshold voltage given as
V T H P T = V T H P 0 + κ P T T 0
where the characteristic current in weak inversion IS = μp(T)CoxVT2, VTHP0 is the threshold voltage at T0 = 300 K, μp(T0) is the carrier mobility at T0 = 300 K, Cox is the capacitance of the gate oxide, W is the channel width, L is the channel length, VT = kT/q is the thermal voltage, k is Boltzmann’s constant, q is the electronic charge, and the subthreshold slope n is a constant between 1 and 3 [25,26]. n can be estimated to be 1.3 using this technology, which is convenient for theoretical calculation. mp is approximately 1.16, which is the exponential coefficient of μp(T) with respect to temperature, and κP is approximately 0.614 mV/K, which is the magnitude of the slope of VTHP(T). mp and κP are obtained from PMOS device simulation. Since VSD > 3 VT, this means that the exp[−VSD(T)/VT] term is small enough to be ignored, while λ is the channel length modulation factor. According to (14), the voltage VA in the first stage of OTAo (Figure 10) is
V A = V D D V S G 3 = V D D n k T q I n I M 3 T m p 2 μ p T 0 T 0 m p C o x k / q 2 W / L M 3 q κ P n k V T H P 0 , M 3 + κ P T 0 α 1 T I n α 2 T 1.84 α 3 + α 4 T C 1 T 300 + α 5 T C 2 T 300 2 α 6 ,
where ɑn (n = 1, 2, 3…) is the lumped constant. With MATLAB (version: R2023a) verification, VA can be considered as PTAT voltage. Due to the symmetrical structure of the first stage of OTAo, VO1 is equal to VA, which implies VO1 is also a PTAT voltage. Figure 13a shows the plot of VO1 against temperature.
This PTAT voltage couples to the input of the second stage in the OTAo. It generates the current through M5. Since M3 and M5 have different channel lengths, this results in different threshold voltages. According to the BSIM3v3 model [27], VTHP0 in Equation (16) can be written as
V T H 0 = V T H 0 + K 1 ϕ s V b s ϕ s K 2 V b s + K 1 1 + N L x L e f f 1 ϕ s Δ V T H ,
where K1, K2, NLx, and ∆VTH are parameters given in [27], V’ TH0 is the threshold voltage at zero substrate bias, and ϕs is the surface potential. As the channel length becomes shorter, the threshold voltage shows a greater dependence on the channel length. In this design, M5 has a smaller channel length than M3, causing the threshold voltage VTHP0,M5 to be less than VTHP0,M3. The current IM5 becomes
I M 5 = μ p T 0 T 0 m p C o x k 2 q 2 W L M 5 e q κ p n k e q V D D V O 1 + V T H P 0 , M 5 κ P T 0 n k T T 2 m p = W / L M 5 W / L M 3 I M 3 e q κ P n k e q V T H P 0 , M 5 V T H P 0 , M 3 n k T .
In (19), VTHP0,M5VTHP0,M3 is negative, resulting in the term e q V T H P 0 , M 5 V T H P 0 , M 3 / n k T , showing a PTAT effect. Since IM3 also has a PTAT effect, IM5 becomes a PTAT current. This current passes through M6 and generates the VC in Figure 10. VC can be represented as
V C = n k T q I n I M 5 T m n 1 μ n T 0 T 0 m n C o x k / q 2 W / L M 6 q κ N n k + V T H N 0 , M 6 + κ N T 0 α 7 T I n α 8 I M 5 T 0.5 α 9 + α 10 ,
where mn is approximately 1.5, and κN is approximately 1.589 mV/K. They are characterized by simulation in this technology. According to the analytical result, VC is also a PTAT voltage. Due to the balanced design, VO2 is approximately equal to VC and it displays the PTAT effect. This is verified with the plot of VO2 against the temperature, as illustrated in Figure 13b.
Assuming that the resistor array Rarray of the third stage has a temperature-independent property, the output current IM9 can be expressed as
I M 9 = μ p T 0 T 0 m p C o x k 2 q 2 W L M 9 e q κ P n k e q V D D V O 2 + V T H P 0 , M 9 κ P T 0 n k T T 2 m p = μ p T 0 μ n T 0 T 0 m p + m n C o x 2 k 4 q 4 W L M 9 W L M 6 e q κ P + κ N n k e q V D D V T H N 0 , M 6 + V T H P 0 , M 9 κ N T 0 κ P T 0 n k T I M 5 1 T 0.34 α 11 e α 12 T T 0.34 I M 5 1 ,
where ɑ12 is negative and it causes the term e α 12 / T to display a PTAT effect. Although I M 5 1 shows a CTAT effect, the term e α 12 / T T 0.34 is dominant, resulting in IM9 as a PTAT current. This PTAT current passes through Rarray and will generate the output voltage VOUT with PTAT characteristics. In order to ensure IM9 is temperature independent, Rarray needs to be positively temperature dependent so that VOUT/Rarray becomes temperature independent and achieves a low temperature coefficient for the output current. This can be synthesized using two types of poly resistors with opposite temperature coefficients. For the complete temperature compensation, the level shifter allows some modulation of the temperature coefficient to the output current. As depicted in Figure 9, the source follower MS2 uses a gate-bulk connection instead of a source-bulk connection. The use of gate-bulk connection reduces the |VTH| of PMOS and slightly modifies the trend of |VTH| with temperature, as shown in Figure 14.
Compared to PMOS with source-bulk connection, the trend of |VTH| has relatively low T.C. using the gate-bulk driven transistor in the source follower of the level shifter. According to (14), if the bias current is fixed, a more slowly decreasing |VTH| will improve the CTAT effect of the output voltage of the level shifter. This voltage entering into the OTAo will cause the PTAT effect of the output voltage of OTAi shown in Figure 6, which offers better temperature compensation. It allows the driven transistor to receive more CTAT compensation, which compensates for the PTAT effect brought in by the resistor array and optimizes the temperature coefficient. On the whole, the gate-bulk connection improves the operation headroom and mitigates excessive PTAT effects due to the resistor array. It makes compensation of the temperature coefficient easier.

4. Results and Discussions

Realized using TSMC 40 nm CMOS technology, the proposed V-I Converter circuit operates at a supply voltage of 0.45 V.
The stability analysis of the OTAo is first carried out. Its Bode plot at the TT process corner is shown in Figure 15. The DC open-loop gain is 64.79 dB, the phase margin (PM) is 80.07°, the bandwidth (BW) is 25.1 Hz, and the unity gain bandwidth (UGB) is 48.13 kHz. The stability analysis of OTAo, considering TT, SS, and FF process corners and fluctuations in supply voltage, is summarized in Table 2. It can be observed that the circuit sustains the function regardless of the PVT variation.
For the closed-loop configuration with the capacitive load capacitor C3 = 10 pF, the closed-loop gain (Figure 16) is −5.92 mdB, whereas the closed-loop bandwidth is 34.45 kHz. This indicates that the gain of the entire closed-loop system is about 1, achieving an output voltage equal to the input voltage.
The input DC voltage of the design is in the range of 0.1–0.3 V, and the programmable binary-weighted output currents at T = 300 K, VDD = 0.45 V and the TT process corner are shown in Figure 17. The minimum output current is 260 nA, and the maximum output current is 5.44 μA.
Monte-Carlo simulations have bene used to evaluate the accuracy of the output currents under process variations and mismatch, which are presented in Figure 18. These Monte-Carlo simulations were performed at VDD = 0.45 V and the input DC voltage VIN = VDD/2 = 0.225 V.
The results are summarized in Table 3, showing the mean and the standard deviation of seven different output current levels, as well as the sensitivity of the respective output currents. It has been confirmed that the variation is around a few percentage points, which is acceptable in the context of process variation. Due to the programmable feature in this design, the variation can be compensated for by tuning in applications that require higher precision.
For each of the seven sets of output currents, their temperature coefficients at three different process corners are shown in Figure 19, where the temperature range is −20–80 °C.
The simulation results indicate that the T.C. ranges from 13.80 ppm/°C to 54.68 ppm/°C at a 0.45 V supply voltage and TT process corner. Considering TT, SS, and FF process corners, the T.C. ranges from 9.43 ppm/°C to 78.78 ppm/°C at 0.45 V supply voltage. When the voltage varies by ±5%, the T.C. ranges from 12.60 ppm/°C to 62.11 ppm/°C at the TT corner. The maximum and minimum values of T.C. are shown in Table 4. It can be observed that the variation in T.C. maintains reasonable values regardless of supply voltages and different corner variations.
In order to observe the change in T.C. under process mismatch and variations in statistical approach, seven sets of Monte-Carlo simulations, with each comprising 100 random sample points, are illustrated in Figure 20. These Monte-Carlo simulations are performed at VDD = 0.45 V, and the input DC voltage VIN = VDD/2 = 0.225 V.
The results show that the mean value of the temperature constant is less than 52 ppm/°C, with a standard deviation of less than 13 ppm/°C. The obtained statistical performance parameters are listed in Table 5.
For the benefits of using gate-bulk connections in level shifters, a comparison of the temperature coefficients of the output currents using gate-bulk connection and source-bulk connection is carried out at a supply voltage of 0.45 V and the TT process corner. This comparison is shown in Figure 21. The use of gate-bulk connection exhibits smaller and more stable temperature coefficients. Thus, the use of gate-bulk connections in level shifters helps optimize the temperature coefficient of the output current.
To evaluate the PSRR, the resistive test load is connected in parallel with C4 = 100 pF in Figure 6. From Figure 22, we see that the PSRR at low frequency is 44.96 dB.
The CMRR of this circuit is shown in Figure 23. From Figure 23, we see that the CMRR at low frequency is 47.44 dB.
Figure 24 illustrates the input-referred noise spectrum. The input-referred noise is 4.93 µV/sqrt(Hz) at an input signal frequency of 1 kHz.
Figure 25 illustrates the relationship between THD and the peak-to-peak value of the input signal for different input frequencies. In this evaluation, the input signal has a DC quiescent bias voltage of 0.225 V, and the V-I Converter is powered at 0.45 V supply.
With THD = 1%, i.e., −40 dB as an upper limit, the input peak-to-peak value Vpp can reach a maximum of 0.36 V when the input frequency is 1 kHz. When Vpp is 0.225 V, the maximum input frequency can reach 2 kHz.
Table 6 shows a comparison in terms of performance with the previously reported designs. The figure of merit (FOM) is introduced to evaluate the quality of the work on a comparative basis. FOM is given by the following equation [28]:
F O M = P w × I n p u t   R e f e r r e d   N o i s e B a n d w i d t h μ W μ V / H z / H z
where Pw is the power consumption of the system. The smaller the FOM, the better the overall performance of the circuit.
Referring to Table 6, we see that the conventional FOM does not account for temperature stability—a critical metric for precision analog circuits. The proposed circuit has demonstrated several key advantages for very low-voltage applications. First, this design achieves a temperature coefficient of 54.68 ppm/°C, which is 2× better than in [7] (113 ppm/°C) and 5× better than in [29] (276 ppm/°C). This ensures stable operation across a wide temperature range (−20 °C to 80 °C), making it suitable for precision applications in the context of temperature variation. Additionally, the ability to program output currents enhances its flexibility, enabling the circuit to be adapted to diverse scenarios, from biomedical sensors to energy harvesting systems. With a power consumption of only 0.36–2.76 μW, the circuit is ideal for battery-powered or energy-constrained applications, such as wearable devices and IoT nodes.
The proposed circuit also achieves a CMRR of 47.35 dB and a PSRR of 45.58 dB, which are comparable to those in the representative works. To optimize the trade-off between input-referred noise and temperature stability, a gate-bulk connection in the level shifter, which replaces the conventional source-bulk connection, is suggested. Although the circuit operates in the subthreshold region with Q-factor frequency compensation for stabilizing multiple gain stages in exchange for reduced bandwidth (34.45 kHz), the key objectives for attaining low-power consumption as well as the low temperature coefficient of the output currents have been confirmed. Future work can explore advanced compensation techniques to further improve bandwidth without compromising these critical advantages.

5. Conclusions

This paper describes a V-I Converter embedded with a three-stage OTA, which is based on a modified conventional structure. The circuit is designed using the TSMC 40 nm process and functions at a supply voltage of 0.45 V, enabling operation in the subthreshold region. The circuit has a programmable resistor array for a wide range of output currents when compared to previous designs, and guarantees a low temperature coefficient when pushing for the precision requirement. The low temperature coefficient is a critical parameter for very low-voltage cells. In addition, it has achieved lower power consumption and reasonable PSRR and CMRR. Therefore, the design can be adapted to a variety of application scenarios, and is useful for low-voltage, low-power analog signal processing and sensor signal processing applications. Compared to the previously reported designs, this design has lower bandwidth, which is due to the complicated frequency compensation allowed by its three-stage structure. This results in a restricted operating frequency range, leading to one of the limitations of the design. To this end, the design of the V-I Converter with low temperate coefficient awareness gives the extra benefit of larger operation headroom in the context of temperature variation.

Author Contributions

Conceptualization, H.C. and P.K.C.; validation: H.C. and P.K.C.; writing—original draft preparation: H.C.; writing—review and editing: P.K.C. All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

Data are contained within the article.

Conflicts of Interest

The authors declare no conflicts of interest.

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Figure 1. Conventional V-I structures: (a) Using NMOS as the driving transistor; (b) using PMOS as the driving transistor.
Figure 1. Conventional V-I structures: (a) Using NMOS as the driving transistor; (b) using PMOS as the driving transistor.
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Figure 2. FBVA [7].
Figure 2. FBVA [7].
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Figure 3. V-I Converter with nested feedback loops [14].
Figure 3. V-I Converter with nested feedback loops [14].
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Figure 4. Bulk-driven transconductor.
Figure 4. Bulk-driven transconductor.
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Figure 5. Low-voltage linear V-I conversion unit [17].
Figure 5. Low-voltage linear V-I conversion unit [17].
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Figure 6. Topology of proposed circuit architecture.
Figure 6. Topology of proposed circuit architecture.
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Figure 7. PR.
Figure 7. PR.
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Figure 8. Cross-section of the PR.
Figure 8. Cross-section of the PR.
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Figure 9. The level shifter.
Figure 9. The level shifter.
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Figure 10. (a) The design of the OTAo with resistor array as the passive load in the output stage; (b) the bias circuit.
Figure 10. (a) The design of the OTAo with resistor array as the passive load in the output stage; (b) the bias circuit.
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Figure 11. System block of OTAo.
Figure 11. System block of OTAo.
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Figure 12. Resistor array implementation.
Figure 12. Resistor array implementation.
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Figure 13. (a) VO1 versus T; (b) VO2 versus T.
Figure 13. (a) VO1 versus T; (b) VO2 versus T.
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Figure 14. The plot of the variation of |VTH| with temperature with different bulk connections.
Figure 14. The plot of the variation of |VTH| with temperature with different bulk connections.
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Figure 15. Bode plot of OTAo at TT process corner.
Figure 15. Bode plot of OTAo at TT process corner.
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Figure 16. Closed-loop gain against frequency.
Figure 16. Closed-loop gain against frequency.
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Figure 17. Output current versus input voltage.
Figure 17. Output current versus input voltage.
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Figure 18. Monte-Carlo simulation result of (a) output current 1, (b) output current 2, (c) output current 3, (d) output current 4, (e) output current 5, (f) output current 6, and (g) output current 7.
Figure 18. Monte-Carlo simulation result of (a) output current 1, (b) output current 2, (c) output current 3, (d) output current 4, (e) output current 5, (f) output current 6, and (g) output current 7.
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Figure 19. T.C. in PVT simulation of (a) output current 1, (b) output current 2, (c) output current 3, (d) output current 4, (e) output current 5, (f) output current 6, and (g) output current 7.
Figure 19. T.C. in PVT simulation of (a) output current 1, (b) output current 2, (c) output current 3, (d) output current 4, (e) output current 5, (f) output current 6, and (g) output current 7.
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Figure 20. T.C. in Monte-Carlo simulation of (a) output current 1, (b) output current 2, (c) output current 3, (d) output current 4, (e) output current 5, (f) output current 6 and (g) output current 7.
Figure 20. T.C. in Monte-Carlo simulation of (a) output current 1, (b) output current 2, (c) output current 3, (d) output current 4, (e) output current 5, (f) output current 6 and (g) output current 7.
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Figure 21. Comparison of T.C. of two different bulk connections.
Figure 21. Comparison of T.C. of two different bulk connections.
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Figure 22. The plot of PSRR against frequency.
Figure 22. The plot of PSRR against frequency.
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Figure 23. The plot of CMRR against frequency.
Figure 23. The plot of CMRR against frequency.
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Figure 24. The input-referred noise spectrum.
Figure 24. The input-referred noise spectrum.
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Figure 25. THD.
Figure 25. THD.
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Table 1. Types and sizes of devices of proposed V-I Converter.
Table 1. Types and sizes of devices of proposed V-I Converter.
DeviceTypeSize (W/L)DeviceTypeSize (W/L)
MB1pch_lvt10 μm/1 μmM9pch_lvt840 μm/10 μm
MB2pch_lvt2 μm/1 μmRB1rppolywo4 MΩ
MB3pch_lvt50.8 μm/20 μmRB3rppolywo4.5 MΩ
MB4,S1pch_lvt50 μm/20 μmR1R4pch_lvt600 nm/110 nm
MB5,B6nch_lvt200 nm/6 μmRarray1arppoly7.25 kΩ
MB13nch120 nm/1 μmRarray2arppoly14.5 kΩ
MB14nch5 μm/1 μmRarray4arppoly24.5 kΩ
MB15,B16pch_lvt28 μm/1 μmRarray1brppolywo89 kΩ
MB17nch_lvt2.5 μm/1 μmRarray2brppolywo178 kΩ
MB18nch_lvt12 μm/1 μmRarray4brppolywo360.5 kΩ
MS2pch_lvt19 μm/200 nmCB1cap10 pF
M0nch_lvt30 μm/1 μmCB2cap10 pF
M1,2nch_lvt50 μm/1 μmCB5,B6cap10 pF
M3,4pch_lvt8 μm/1 μmC1cap1 pF
M5,8pch_lvt70 μm/200 nmC2cap5 pF
M6,7nch_lvt6 μm/1 μmC3cap10 pF
Table 2. Stability of OTAo in PVT simulation.
Table 2. Stability of OTAo in PVT simulation.
VDD (V)Process CornerDC Gain (dB)PM (°)BW (Hz)UGB (kHz)
0.4275TT 166.682.2919.9565.45
SS 267.7579.0613.9451.58
FF 365.1285.5230.9686.37
0.45TT67.9779.1217.6970.04
SS69.275.3412.2355.13
FF66.5382.7627.4393.07
0.4725TT68.9475.3916.4274.99
SS70.271.0811.2958.84
FF67.4979.5525.45100.1
1 Typical-Typical corner, representing nominal N transistors and nominal P transistors. 2 Slow-Slow corner, representing slow N transistors and slow P transistors. 3 Fast-Fast corner, representing fast N transistors and fast P transistors.
Table 3. Output currents in Monte-Carlo simulation.
Table 3. Output currents in Monte-Carlo simulation.
1234567
μ (μA)2.3351.173.5030.5862.921.7554.087
σ (nA)107.954.09162.127.5135.581.53189.4
Sensitivity of Output currents [(σ/μ)%]4.624.624.634.694.644.654.63
Table 4. T.C. summary.
Table 4. T.C. summary.
VDD(V)0.42750.450.4725Overall
T.C.
(ppm/°C)
Min.Max.Min.Max.Min.Max.Min.Max.
TT 113.5653.8313.8054.6812.6062.1112.6062.11
SS 236.7279.4834.9778.7835.8881.8534.9781.85
FF 39.3364.959.4365.398.8868.038.8868.03
Min.9.339.438.88NA 4
Max.79.4878.7881.85NA
1 Typical-Typical corner, representing nominal N transistors and nominal P transistors. 2 Slow-Slow corner, representing slow N transistors and slow P transistors. 3 Fast-Fast corner, representing fast N transistors and fast P transistors. 4 NA means Not-Applicable.
Table 5. T.C. in Monte-Carlo simulation.
Table 5. T.C. in Monte-Carlo simulation.
1234567
μ (ppm/°C)50.5449.9251.1030.0846.8143.5848.30
σ (ppm/°C)12.7412.9612.368.3311.6811.4611.69
Sensitivity of T.C. [(σ/μ)%]25.2025.9624.1927.6924.9526.3024.20
Table 6. Simulated performance comparison with previously reported works.
Table 6. Simulated performance comparison with previously reported works.
2001
[29]
2007
[14]
2013
[7]
2019
[30]
2020
[17]
This Work
Technology (μm)NA 10.50.180.180.130.04
Supply voltage (V)+1/−2±1.51.20.3±0.20.45
Input range (V)NA0–30–1.10–0.3−0.1–0.10.1–0.3
Temperature range (°C)0–70NA−40–120NANA−20–80
T.C. (ppm/°C)276NA113NANA54.68
Power consumption (μW)NA3000850.01–0.10.360.36–2.76
BW (Hz)NA90 M14.1 M50–3341.1 M34.45 k
PSRR (dB)46.235/4347.850.25245.58
CMRR (dB)NA62NA54.97047.35
Input referred noise [µV/sqrt(Hz)]NA1.70.261.330.994.93
THD (dB@Vpp@kHz)NA−60@6@100−44.2@1@100−46@0.1@0.1−41.61@0.1@10−56.66@0.1@1
FOM {µW·[µV/sqrt(Hz)]/Hz}NA5.67 × 10−71.56 × 10−63.98 × 10−43.24 × 10−75.15 × 10−5
1 NA means Not-Applicable.
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Chen, H.; Chan, P.K. A Low-Voltage Low-Power Voltage-to-Current Converter with Low Temperature Coefficient Design Awareness. Sensors 2025, 25, 1204. https://doi.org/10.3390/s25041204

AMA Style

Chen H, Chan PK. A Low-Voltage Low-Power Voltage-to-Current Converter with Low Temperature Coefficient Design Awareness. Sensors. 2025; 25(4):1204. https://doi.org/10.3390/s25041204

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Chen, Haoze, and Pak Kwong Chan. 2025. "A Low-Voltage Low-Power Voltage-to-Current Converter with Low Temperature Coefficient Design Awareness" Sensors 25, no. 4: 1204. https://doi.org/10.3390/s25041204

APA Style

Chen, H., & Chan, P. K. (2025). A Low-Voltage Low-Power Voltage-to-Current Converter with Low Temperature Coefficient Design Awareness. Sensors, 25(4), 1204. https://doi.org/10.3390/s25041204

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