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Advanced Interface Circuits for Sensor Systems (Volume II)

A special issue of Sensors (ISSN 1424-8220). This special issue belongs to the section "Electronic Sensors".

Deadline for manuscript submissions: 30 November 2024 | Viewed by 6265

Special Issue Editors


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Guest Editor
School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore, Singapore
Interests: sensor interface ICs; smart sensor systems; low-energy low-noise circuit design; sensor power management ICs; PVT-insensitive circuits and systems
Special Issues, Collections and Topics in MDPI journals

E-Mail Website
Guest Editor
School of Mechanical and Aerospace Engineering, Nanyang Technological University, Singapore, Singapore
Interests: MEMS sensors; MOEMS sensors; CMOS-MEMS integration; sensor reliability and long term performance; sensor design for manufacturability
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Sensors are widely used in healthcare, automobiles, consumer electronics, industrial applications, and so forth. These industries expect high-quality and intelligent sensor circuits. In an era of digital technology, digital-aware or software-aware sensor circuits are a major design agenda. With the combination of artificial intelligence (AI) and the Internet-of-Things (IoT) as one of the driving forces, this has posed further design criteria and constraints to the interface circuits that aim to enhance the detection capability through the assistance of AI. It turns out that the interface circuits, which may be coupled with intelligent peripheral support circuits, can provide advanced features to meet high-performance-aware specifications or high-adaptability, etc., and, therefore, realize smart functions through smart program control. These design concerns impose design challenges and cause a paradigm shift in the design approach to designers or researchers in this emerging field. This Special Issue will publish papers that explore the potential solutions to tackle these issues. Potential topics include but are not limited to the following:

  • High-performance interface circuits
  • AI–IoT sensor circuit design and techniques
  • Smart power management circuits for sensors
  • Sensor circuits with configurable architectures
  • Intelligent peripheral circuits for sensor circuits
  • Software for sensor circuits
  • Digital-assisted sensor circuits
  • Data communication for sensor circuits

For your reference, you may refer to publications in Volume I of this Special Issue series.

Dr. Pak Kwong Chan
Dr. Holden King-Ho Li
Guest Editors

Manuscript Submission Information

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Keywords

  • readout circuits
  • interface circuit techniques
  • AI-IoT
  • power management
  • system architectures
  • sensor peripheral circuits
  • data communication
  • digital-assisted design
  • software-assisted design

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Published Papers (6 papers)

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Research

19 pages, 7546 KiB  
Article
Ultra-Wideband Common-Mode Rejection Structure with Autonomous Phase Balancing for Ultra-High-Speed Digital Transmission
by Byung-Cheol Min, Jeong-Sik Choi, Hyun-Chul Choi and Kang-Wook Kim
Sensors 2024, 24(19), 6180; https://doi.org/10.3390/s24196180 - 24 Sep 2024
Viewed by 403
Abstract
For ultra-high-speed digital transmission, required by 5G/6G communications, ultra-wideband common-mode rejection (CMR) structures with autonomous phase-balancing capability are proposed. Common-mode noise, caused by phase and amplitude unbalances, is one of the most undesired disturbances affecting modern digital circuits. According to the circuit design [...] Read more.
For ultra-high-speed digital transmission, required by 5G/6G communications, ultra-wideband common-mode rejection (CMR) structures with autonomous phase-balancing capability are proposed. Common-mode noise, caused by phase and amplitude unbalances, is one of the most undesired disturbances affecting modern digital circuits. According to the circuit design guides with a typically used differential line (DL) for high-speed digital transmission, common-mode rejection is achieved using CMR filters, and the unbalanced phase, caused by a length difference between the two signal lines of a DL, is compensated by inserting an additional delay line. However, due to nonlinear phase interactions between the two DLs and unbalanced electromagnetic (EM) interferences, the conventional compensation method is frequency-limited at around 10 GHz. To significantly enhance the common-mode rejection level and extend the phase recovery bandwidth, the proposed CMR structure utilizes a planar balanced line (BL), such as a coplanar stripline (CPS) or a parallel stripline (PSL), along with additional conductor strips arranged laterally near the BL. To demonstrate the performance of the proposed BL-based CMR structures, various types of CMR structures are fabricated, and the measurement results are compared with the 3D EM simulation results. As a result, it is proven that the proposed BL-based CMR structures have the capability to reject the common-mode noise with suppression levels of more than 10 dB and to simultaneously recover the phase balance from near DC to over 40 GHz. Full article
(This article belongs to the Special Issue Advanced Interface Circuits for Sensor Systems (Volume II))
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21 pages, 7596 KiB  
Article
A High-Resolution Discrete-Time Second-Order ΣΔ ADC with Improved Tolerance to KT/C Noise Using Low Oversampling Ratio
by Kyung-Chan An, Neelakantan Narasimman and Tony Tae-Hyoung Kim
Sensors 2024, 24(17), 5755; https://doi.org/10.3390/s24175755 - 4 Sep 2024
Viewed by 726
Abstract
This work presents a novel ΣΔ analog-to-digital converter (ADC) architecture for a high-resolution sensor interface. The concept is to reduce the effect of kT/C noise generated by the loop filter by placing the gain stage in front of the loop filter. The proposed [...] Read more.
This work presents a novel ΣΔ analog-to-digital converter (ADC) architecture for a high-resolution sensor interface. The concept is to reduce the effect of kT/C noise generated by the loop filter by placing the gain stage in front of the loop filter. The proposed architecture effectively reduces the kT/C noise power from the loop filter by as much as the squared gain of the added gain stage. The gain stage greatly relaxes the loop filter’s sampling capacitor requirements. The target resolution is 20 bit. The sampling frequency is 512 kHz, and the oversampling ratio (OSR) is only 256 for a target resolution. Therefore, the proposed ΔΣ ADC structure allows for high-resolution ADC design in an environment with a limited OSR. The proposed ADC designed in 65 nm CMOS technology operates at supply voltages of 1.2 V and achieves a peak signal-to-noise ratio (SNR) and Schreier Figure of Merit (FoMs) of 117.7 dB and 180.4 dB, respectively. Full article
(This article belongs to the Special Issue Advanced Interface Circuits for Sensor Systems (Volume II))
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14 pages, 2451 KiB  
Article
Hardware Acceleration of Digital Pulse Shape Analysis Using FPGAs
by César González, Mariano Ruiz, Antonio Carpeño, Alejandro Piñas, Daniel Cano-Ott, Julio Plaza, Trino Martinez and David Villamarin
Sensors 2024, 24(9), 2724; https://doi.org/10.3390/s24092724 - 25 Apr 2024
Viewed by 1071
Abstract
The BC501A sensor is a liquid scintillator frequently used in nuclear physics for detecting fast neutrons. This paper describes a hardware implementation of digital pulse shape analysis (DPSA) for real-time analysis. DPSA is an algorithm that extracts the physically relevant parameters from the [...] Read more.
The BC501A sensor is a liquid scintillator frequently used in nuclear physics for detecting fast neutrons. This paper describes a hardware implementation of digital pulse shape analysis (DPSA) for real-time analysis. DPSA is an algorithm that extracts the physically relevant parameters from the detected BC501A signals. The hardware solution is implemented in a MicroTCA system that provides the physical, mechanical, electrical, and cooling support for an AMC board (NAMC-ZYNQ-FMC) with a Xilinx ZYNQ Ultrascale-MP SoC. The Xilinx FPGA programmable logic implements a JESD204B interface to high-speed ADCs. The physical and datalink JESD204B layers are implemented using hardware description language (HDL), while the Xilinx high-level synthesis language (HLS) is used for the transport and application layers. The DPSA algorithm is a JESD204B application layer that includes a FIR filter and a constant fraction discriminator (CFD) function, a baseline calculation function, a peak detection function, and an energy calculation function. This architecture achieves an analysis mean time of less than 100 µs per signal with an FPGA resource utilization of about 50% of its most used resources. This paper presents a high-performance DPSA embedded system that interfaces with a 1 GS/s ADC and performs accurate calculations with relatively low latency. Full article
(This article belongs to the Special Issue Advanced Interface Circuits for Sensor Systems (Volume II))
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24 pages, 4805 KiB  
Article
Efficient and Accurate Analog Voltage Measurement Using a Direct Sensor-to-Digital Port Interface for Microcontrollers and Field-Programmable Gate Arrays
by Marco Grossi
Sensors 2024, 24(3), 873; https://doi.org/10.3390/s24030873 - 29 Jan 2024
Cited by 1 | Viewed by 1236
Abstract
Portable sensor systems are usually based on microcontrollers and/or Field-Programmable Gate Arrays (FPGAs) that are interfaced with sensors by means of an Analog-to-Digital converter (ADC), either integrated in the computing device or external. An alternative solution is based on the direct connection of [...] Read more.
Portable sensor systems are usually based on microcontrollers and/or Field-Programmable Gate Arrays (FPGAs) that are interfaced with sensors by means of an Analog-to-Digital converter (ADC), either integrated in the computing device or external. An alternative solution is based on the direct connection of the sensors to the digital input port of the microcontroller or FPGA. This solution is particularly interesting in the case of devices not integrating an internal ADC or featuring a small number of ADC channels. In this paper, a technique is presented to directly interface sensors with analog voltage output to the digital input port of a microcontroller or FPGA. The proposed method requires only a few passive components and is based on the measurements of the duty cycle of a digital square-wave signal. This technique was investigated by means of circuit simulations using LTSpice and was implemented in a commercial low-cost FPGA device (Gowin GW1NR-9). The duty cycle of the square-wave signal features a good linear correlation with the analog voltage to be measured. Thus, a look-up table to map the analog voltage values to the measured duty cycle is not required with benefits in terms of memory occupation. The experimental results on the FPGA device have shown that the analog voltage can be measured with a maximum accuracy of 1.09 mV and a sampling rate of 9.75 Hz. The sampling rate can be increased to 31.35 Hz and 128.31 Hz with an accuracy of 1.61 mV and 2.68 mV, respectively. Full article
(This article belongs to the Special Issue Advanced Interface Circuits for Sensor Systems (Volume II))
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13 pages, 2056 KiB  
Article
Two Proposals of a Simple Analog Conditioning Circuit for Remote Resistive Sensors with a Three-Wire Connection
by Ferran Reverter
Sensors 2024, 24(2), 422; https://doi.org/10.3390/s24020422 - 10 Jan 2024
Cited by 4 | Viewed by 908
Abstract
This article proposes and experimentally characterizes two implementations of a novel front-end circuit for three-wire connected resistive sensors with a wire-resistance compensation. The first implementation relies on two twin diodes, whereas the second on a switch; in both cases, those devices are non-remote [...] Read more.
This article proposes and experimentally characterizes two implementations of a novel front-end circuit for three-wire connected resistive sensors with a wire-resistance compensation. The first implementation relies on two twin diodes, whereas the second on a switch; in both cases, those devices are non-remote (i.e., they are placed at the circuit end). The two circuit proposals have a square-wave input excitation so that a constant current with the two polarities is alternatively generated. Then, depending on that polarity, the current goes through either the sensor and the wire parasitic resistances or just the parasitic resistances. This generates a square-wave bipolar output signal whose average value, which is obtained by a low-pass filter, is proportional to the sensor resistance and only depends on the mismatch between two of the three wire resistances involved. Experimental tests applied to resistances related to a Pt100 thermal sensor show a remarkable linearity. For example, the switch-based front-end circuit offers a non-linearity error lower than 0.01% full-scale span, and this is practically insensitive to both the presence and the mismatch between the wire resistances. Full article
(This article belongs to the Special Issue Advanced Interface Circuits for Sensor Systems (Volume II))
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20 pages, 8551 KiB  
Article
Design of a 0.5 V Chopper-Stabilized Differential Difference Amplifier for Analog Signal Processing Applications
by Xinlan Fan, Feifan Gao and Pak Kwong Chan
Sensors 2023, 23(24), 9808; https://doi.org/10.3390/s23249808 - 13 Dec 2023
Viewed by 1292
Abstract
This paper presents a low-voltage low-power chopper-stabilized differential difference amplifier (DDA) realized using 40 nm CMOS technology. Operating with a supply voltage of 0.5 V, a three-stage DDA has been employed to achieve an open-loop gain of 89 dB, while consuming just 0.74 [...] Read more.
This paper presents a low-voltage low-power chopper-stabilized differential difference amplifier (DDA) realized using 40 nm CMOS technology. Operating with a supply voltage of 0.5 V, a three-stage DDA has been employed to achieve an open-loop gain of 89 dB, while consuming just 0.74 μW of power. The proposed DDA incorporates feed-forward frequency compensation and a Type II compensator to achieve pole-zero cancellation and damping factor control. The DDA has a unity-gain bandwidth (UGB) of 170 kHz, a phase margin (PM) of 63.98°, and a common-mode rejection ratio (CMRR) of up to 100 dB. This circuit can effectively drive a 50 pF capacitor in parallel with a 300 kΩ resistor. The use of the chopper stabilization technique effectively mitigates the offset and 1/f noise. The chopping frequency of the chopper modulator is 5 kHz. The input noise is 245 nV/sqrt (Hz) at 1 kHz, and the input-referred offset under Monte Carlo cases is only 0.26 mV. Such a low-voltage chopper-stabilized DDA will be very useful for analog signal processing applications. Compared to the reported chopper DDA counterparts, the proposed DDA is regarded as that with one of the lowest supply voltages. The proposed DDA has demonstrated its effectiveness in tradeoff design when dealing with multiple parameters pertaining to power consumption, noise, and bandwidth. Full article
(This article belongs to the Special Issue Advanced Interface Circuits for Sensor Systems (Volume II))
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