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Micromachines
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Flash Memory Devices
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Flash Memory Devices

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "E：Engineering and Technology".

Deadline for manuscript submissions: closed (31 May 2021) | Viewed by 32320

Printed Edition Available!
A printed edition of this Special Issue is available here.

Special Issue Editors

Dr. Cristian Zambelli

E-Mail Website
Guest Editor
Dipartimento di Ingegneria, Università di Ferrara, 44121 Ferrara, Italy
Interests: electrical characterization and modeling of non-volatile memories reliability; reliability of solid-state drives
Special Issues, Collections and Topics in MDPI journals
Dr. Rino Micheloni

E-Mail Website
Guest Editor
Flash Signal Processing Labs, Microchip Corp., Vimercate, Italy
Interests: flash memories; non-volatile memories; error correction code

Special Issue Information

Dear Colleagues,

Flash memory devices represented a breakthrough in storage since their inception in the mid ‘80s, and innovation is still ongoing after more than 35 years. The peculiarity of such technology is an inherent flexibility in terms of performance and integration density according to the architecture devised for cells integration. The NOR Flash technology is still the workhorse of many code storage applications in the embedded world, ranging from microcontrollers for automotive environment to IoT smart devices. Their usage is also forecasted to be fundamental in emerging AI edge scenario. Their density ranges from a few Kbytes up to the Gigabit size. On the contrary, when massive data storage is required, NAND Flash memories are necessary to have in a system. You can find NAND Flash in USB, Flash Cards (SD, eMMC), but most of all in Solid-State Drives (SSDs). Since SSDs are extremely demanding in terms of storage capacity, they fueled a new wave of innovation for Flash memories, namely the 3D architecture. Today “3D” means that multiple layers (up to one hundred, as we speak) of memory cells are manufactured within the same piece of silicon, easily reaching a terabit of storage capacity per chip. So far, NOR and NAND Flash architectures have always been based on "floating gate," where the information is stored by injecting electrons in a piece of polysilicon surrounded by oxide. On the contrary, emerging concepts for embedded applications and most of 3D memories are based on "charge trap" cells.

In summary, flash memory devices represent the largest landscape of storage devices and we do expect more and more advancements in the coming years. This will require a lot of innovation in process technology, materials, circuit design, flash management algorithms, Error Correction Code and, finally, system co-design for new applications like AI and security enforcement.

Authors are invited to submit original contributions on the following topics but not limited to:

  • NOR Flash memories for embedded applications (automotive, IoT)
  • Planar and 3D NAND Flash memory architectures with multi-level data storage (MLC, TLC, QLC)
  • Process technology for 3D flash memories
  • Reliability of flash memories
  • Impact of flash memories on Solid State Drives reliability and performance
  • Error Correction Codes and Secondary Correction Algorithms for flash memories
  • Flash memory cell/string characterization (floating gate and charge trapping) and design
  • Testing, characterization, and defects
  • Flash management and flash signal processing in controllers for Big Data storage
  • Flash memories for AI applications at the edge
  • Security (PUF, TRNG) concerns addressable with flash memories

Dr. Cristian Zambelli
Dr. Rino Micheloni
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Flash memories
  • NOR and NAND architectures
  • 3D Flash memories
  • Solid State Drive
  • AI and security with Flash
  • Error Correction Code
  • Flash Management
  • Flash Signal Processing
  • Flash reliability

Published Papers (10 papers)

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Editorial

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3 pages, 175 KiB  
Editorial
Editorial for the Special Issue on Flash Memory Devices
by Cristian Zambelli and Rino Micheloni
Micromachines 2021, 12(12), 1566; https://doi.org/10.3390/mi12121566 - 17 Dec 2021
Viewed by 1942
Abstract
Flash memory devices represented a breakthrough in the storage industry since their inception in the mid-1980s, and innovation is still ongoing after more than 35 years [...] Full article
(This article belongs to the Special Issue Flash Memory Devices)

Research

Jump to: Editorial, Review

11 pages, 2354 KiB  
Article
Temperature Impacts on Endurance and Read Disturbs in Charge-Trap 3D NAND Flash Memories
by Fei Chen, Bo Chen, Hongzhe Lin, Yachen Kong, Xin Liu, Xuepeng Zhan and Jiezhi Chen
Micromachines 2021, 12(10), 1152; https://doi.org/10.3390/mi12101152 - 25 Sep 2021
Cited by 5 | Viewed by 4809
Abstract
Temperature effects should be well considered when designing flash-based memory systems, because they are a fundamental factor that affect both the performance and the reliability of NAND flash memories. In this work, aiming to comprehensively understanding the temperature effects on 3D NAND flash [...] Read more.
Temperature effects should be well considered when designing flash-based memory systems, because they are a fundamental factor that affect both the performance and the reliability of NAND flash memories. In this work, aiming to comprehensively understanding the temperature effects on 3D NAND flash memory, triple-level-cell (TLC) mode charge-trap (CT) 3D NAND flash memory chips were characterized systematically in a wide temperature range (−30~70 °C), by focusing on the raw bit error rate (RBER) degradation during program/erase (P/E) cycling (endurance) and frequent reading (read disturb). It was observed that (1) the program time showed strong dependences on the temperature and P/E cycles, which could be well fitted by the proposed temperature-dependent cycling program time (TCPT) model; (2) RBER could be suppressed at higher temperatures, while its degradation weakly depended on the temperature, indicating that high-temperature operations would not accelerate the memory cells’ degradation; (3) read disturbs were much more serious at low temperatures, while it helped to recover a part of RBER at high temperatures. Full article
(This article belongs to the Special Issue Flash Memory Devices)
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15 pages, 9497 KiB  
Article
Understanding the Origin of Metal Gate Work Function Shift and Its Impact on Erase Performance in 3D NAND Flash Memories
by Sivaramakrishnan Ramesh, Arjun Ajaykumar, Lars-Åke Ragnarsson, Laurent Breuil, Gabriel Khalil El Hajjam, Ben Kaczer, Attilio Belmonte, Laura Nyns, Jean-Philippe Soulié, Geert Van den bosch and Maarten Rosmeulen
Micromachines 2021, 12(9), 1084; https://doi.org/10.3390/mi12091084 - 08 Sep 2021
Cited by 2 | Viewed by 3760
Abstract
We studied the metal gate work function of different metal electrode and high-k dielectric combinations by monitoring the flat band voltage shift with dielectric thicknesses using capacitance–voltage measurements. We investigated the impact of different thermal treatments on the work function and linked any [...] Read more.
We studied the metal gate work function of different metal electrode and high-k dielectric combinations by monitoring the flat band voltage shift with dielectric thicknesses using capacitance–voltage measurements. We investigated the impact of different thermal treatments on the work function and linked any shift in the work function, leading to an effective work function, to the dipole formation at the metal/high-k and/or high-k/SiO2 interface. We corroborated the findings with the erase performance of metal/high-k/ONO/Si (MHONOS) capacitors that are identical to the gate stack in three-dimensional (3D) NAND flash. We demonstrate that though the work function extraction is convoluted by the dipole formation, the erase performance is not significantly affected by it. Full article
(This article belongs to the Special Issue Flash Memory Devices)
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12 pages, 787 KiB  
Article
Artificial Neural Network Assisted Error Correction for MLC NAND Flash Memory
by Ruiquan He, Haihua Hu, Chunru Xiong and Guojun Han
Micromachines 2021, 12(8), 879; https://doi.org/10.3390/mi12080879 - 27 Jul 2021
Cited by 4 | Viewed by 2490
Abstract
The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise [...] Read more.
The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory. Full article
(This article belongs to the Special Issue Flash Memory Devices)
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17 pages, 4061 KiB  
Article
Observation and Optimization on Garbage Collection of Flash Memories: The View in Performance Cliff
by Yajuan Du, Wei Liu, Yuan Gao and Rachata Ausavarungnirun
Micromachines 2021, 12(7), 846; https://doi.org/10.3390/mi12070846 - 20 Jul 2021
Cited by 2 | Viewed by 1922
Abstract
The recent development of 3D flash memories has promoted the widespread application of SSDs in modern storage systems by providing large storage capacity and low cost. Garbage collection (GC) as a time-consuming but necessary operation in flash memories largely affects the performance. In [...] Read more.
The recent development of 3D flash memories has promoted the widespread application of SSDs in modern storage systems by providing large storage capacity and low cost. Garbage collection (GC) as a time-consuming but necessary operation in flash memories largely affects the performance. In this paper, we perform a comprehensive experimental study on how garbage collection impacts the performance of flash-based SSDs, in the view of performance cliff that closely relates to Quality of Service (QoS). According to the study results using real-world workloads, we first observe that GC occasionally causes response time spikes, which we call the performance cliff problem. Then, we find that 3D SSDs exacerbate the situation by inducing a much higher number of page migrations during GC. To relieve the performance cliff problem, we propose PreGC to assist normal GC. The key idea is to distribute the page migrations into the period before normal GC, thus leading to a reduction in page migrations during the GC period. Comprehensive experiments with real-world workloads have been performed on the SSDsim simulator. Experimental results show that PreGC can efficiently relieve the performance cliff by reducing the tail latency from the 90th to 99.99th percentiles while inducing a little extra write amplification. Full article
(This article belongs to the Special Issue Flash Memory Devices)
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14 pages, 6702 KiB  
Article
A Scalable Bidimensional Randomization Scheme for TLC 3D NAND Flash Memories
by Michele Favalli, Cristian Zambelli, Alessia Marelli, Rino Micheloni and Piero Olivo
Micromachines 2021, 12(7), 759; https://doi.org/10.3390/mi12070759 - 27 Jun 2021
Cited by 4 | Viewed by 2288
Abstract
Data randomization has been a widely adopted Flash Signal Processing technique for reducing or suppressing errors since the inception of mass storage platforms based on planar NAND Flash technology. However, the paradigm change represented by the 3D memory integration concept has complicated the [...] Read more.
Data randomization has been a widely adopted Flash Signal Processing technique for reducing or suppressing errors since the inception of mass storage platforms based on planar NAND Flash technology. However, the paradigm change represented by the 3D memory integration concept has complicated the randomization task due to the increased dimensions of the memory array, especially along the bitlines. In this work, we propose an easy to implement, cost effective, and fully scalable with memory dimensions, randomization scheme that guarantees optimal randomization along the wordline and the bitline dimensions. At the same time, we guarantee an upper bound on the maximum length of consecutive ones and zeros along the bitline to improve the memory reliability. Our method has been validated on commercial off-the-shelf TLC 3D NAND Flash memory with respect to the Raw Bit Error Rate metric extracted in different memory working conditions. Full article
(This article belongs to the Special Issue Flash Memory Devices)
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21 pages, 2227 KiB  
Article
An SVM-Based NAND Flash Endurance Prediction Method
by Haichun Zhang, Jie Wang, Zhuo Chen, Yuqian Pan, Zhaojun Lu and Zhenglin Liu
Micromachines 2021, 12(7), 746; https://doi.org/10.3390/mi12070746 - 25 Jun 2021
Cited by 6 | Viewed by 2448
Abstract
NAND flash memory is widely used in communications, commercial servers, and cloud storage devices with a series of advantages such as high density, low cost, high speed, anti-magnetic, and anti-vibration. However, the reliability is increasingly getting worse while process improvements and technological advancements [...] Read more.
NAND flash memory is widely used in communications, commercial servers, and cloud storage devices with a series of advantages such as high density, low cost, high speed, anti-magnetic, and anti-vibration. However, the reliability is increasingly getting worse while process improvements and technological advancements have brought higher storage densities to NAND flash memory. The degradation of reliability not only reduces the lifetime of the NAND flash memory but also causes the devices to be replaced prematurely based on the nominal value far below the minimum actual value, resulting in a great waste of lifetime. Using machine learning algorithms to accurately predict endurance levels can optimize wear-leveling strategies and warn bad memory blocks, which is of great significance for effectively extending the lifetime of NAND flash memory devices and avoiding serious losses caused by sudden failures. In this work, a multi-class endurance prediction scheme based on the SVM algorithm is proposed, which can predict the remaining P-E cycle level and the raw bit error level after various P-E cycles. Feature analysis based on endurance data is used to determine the basic elements of the model. Based on the error features, we present a variety of targeted optimization strategies, such as extracting the numerical features closely related to the endurance, and reducing the noise interference of transient faults through short-term repeated operations. Besides a high-parallel flash test platform supporting multiple protocols, a feature preprocessing module is constructed based on the ZYNQ-7030 chip. The pipelined module of SVM decision model can complete a single prediction within 37 us. Full article
(This article belongs to the Special Issue Flash Memory Devices)
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10 pages, 2715 KiB  
Article
Novel Program Scheme of Vertical NAND Flash Memory for Reduction of Z-Interference
by Su-in Yi and Jungsik Kim
Micromachines 2021, 12(5), 584; https://doi.org/10.3390/mi12050584 - 20 May 2021
Cited by 10 | Viewed by 3550
Abstract
Minimizing the variation in threshold voltage (Vt) of programmed cells is required to the extreme level for realizing multi-level-cells; as many as even 5 bits per cell recently. In this work, a recent program scheme to write the cells from [...] Read more.
Minimizing the variation in threshold voltage (Vt) of programmed cells is required to the extreme level for realizing multi-level-cells; as many as even 5 bits per cell recently. In this work, a recent program scheme to write the cells from the top, for instance the 170th layer, to the bottom, the 1st layer, (T-B scheme) in vertical NAND (VNAND) Flash Memory, is investigated to minimize Vt variation by reducing Z-interference. With the aid of Technology Computer Aided Design (TCAD) the Z-Interference for T-B (84 mV) is found to be better than B-T (105 mV). Moreover, under scaled cell dimensions (e.g., Lg: 31→24 nm), the improvement becomes protruding (T-B: 126 mV and B-T: 162 mV), emphasizing the significance of the T-B program scheme for the next generation VNAND products with the higher bit density. Full article
(This article belongs to the Special Issue Flash Memory Devices)
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11 pages, 2549 KiB  
Article
Retention Enhancement in Low Power NOR Flash Array with High-κ–Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide
by Young Suh Song and Byung-Gook Park
Micromachines 2021, 12(3), 328; https://doi.org/10.3390/mi12030328 - 19 Mar 2021
Cited by 4 | Viewed by 3291
Abstract
For improving retention characteristics in the NOR flash array, aluminum oxide (Al2O3, alumina) is utilized and incorporated as a tunneling layer. The proposed tunneling layers consist of SiO2/Al2O3/SiO2, which take advantage [...] Read more.
For improving retention characteristics in the NOR flash array, aluminum oxide (Al2O3, alumina) is utilized and incorporated as a tunneling layer. The proposed tunneling layers consist of SiO2/Al2O3/SiO2, which take advantage of higher permittivity and higher bandgap of Al2O3 compared to SiO2 and silicon nitride (Si3N4). By adopting the proposed tunneling layers in the NOR flash array, the threshold voltage window after 10 years from programming and erasing (P/E) was improved from 0.57 V to 4.57 V. In order to validate our proposed device structure, it is compared to another stacked-engineered structure with SiO2/Si3N4/SiO2 tunneling layers through technology computer-aided design (TCAD) simulation. In addition, to verify that our proposed structure is suitable for NOR flash array, disturbance issues are also carefully investigated. As a result, it has been demonstrated that the proposed structure can be successfully applied in NOR flash memory with significant retention improvement. Consequently, the possibility of utilizing HfO2 as a charge-trapping layer in NOR flash application is opened. Full article
(This article belongs to the Special Issue Flash Memory Devices)
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Review

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14 pages, 2163 KiB  
Review
Random Telegraph Noise in 3D NAND Flash Memories
by Alessandro S. Spinelli, Gerardo Malavena, Andrea L. Lacaita and Christian Monzio Compagnoni
Micromachines 2021, 12(6), 703; https://doi.org/10.3390/mi12060703 - 16 Jun 2021
Cited by 7 | Viewed by 4229
Abstract
In this paper, we review the phenomenology of random telegraph noise (RTN) in 3D NAND Flash arrays. The main features of such arrays resulting from their mainstream integration scheme are first discussed, pointing out the relevant role played by the polycrystalline nature of [...] Read more.
In this paper, we review the phenomenology of random telegraph noise (RTN) in 3D NAND Flash arrays. The main features of such arrays resulting from their mainstream integration scheme are first discussed, pointing out the relevant role played by the polycrystalline nature of the string silicon channels on current transport. Starting from that, experimental data for RTN in 3D arrays are presented and explained via theoretical and simulation models. The attention is drawn, in particular, to the changes in the RTN dependences on the array working conditions that resulted from the transition from planar to 3D architectures. Such changes are explained by considering the impact of highly-defective grain boundaries on percolative current transport in cell channels in combination with the localized nature of the RTN traps. Full article
(This article belongs to the Special Issue Flash Memory Devices)
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