Special Issue "Approximate Computing: Design, Acceleration, Validation and Testing of Circuits, Architectures and Algorithms in Future Systems"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: 30 June 2021.

Special Issue Editor

Dr. Alessandro Savino
Website
Guest Editor
Politecnico di Torino, Corso Duca degli Abruzzi, 24, 10129 Torino, Italy
Interests: approximate computing, reliability assessment, software-based self-test, statistical models

Special Issue Information

Dear Colleagues,

In recent years, the applicability of approximate computing has represented a breakthrough in many scientific areas, making AC a step closer to being one of the mainstream computing approaches in future systems. First, it is becoming more and more difficult to achieve significant performance improvement with the scaling of CMOS technology. Second, modern architectures vary from HPC to embedded systems (e.g., IoT, autonomous driving, etc.), making room for the need for a trade-off between efficiency, in terms of memory and performance resources, and power consumption, and the quality of the final outcomes. In this sense, for several application domains, especially those related to human perception, the approximate results might turn out to be hard to distinguish from perfect results, opening the application of AC for system designers.

Suitable solutions will not be fully realized in a single layer only. Therefore, applying AC in different layers of hardware, architecture, software and algorithms should be investigated. Moreover, while the hidden cost of AC is a reduction of an application’s inherent resiliency to errors, AC has also recently been demonstrated to be effective in safety-critical applications.

This Special Issue on AC will explore exciting, new ideas in the field of approximate computing, covering cross-layer design methodologies bridging the circuit, architecture and algorithm levels. It will also include connections between the AC paradigm and the safety, verification, testing and reliability of digital systems.

Topics for this Special Issue include (but are not limited to):

  • Analog and circuit-level approximation techniques
  • Approximation-induced error modeling and propagation
  • Approximation techniques for emerging processor and memory technologies
  • Architectural support for AC
  • Dependability of approximate circuits and systems
  • Design automation of AC architectures
  • Design of reconfigurable AC architectures
  • Error-resilient near-threshold computing
  • Hardware accelerators for approximation-tolerant application domains
  • Hardware/software co-design of AC systems
  • Language, compiler, and operating system support for approximate architectures
  • Safety and reliability applications of approximate computing
  • Techniques for monitoring and controlling approximation quality
  • Test and fault tolerance of approximate systems
  • Verification of approximate systems

Dr. Alessandro Savino
Guest Editor

Manuscript Submission Information

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Keywords

  • Approximate Computing
  • Reconfigurable Systems
  • Hardware Accelerators
  • Safety-Critical Applications
  • Reliability Assessment
  • Fault Tolerance

Published Papers (7 papers)

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Research

Open AccessArticle
RNS Number Comparator Based on a Modified Diagonal Function
Electronics 2020, 9(11), 1784; https://doi.org/10.3390/electronics9111784 - 27 Oct 2020
Abstract
Number comparison has long been recognized as one of the most fundamental non-modular arithmetic operations to be executed in a non-positional Residue Number System (RNS). In this paper, a new technique for designing comparators of RNS numbers represented in an arbitrary moduli set [...] Read more.
Number comparison has long been recognized as one of the most fundamental non-modular arithmetic operations to be executed in a non-positional Residue Number System (RNS). In this paper, a new technique for designing comparators of RNS numbers represented in an arbitrary moduli set is presented. It is based on a newly introduced modified diagonal function, whose strictly monotonic properties make it possible to replace the cumbersome operations of finding the remainder of the division by a large and awkward number with significantly simpler computations involving only a power of 2 modulus. Comparators of numbers represented in sample RNSs composed of varying numbers of moduli and offering different dynamic ranges, designed using various methods, were synthesized for the 65 nm technology. The experimental results suggest that the new circuits enjoy a delay reduction ranging from over 11% to over 75% compared to the fastest circuits designed using existing methods. Moreover, it is achieved using less hardware, the reduction of which reaches over 41%, and is accompanied by significantly reduced power-consumption, which in several cases exceeds 100%. Therefore, it seems that the presented method leads to the design of the most efficient current hardware comparators of numbers represented using a general RNS moduli set. Full article
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Open AccessFeature PaperArticle
Survey on Approximate Computing and Its Intrinsic Fault Tolerance
Electronics 2020, 9(4), 557; https://doi.org/10.3390/electronics9040557 - 26 Mar 2020
Cited by 3
Abstract
This work is a survey on approximate computing and its impact on fault tolerance, especially for safety-critical applications. It presents a multitude of approximation methodologies, which are typically applied at software, architecture, and circuit level. Those methodologies are discussed and compared on all [...] Read more.
This work is a survey on approximate computing and its impact on fault tolerance, especially for safety-critical applications. It presents a multitude of approximation methodologies, which are typically applied at software, architecture, and circuit level. Those methodologies are discussed and compared on all their possible levels of implementations (some techniques are applied at more than one level). Approximation is also presented as a means to provide fault tolerance and high reliability: Traditional error masking techniques, such as triple modular redundancy, can be approximated and thus have their implementation and execution time costs reduced compared to the state of the art. Full article
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Open AccessArticle
HEAP: A Holistic Error Assessment Framework for Multiple Approximations Using Probabilistic Graphical Models
Electronics 2020, 9(2), 373; https://doi.org/10.3390/electronics9020373 - 22 Feb 2020
Abstract
Approximate computing has been a good paradigm of energy-efficient accelerator design. Accurate and fast error estimation is critical for appropriate approximate techniques selection so that power saving (or performance improvement) can be maximized with acceptable output quality in approximate accelerators. In the paper, [...] Read more.
Approximate computing has been a good paradigm of energy-efficient accelerator design. Accurate and fast error estimation is critical for appropriate approximate techniques selection so that power saving (or performance improvement) can be maximized with acceptable output quality in approximate accelerators. In the paper, we propose HEAP, a Holistic Error assessment framework to characterize multiple Approximate techniques with Probabilistic graphical models (PGM) in a joint way. HEAP maps the problem of evaluating errors induced by different approximate techniques into a PGM issue, including: (1) A heterogeneous Bayesian network is represented by converting an application’s data flow graph, where various approximate options are {precise, approximate} two-state X*-type nodes, while input or operating variables are {precise, approximate, unacceptable} three-state X-type nodes. These two different kinds of nodes are separately used to configure the available approximate techniques and track the corresponding error propagation for guaranteed configurability; (2) node learning is accomplished via an approximate library, which consists of probability mass functions of multiple approximate techniques to fast calculate each node’s Conditional Probability Table by mechanistic modeling or empirical modeling; (3) exact inference provides the probability distribution of output quality at three levels of precise, approximate, and unacceptable. We do a complete case study of 3 × 3 Gaussian kernels with different approximate configurations to verify HEAP. The comprehensive results demonstrate that HEAP is helpful to explore design space for power-efficient approximate accelerators, with just 4.18% accuracy loss and 3.34 × 105 speedup on average over Mentor Carlo simulation. Full article
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Open AccessArticle
FPGA-Based Hardware Matrix Inversion Architecture Using Hybrid Piecewise Polynomial Approximation Systolic Cells
Electronics 2020, 9(1), 182; https://doi.org/10.3390/electronics9010182 - 18 Jan 2020
Cited by 2
Abstract
The hardware of the matrix inversion architecture using QR decomposition with Givens Rotations (GR) and a back substitution (BS) block is required for many signal processing algorithms. However, the hardware of the GR algorithm requires the implementation of complex operations, such as the [...] Read more.
The hardware of the matrix inversion architecture using QR decomposition with Givens Rotations (GR) and a back substitution (BS) block is required for many signal processing algorithms. However, the hardware of the GR algorithm requires the implementation of complex operations, such as the reciprocal square root (RSR), which is typically implemented using LookUp Table (LUT) and COordinate Rotation DIgital Computer (CORDICs), among others, conveying to either high-area consumption or low throughput. This paper introduces an Field-Programmable Gate Array (FPGA)-based full matrix inversion architecture using hybrid piecewise polynomial approximation systolic cells. In the design, a hybrid segmentation technique was incorporated for the implementation of piecewise polynomial systolic cells. This hybrid approach is composed by an external and internal segmentation, where the first is nonuniform and the second is uniform, fitting the curve shape of the complex functions achieving a better signal-quantization-to noise-ratio; furthermore, it improves the time performance and area resources. Experimental results reveal a well-balanced improvement in the design achieving high throughput and, hence, less resource utilization in comparison to state-of-the-art FPGA-based architectures. In our study, the proposed design achieves 7.51 Mega-Matrices per second for performing 4 × 4 matrix operations with a latency of 12 clock cycles; meanwhile, the hardware design requires only 1474 slice registers, 1458 LUTs in an FPGA Virtex-5 XC5VLX220T, and 1474 slice registers and 1378 LUTs when a FPGA Virtex-6 XC6VLX240T is used. Full article
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Open AccessArticle
Using Approximate Computing and Selective Hardening for the Reduction of Overheads in the Design of Radiation-Induced Fault-Tolerant Systems
Electronics 2019, 8(12), 1539; https://doi.org/10.3390/electronics8121539 - 13 Dec 2019
Abstract
Fault mitigation techniques based on pure software, known as software-implemented hardware fault tolerance (SIHFT), are very attractive for use in COTS (commercial off-the-shelf) microprocessors because they do not require physical modification of the system. However, these techniques cause software overheads that may affect [...] Read more.
Fault mitigation techniques based on pure software, known as software-implemented hardware fault tolerance (SIHFT), are very attractive for use in COTS (commercial off-the-shelf) microprocessors because they do not require physical modification of the system. However, these techniques cause software overheads that may affect the efficiency and costs of the overall system. This paper presents a design method of radiation-induced fault-tolerant microprocessor-based systems with lower execution time overheads. For this purpose, approximate computing and selective fault mitigation software-based techniques are used; thus it can be used in COTS devices. The proposal is validated through a case study for the TI MSP430 microcontroller. Results show that the designer can choose among a wide spectrum of design configurations, exploring different trade-offs between reliability, performance, and accuracy of results. Full article
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Open AccessArticle
A High-Speed Division Algorithm for Modular Numbers Based on the Chinese Remainder Theorem with Fractions and Its Hardware Implementation
Electronics 2019, 8(3), 261; https://doi.org/10.3390/electronics8030261 - 27 Feb 2019
Cited by 7
Abstract
In this paper, a new simplified iterative division algorithm for modular numbers that is optimized on the basis of the Chinese remainder theorem (CRT) with fractions is developed. It requires less computational resources than the CRT with integers and mixed radix number systems [...] Read more.
In this paper, a new simplified iterative division algorithm for modular numbers that is optimized on the basis of the Chinese remainder theorem (CRT) with fractions is developed. It requires less computational resources than the CRT with integers and mixed radix number systems (MRNS). The main idea of the algorithm is (a) to transform the residual representation of the dividend and divisor into a weighted fixed-point code and (b) to find the higher power of 2 in the divisor written in a residue number system (RNS). This information is acquired using the CRT with fractions: higher power is defined by the number of zeros standing before the first significant digit. All intermediate calculations of the algorithm involve the operations of right shift and subtraction, which explains its good performance. Due to the abovementioned techniques, the algorithm has higher speed and consumes less computational resources, thereby being more appropriate for the multidigit division of modular numbers than the algorithms described earlier. The new algorithm suggested in this paper has O (log2 Q) iterations, where Q is the quotient. For multidigit numbers, its modular division complexity is Q(N), where N denotes the number of bits in a certain fraction required to restore the number by remainders. Since the number N is written in a weighed system, the subtraction-based comparison runs very fast. Hence, this algorithm might be the best currently available. Full article
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Open AccessArticle
A Novel Multicomponent PSO Algorithm Applied in FDE–AJTF Decomposition
Electronics 2019, 8(1), 51; https://doi.org/10.3390/electronics8010051 - 02 Jan 2019
Cited by 1
Abstract
The echo of maneuvering targets can be expressed as a multicomponent polynomial phase signal (mc-PPS), which should be processed by time frequency analysis methods, while, as a modified maximum likelihood (ML) method, the frequency domain extraction-based adaptive joint time frequency (FDE–AJTF) decomposition method [...] Read more.
The echo of maneuvering targets can be expressed as a multicomponent polynomial phase signal (mc-PPS), which should be processed by time frequency analysis methods, while, as a modified maximum likelihood (ML) method, the frequency domain extraction-based adaptive joint time frequency (FDE–AJTF) decomposition method is an effective tool. However, the key procedure in the FDE–AJTF method is searching for the optimal parameters in the solution space, which is essentially a multidimensional optimization problem with different extremal solutions. To solve the problem, a novel multicomponent particle swarm optimization (mc-PSO) algorithm is presented and applied in the FDE–AJTF decomposition with the new characteristic that can extract several components simultaneously based on the feature of the standard PSO, in which the population is divided into three groups and the neighborhood of the best particle in the optimal group is set as the forbidden area for the suboptimal group, and then two different independent components can be obtained and extracted in one extraction. To analyze its performance, three simulation tests are carried out and compared with a standard PSO, genetic algorithm, and differential evolution algorithm. According to the tests, it is verified that the mc-PSO has the best performance in that the convergence, accuracy, and stability are improved, while its searching times and computation are reduced. Full article
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