From Circuits to Systems: Embedded and FPGA-Based Applications

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 15 July 2026 | Viewed by 1990

Special Issue Editor


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Guest Editor
School of Microelectronics, Xi’an Jiaotong University, Xi’an 710049, China
Interests: neural network accelerator; network protocol offloading; post-quantum cryptography (PQC); reconfigurable computing and VLSI SoC design
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Special Issue Information

Dear Colleagues,

Embedded systems and Field-Programmable Gate Arrays (FPGAs) have long been recognized as powerful platforms for delivering low-latency, energy-efficient, and highly customizable acceleration solutions. Their inherent flexibility, parallelism, and hardware-level optimization have enabled significant advances in traditional domains such as signal processing, industrial control, and communication infrastructure. However, the landscape of computing is rapidly evolving. With the emergence of data-intensive artificial intelligence workloads, large-scale computational tasks, high-speed network processing, and increasingly complex security requirements, new challenges arise in fully exploiting the capabilities of embedded platforms and FPGAs. These developments call for innovative design methodologies, scalable architectures, and domain-specialized accelerators that bridge circuit-level optimization with system-level performance demands.

The aim of this Special Issue, “From Circuits to Systems: Embedded and FPGA-Based Applications”, is to provide a platform for presenting recent advances, design methodologies, architectures, and practical implementations that push the frontier of FPGA-based and embedded-system research. We encourage contributions that demonstrate how emerging technologies such as machine learning, privacy-preserving computation, reconfigurable accelerators, and secure communication protocols can be efficiently produced and deployed on FPGA or embedded platforms.

This Special Issue welcomes original research articles, innovative designs, and comprehensive surveys. Topics of interest include, but are not limited to the following:

  • FPGA-based acceleration for machine learning, deep learning, and data-intensive AI workloads;
  • Hardware architectures for privacy-preserving computation, secure protocols, and cryptographic algorithms;
  • High-performance and low-latency FPGA designs for networking, communication, and edge processing;
  • Reconfigurable computing architectures and heterogeneous SoC/FPGA platforms;
  • Hardware/software co-design methodologies for embedded and FPGA-based systems;
  • Custom domain-specific accelerators and scalable FPGA computing architectures;
  • Real-time signal, image, and video processing on embedded or FPGA platforms;
  • Energy-efficient, low-power, and thermal-aware designs for reconfigurable hardware;
  • Reliability, safety, and security mechanisms in embedded and reconfigurable systems;
  • Embedded and FPGA-based solutions for edge computing, IoT, and autonomous systems;
  • High-speed interconnects, memory architectures, and data movement optimization in FPGA systems;
  • Emerging applications of FPGAs in robotics, smart sensing, biomedical systems, and high-performance computing.

Dr. Chen Yang
Guest Editor

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Keywords

  • FPGA
  • embedded systems
  • edge and IoT systems

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Published Papers (5 papers)

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Research

23 pages, 1210 KB  
Article
Enhancing Single Event-Related Potentials Through Preprocessing and Denoising
by Salah Djelel and Moncef Benkherrat
Electronics 2026, 15(10), 1981; https://doi.org/10.3390/electronics15101981 - 7 May 2026
Abstract
Extracting evoked potentials (EPs) from single trials in electroencephalography (EEG) remains a major challenge due to a characteristically low signal-to-noise ratio (SNR). This paper presents an enhanced denoising framework that combines multiresolution wavelet transform (MWT) with a statistical resampling technique. A key contribution [...] Read more.
Extracting evoked potentials (EPs) from single trials in electroencephalography (EEG) remains a major challenge due to a characteristically low signal-to-noise ratio (SNR). This paper presents an enhanced denoising framework that combines multiresolution wavelet transform (MWT) with a statistical resampling technique. A key contribution is the introduction of an SNR-based preprocessing step that assesses individual trials and discards those with an SNR below 0 dB to prevent heavily corrupted data from degrading the analysis. Unlike traditional methods that rely on Gaussian noise assumptions, our approach utilizes empirical resampling to estimate optimal wavelet coefficient thresholds in a fully data-driven manner. Hard thresholding is subsequently applied to isolate transient neural events from background fluctuations. The method was validated using synthetic signals and real EEG recordings from ten subjects (aged 20–31 years) performing an Eriksen flanker task. Results from simulations demonstrated a significant mean SNR improvement of 13 dB. In real data applications, the error-monitoring components (Ne and Pe) were clearly identified at the single-trial level, with peak latencies observed at approximately 180 ms and 220 ms, respectively. This approach enables reliable single-trial EP analysis without the need for templates or multichannel recordings, offering a robust tool for brain–computer interfaces and clinical diagnostics. Full article
(This article belongs to the Special Issue From Circuits to Systems: Embedded and FPGA-Based Applications)
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22 pages, 911 KB  
Article
STORM: Hardware-Aware Tiny Transformer Co-Design for Low-Power Inertial Human Activity Recognition
by Alessandro Varaldi, Claudio Genta, Alberto Manzone and Marco Vacca
Electronics 2026, 15(9), 1924; https://doi.org/10.3390/electronics15091924 - 1 May 2026
Viewed by 255
Abstract
Human Activity Recognition (HAR) from inertial sensors must run continuously on battery-powered wearables under tight latency, memory, and energy budgets. While tiny Transformers can be effective on inertial time series, end-to-end co-design across quantized inference and heterogeneous low-power platforms remains underexplored. We present [...] Read more.
Human Activity Recognition (HAR) from inertial sensors must run continuously on battery-powered wearables under tight latency, memory, and energy budgets. While tiny Transformers can be effective on inertial time series, end-to-end co-design across quantized inference and heterogeneous low-power platforms remains underexplored. We present STORM (Small Transformer for On-node Recognition of Motion), a deployment-oriented [round-mode=places, round-precision=1]19.7k-parameter 1D Transformer co-designed with X-HEEP, an open-source low-power single-core RISC-V SoC, and a tightly coupled streaming CGRA for nonlinear primitives (e.g., softmax). We build a cross-source 8-class benchmark by harmonizing 3 public datasets under a stringent, deployment-aligned protocol that exposes both cross-subject and cross-source shift. Using 1.280 s windows with 0.640 s stride, the protocol models continuous on-node HAR under cross-dataset generalization. After quantization-aware training and INT8 C inference export, STORM achieves [round-mode=places, round-precision=3]0.799/[round-mode=places, round-precision=3]0.801 accuracy/macro-F1 on this benchmark. Deployed on an FPGA prototype of X-HEEP with the streaming CGRA backend, STORM requires round(6739790/ (100* 1000000)* 1000, 1) ms per inference at 100 MHz, while activity-based power analysis estimates a total inference energy of 632.4 μJ, satisfying the stride-driven real-time constraint. These results support the practical viability of compact attention-based HAR on low-power wearable-class embedded platforms. Full article
(This article belongs to the Special Issue From Circuits to Systems: Embedded and FPGA-Based Applications)
31 pages, 7359 KB  
Article
LwAMP-Net: A Lightweight Network-Based AMP Detector on FPGA for Massive MIMO
by Zhijie Lin, Yuewen Fan, Yujie Chen, Liyan Liang, Yishuo Meng, Jianfei Wang and Chen Yang
Electronics 2026, 15(7), 1494; https://doi.org/10.3390/electronics15071494 - 2 Apr 2026
Viewed by 366
Abstract
The rapid growth of 5G necessitates wireless receivers capable of high-speed, low-latency communication under complex channel conditions. Traditional receivers struggle with the performance–complexity trade-off in massive MIMO systems, where linear detectors underperform and maximum likelihood (ML) detection becomes computationally prohibitive. Deep-learning-based model-driven approaches [...] Read more.
The rapid growth of 5G necessitates wireless receivers capable of high-speed, low-latency communication under complex channel conditions. Traditional receivers struggle with the performance–complexity trade-off in massive MIMO systems, where linear detectors underperform and maximum likelihood (ML) detection becomes computationally prohibitive. Deep-learning-based model-driven approaches have demonstrated a favorable balance between detection performance and computational cost. However, despite their algorithmic promise, the transition of these learned detectors into practical, real-time systems is critically hampered by inefficient hardware mapping, resulting in suboptimal throughput, high resource overhead, and limited scalability. To bridge this gap, this paper presents LwAMP-Net, a dedicated FPGA accelerator for a lightweight learned AMP detector. We propose a modular and multi-mode hardware architecture for LwAMP-Net, featuring an outer-product-based dataflow that mitigates pipeline stalls and multi-mode processing elements that adapt to diverse computation patterns. These innovations jointly enhance computational parallelism and resource utilization on the FPGA. Implemented on a Xilinx XC7VX690T FPGA for a 128 × 8 MIMO system with 16QAM, the accelerator achieves a 49.2% higher normalized throughput per iteration, an 85.4% improvement in throughput per LUT slice, and a 12.7% improvement in throughput per DSP compared to the state-of-the-art methods. This work provides a complete architectural solution for deploying high-performance, hardware-efficient learned MIMO detectors in real-world systems. Full article
(This article belongs to the Special Issue From Circuits to Systems: Embedded and FPGA-Based Applications)
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39 pages, 7548 KB  
Article
A Cross-Platform Toolchain for Migrating Software to an OpenRISC-Based FPGA SoC
by Roland Szabo
Electronics 2026, 15(5), 1060; https://doi.org/10.3390/electronics15051060 - 3 Mar 2026
Viewed by 385
Abstract
This paper describes the development of several software-based games using a high-level programming language (C in our case), designed so that they can be ported to a Field-Programmable Gate Array (FPGA). It also outlines the mathematical foundations underlying these games. Making executables portable [...] Read more.
This paper describes the development of several software-based games using a high-level programming language (C in our case), designed so that they can be ported to a Field-Programmable Gate Array (FPGA). It also outlines the mathematical foundations underlying these games. Making executables portable in this way can simplify running applications on FPGA platforms. Porting a game to an FPGA serves as evidence that arbitrary executables can be migrated to such hardware. The complete workflow for creating the game, along with the final game outcomes, is detailed in this paper. In addition, statistical analyses of these games were conducted. The proposed approach relies on graphics and character-handling libraries typically available in advanced programming languages. The background of this work is that a microcontroller architecture which can easily be run on a Spartan-6 FPGA was needed. The innovative point of this paper is that it created the cross-compilation toolchain on an uncommon microcontroller architecture, like the OpenRISC. Full article
(This article belongs to the Special Issue From Circuits to Systems: Embedded and FPGA-Based Applications)
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17 pages, 2317 KB  
Article
Design and Realization of Dynamically Adjustable Multi-Pulse Real-Time Coherent Integration System
by Jinrui Bi, Hongyu Zhang, Lihua Sun and Qingchao Jiang
Electronics 2026, 15(2), 397; https://doi.org/10.3390/electronics15020397 - 16 Jan 2026
Viewed by 522
Abstract
Radar signal coherent integration technology is a critical method to improve the performance of detection systems. However, existing techniques face challenges regarding real-time performance and the flexibility of multi-pulse coherent accumulation. In this paper, a dynamically configurable multi-pulse multi-frame real-time coherent integration system [...] Read more.
Radar signal coherent integration technology is a critical method to improve the performance of detection systems. However, existing techniques face challenges regarding real-time performance and the flexibility of multi-pulse coherent accumulation. In this paper, a dynamically configurable multi-pulse multi-frame real-time coherent integration system based on FPGA is designed and implemented, and the dynamic configuration of the number of pulses and the number of frames stored for each pulse is realized through the host computer. The experimental results show that the output signal delay of coherent integration is 33 microseconds at 40 pulses, and the energy gain reaches 16 dB at 40 pulses, which provides a dynamically configurable hardware platform and solution for real-time coherent integration of high-frame-count, multi-pulse radar signals. Full article
(This article belongs to the Special Issue From Circuits to Systems: Embedded and FPGA-Based Applications)
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