Dynamically Reconfigurable Technology and Chip

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "E:Engineering and Technology".

Deadline for manuscript submissions: closed (31 May 2024) | Viewed by 3006

Special Issue Editor


E-Mail Website
Guest Editor
School of Microelectronics, Xi’an Jiaotong University, Xi’an 710049, China
Interests: neural network accelerator; reconfigurable computing; accelerator for communication and networking; VLSI SoC design
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Micromachines invites manuscript submissions that address dynamically reconfigurable technology and chip, which is a crucial research topic in the field of computing architecture and VLSI design. Dynamically reconfigurable technology can improve the flexibility and adaptability of hardware by reconfiguring hardware resources at run-time, thereby performing different tasks and meeting various application requirements. Therefore, chips based on dynamically reconfigurable technology are widely used in many fields, such as neural network accelerator, post-quantum crypto and network communication, achieving excellent performance and energy efficiency. In recent years, research on dynamically reconfigurable technology and chip has mainly focused on the following directions.

One important direction is to further exploit the advantages of dynamically reconfigurable technology. According to the top-down design methodology, novel reconfigurable architectures for different scenarios should be explored first, so that the performance can be improved to the extreme. Next, it is essential to fully improve the efficiency of hardware, including processing element array, interconnection network, memory data scheduling, buffer management, configuration context storage and so on. It is worth considering that some emerging methods for hardware design have the potential to achieve high flexibility and power consumption reduction. In addition, ways to efficiently map different algorithms to reconfigurable architectures is a key point of interest. Optimization methods for mapping algorithms to reduce configuration latency is another focus area. Along with the widely used reconfigurable technology, hardware security of reconfigurable architecture and chip has also become a topic of increasing concern; some examples of hardware attacks include hardware Trojan and side-channel attack.

There are several issues in the aforementioned areas that still remain unresolved, which limit the application of dynamically reconfigurable technology and chip; as such, professionals and researchers are continually endeavoring to develop reconfigurable technology. Therefore, we invite scholars and researchers to share their latest achievements by submitting their invaluable manuscripts to this Special Issue.

We welcome submissions of both original research articles and reviews. Research areas may include (but not limited to) the following:

  • Domain-specific reconfigurable architecture, such as neural network accelerator, encryption and decryption, network communication, digital signal processing;
  • Design methodology of dynamically reconfigurable architecture;
  • Key components in reconfigurable chip, such as processing element, interconnection network, on chip buffer;
  • Algorithms deployment and applications on reconfigurable architecture;
  • Design of configuration context and mapping mechanism for dynamically reconfigurable architecture;
  • Hardware security for dynamically reconfigurable architecture against hardware Trojan, side-channel attack, fault injection, reverse engineering, electromagnetic interference attack, etc.

We look forward to receiving your contributions.

Dr. Chen Yang
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2100 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • dynamically reconfigurable technology
  • reconfigurable architectures
  • hardware
  • reconfigurable chips

Benefits of Publishing in a Special Issue

  • Ease of navigation: Grouping papers by topic helps scholars navigate broad scope journals more efficiently.
  • Greater discoverability: Special Issues support the reach and impact of scientific research. Articles in Special Issues are more discoverable and cited more frequently.
  • Expansion of research network: Special Issues facilitate connections among authors, fostering scientific collaborations.
  • External promotion: Articles in Special Issues are often promoted through the journal's social media, increasing their visibility.
  • e-Book format: Special Issues with more than 10 articles can be published as dedicated e-books, ensuring wide and rapid dissemination.

Further information on MDPI's Special Issue policies can be found here.

Published Papers (2 papers)

Order results
Result details
Select all
Export citation of selected articles as:

Research

14 pages, 5218 KiB  
Article
A High-Temperature-Resistant Stealth Bandpass/Bandstop-Switchable Frequency Selective Metasurface
by Gengyuan Bao, Peng Li, Jing Sun, Erzhan Chen and Shaojie Li
Micromachines 2024, 15(8), 948; https://doi.org/10.3390/mi15080948 - 24 Jul 2024
Cited by 1 | Viewed by 919
Abstract
We propose a bandpass/bandstop-switchable frequency-selective metasurface (FSM) designed for high-speed vehicles that generate high temperatures during flight, based on a high-temperature-resistant dielectric substrate and liquid metal (LM). We fabricated a cavity structure by utilizing a high-temperature-resistant dielectric substrate to form a metal FSM [...] Read more.
We propose a bandpass/bandstop-switchable frequency-selective metasurface (FSM) designed for high-speed vehicles that generate high temperatures during flight, based on a high-temperature-resistant dielectric substrate and liquid metal (LM). We fabricated a cavity structure by utilizing a high-temperature-resistant dielectric substrate to form a metal FSM element by introducing LM, enabling specific electromagnetic functions. The flow state of the LM can be controlled to achieve the switching of the FSM’s bandpass/bandstop performance. The bandstop characteristic has a resonance frequency of 6.1 GHz and the bandpass interval is 5.53–6.51 GHz. The bandpass characteristic has a resonance frequency of 5.41 GHz and the bandstop interval is 5.30–5.76 GHz, achieving a bandpass/bandstop switching range of 5.53–5.76 GHz. LM fluidity can aid in high-temperature heat dissipation. When the LM reaches a certain flow rate, the FSM structure’s average temperature can be reduced by an order of magnitude from a thousand to less than a hundred degrees. The FSM exhibits low RCS, with 22.35 dB and 36.79 dB reductions in bandstop and bandpass properties, respectively, compared with that of sheet metal. A prototype was developed and tested, validating the design of the FSM structure with high-temperature resistance, bandpass/bandstop switchability, and low RCS characteristics, and is expected to be applied in high-speed aircraft. Full article
(This article belongs to the Special Issue Dynamically Reconfigurable Technology and Chip)
Show Figures

Figure 1

23 pages, 19204 KiB  
Article
PaCHNOC: Packet and Circuit Hybrid Switching NoC for Real-Time Parallel Stream Signal Processing
by Peng Hao, Shengbing Zhang, Xinbing Zhou, Yi Man and Dake Liu
Micromachines 2024, 15(3), 304; https://doi.org/10.3390/mi15030304 - 23 Feb 2024
Cited by 1 | Viewed by 1742
Abstract
Real-time heterogeneous parallel embedded digital signal processor (DSP) systems process multiple data streams in parallel in a stringent time interval. This type of system on chip (SoC) requires the network on chip (NoC) to establish multiple symbiotic parallel data transmission paths with ultra-low [...] Read more.
Real-time heterogeneous parallel embedded digital signal processor (DSP) systems process multiple data streams in parallel in a stringent time interval. This type of system on chip (SoC) requires the network on chip (NoC) to establish multiple symbiotic parallel data transmission paths with ultra-low transmission latency in real time. Our early NoC research PCCNOC meets this need. The PCCNOC uses packet routing to establish and lock a transmission circuit, so that PCCNOC is perfectly suitable for ultra-low latency and high-bandwidth transmission of long data packets. However, a parallel multi-data stream DSP system also needs to transmit roughly the same number of short data packets for job configuration and job execution status reports. While transferring short data packets, the link establishment routing delay of short data packets becomes relatively obvious. Our further research, thus, introduced PaCHNOC, a hybrid NoC in which long data packets are transmitted through a circuit established and locked by routing, and short data packets are attached to the routing packet and the transmission is completed during the routing process, thus avoiding the PCCNOC setup delay. Simulation shows that PaCHNOC performs well in supporting real-time heterogeneous parallel embedded DSP systems and achieves overall latency reduction 65% compared with related works. Finally, we used PaCHNOC in the baseband subsystem of a real 5G base station, which proved that our research is the best NoC for baseband subsystem of 5G base stations, which reduce 31% comprehensive latency in comparison to related works. Full article
(This article belongs to the Special Issue Dynamically Reconfigurable Technology and Chip)
Show Figures

Figure 1

Back to TopTop