Hardware/Algorithm Co-Design for Communication and Networking Acceleration

Dear Colleagues,

Electronics invites manuscript submissions in the area of hardware/algorithm co-design for communication and networking acceleration. In the rapidly evolving landscape of communication and networking, the demands placed on both hardware and software have escalated significantly. The complexity of communication scenarios has grown with the advent of 5G and beyond, where traditional algorithms struggle to cope with high-speed, low-latency, and high-reliability requirements. Meanwhile, network transmission speeds have surged to 100GbE and beyond, accompanied by an explosion in the number of connected devices, leading to increasingly intricate network topologies. This transformation necessitates new paradigms such as Software-Defined Networking (SDN) and Network Function Virtualization (NFV), which introduce additional layers of abstraction and flexibility but also demand more sophisticated management and processing capabilities. Given these challenges, it is evident that conventional algorithmic approaches are no longer sufficient to meet the performance and efficiency needs of modern communication and networking systems. Leveraging hardware-based or hardware–software co-design solutions can provide a significant advantage. By utilizing platforms like Application-Specific Integrated Circuits (ASICs) or Field-Programmable Gate Arrays (FPGAs), researchers and engineers can develop tailored accelerators that not only enhance system performance but also reduce power consumption and cost. Moreover, the integration of artificial intelligence (AI) into communication and networking has shown promise in optimizing resource allocation, improving security, and enabling adaptive, self-managing networks.

This Special Issue of Electronics aims to bring together cutting-edge research in hardware/algorithm co-design for communication and networking acceleration. It seeks to explore innovative methodologies, architectures, and technologies that address the current limitations and open up new possibilities for future systems. By fostering a deeper understanding of how hardware and software can be synergistically combined, this issue will contribute to the development of more efficient, scalable, and intelligent communication and networking infrastructures.

We welcome original research articles and reviews on topics including but not limited to the following:

• Acceleration strategies for large-scale MIMO, millimeter-wave, terahertz communications, and efficient signal processing on hardware platforms, focusing on low-power and high-throughput designs.

• Hardware-accelerated packet classification, congestion control, resource management, and virtualization techniques for SDN, NFV, and emerging network architectures to enhance performance and scalability.

• Techniques for accelerating network protocol stacks, encryption, decryption, and compute-intensive tasks in edge and cloud environments, aimed at reducing latency and improving throughput in data centers.

• Integration of machine learning and AI for predictive maintenance, anomaly detection, network management, automation, and dynamic resource allocation, leveraging reinforcement learning for adaptive systems.

5. Emerging Architectures and Acceleration Techniques:

• Novel architectures and advanced methods for next-generation communication systems.

Dr. Chen Yang
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

• hardware/algorithm co-design
• communication systems
• networking
• ASIC
• FPGA
• large-scale MIMO
• SDN
• NFV
• packet classification
• congestion control
• AI
• machine learning
• network acceleration
• hardware offloading
• emerging architectures