Emerging Topics in Hardware Security (2nd Edition)

A Special Issue of Cryptography (ISSN 2410-387X) belonging to the section "Hardware Security".

Deadline for manuscript submissions: 30 November 2026 | Viewed by 1935

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Department of Electrical and Computer Engineering, University of New Mexico, Albuquerque, NM 87131, USA
Interests: hardware security and trust and design for manufacturability
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Special Issue Information

Dear Colleagues,

We invite authors to submit research papers on topics related to hardware-based authentication; encryption and secure boot protocols for resource-constrained embedded systems, on novel side-channel analysis attacks and countermeasures, on PUFs for ICs and printed circuit boards (PCBs) capable of providing security, trust and detection of tamper, on hardware Trojan attacks, analysis, detection methods and countermeasures, on supply-chain authentication and hardware assurance methods, on hardware-based security and trust primitives for RFID (radio frequency identification); IoT; autonomous vehicles; embedded medical; and industrial control; communication and other types of critical infrastructure; and on reverse engineering techniques and countermeasures to protect ICs and IPs through obfuscation and active metering schemes.

Prof. Dr. Jim Plusquellic
Guest Editor

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Keywords

  • hardware security and trust
  • physical unclonable functions
  • side channel attacks and countermeasures
  • microprocessor security

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Related Special Issue

Published Papers (2 papers)

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Research

23 pages, 673 KB  
Article
Leakage Assessment and Correlation Power Analysis of the MAYO Secret Linear Map on a Cortex-M4: A Reproducible Case Study and a Validated First-Order Countermeasure
by Virginia Lampropoulou, Achilleas Economopoulos, Michail-Alexandros Kourtis, George Xilouris, Marcin Niemiec and Filip Opiłka
Cryptography 2026, 10(5), 68; https://doi.org/10.3390/cryptography10050068 - 11 Sep 2026
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Abstract
This work presents a complete power side-channel evaluation of the MAYO secret linear map on a constrained embedded target, together with a first-order countermeasure evaluated on the same hardware. While MAYO ranks among the most embedded-friendly candidates in the National Institute of Standards [...] Read more.
This work presents a complete power side-channel evaluation of the MAYO secret linear map on a constrained embedded target, together with a first-order countermeasure evaluated on the same hardware. While MAYO ranks among the most embedded-friendly candidates in the National Institute of Standards and Technology (NIST) additional-signatures call, few countermeasures for it are quantified against an explicit leakage threshold. The unprotected map O·xi over GF(16) is evaluated against a masked and row-shuffled variant under an identical acquisition procedure. Test Vector Leakage Assessment (TVLA) of the unprotected map peaks at |t|=52.88 fixed-versus-random and at |t|=195.7 under a secret-dependent fixed-versus-fixed test, while a non-profiled Correlation Power Analysis (CPA) resolving the multiplicative-identity alias and temporal row-mixing collapses the first key row from 168 to 24 candidates, with a median of 287 measured across 20 independent random keys. The proposed countermeasure pairs masking with per-pass row shuffling, in order to suppress the micro-architectural residue masking alone leaves; it realizes a leakage reduction approaching 54×, to |t|=3.62 with no failing point out of 24,000, at roughly 2.22× cycles. The evaluation is a laboratory assessment of the isolated map on an STM32F303 (ARM Cortex-M4) measured with a ChipWhisperer-Lite, and does not exercise complete MAYO signing. Full article
(This article belongs to the Special Issue Emerging Topics in Hardware Security (2nd Edition))
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41 pages, 3933 KB  
Article
Hybrid Architecture for Protected Data Communication Inside the Private Cloud
by Biswaranjan Senapati, Lalit Narayan Mishra, Awad Bin Naeem and Amit J. Rangari
Cryptography 2026, 10(3), 36; https://doi.org/10.3390/cryptography10030036 - 2 Jun 2026
Viewed by 1107
Abstract
Private cloud object stores provide infrastructure isolation but leave application-layer data exposed to insider threats and compromised credentials. This paper presents an engineering integration of an Add-Rotate-XOR (ARX) block cipher and multi-bit Least Significant Bit (LSB) steganography into an end-to-end pipeline for private [...] Read more.
Private cloud object stores provide infrastructure isolation but leave application-layer data exposed to insider threats and compromised credentials. This paper presents an engineering integration of an Add-Rotate-XOR (ARX) block cipher and multi-bit Least Significant Bit (LSB) steganography into an end-to-end pipeline for private MinIO object storage. The cipher, KREA v2, is a SPECK-64/128 derived ARX construction with three application-driven choices: CRC32 key whitening, byte-aligned rotations (α=7, β=2), and deterministic CTR-mode nonces. Mixed Integer Linear Programming (MILP) trail analysis matches SPECK-64/128’s minimum-trail weights through rounds 1–4. KREA v2 ciphertext meets standard keystream-quality preconditions (NIST SP 800-22 battery, 49.98% mean avalanche, Shannon entropy 7.9992–7.9998 bits/byte across realistic XML, JSON, video, and HTTP/2 payloads). Modified LSB (MLSB) embeds 3 bits per RGB channel with an XOR watermark at 37–38 dB Peak Signal-to-Noise Ratio (PSNR), providing 3× standard-LSB capacity. Steganalysis uses chi-square and RS detectors plus a Convolutional Neural Network (CNN) detector (Yedroudj-Net) trained on 8000 BOSSBase-1.01 cover/stego pairs; CNN area under the ROC curve is ≥0.999 against the watermarked variant. The MinIO pipeline runs at 355.1 ms (68.6% network I/O) with 100% message fidelity. The XOR watermark increases RS detectability above 75% capacity; a 200-image ablation cuts median RS detection (0.289 to 0.000) and mean (0.342 to 0.130) in a sparse-keystream variant, prioritised for follow-on full-scale evaluation. The architecture is offered as a documented engineering integration with explicit security caveats and threat-model boundaries, not as a production-hardened cryptographic primitive. Full article
(This article belongs to the Special Issue Emerging Topics in Hardware Security (2nd Edition))
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