Bulk-Driven vs. Gate-Driven OTAs in Deep-Subthreshold ULV Operation: Analytical and Robustness Comparison in Self-Cascode Architectures

Abstract

This work presents a comprehensive analytical and simulation-based comparison between bulk-driven (BD) and gate-driven (GD) operational transconductance amplifiers (OTAs) operating in the deep-subthreshold ultra-low-voltage regime. While BD techniques are traditionally considered unsuitable for high-performance analog design due to their lower transconductance efficiency, this study demonstrates that, when combined with self-cascode structures, BD architectures achieve competitive intrinsic gain, enhanced input common-mode range, and improved slew rate efficiency under nanoampere bias conditions. To support these claims, closed-form analytical derivations, dynamic analysis, and comprehensive Monte Carlo and PVT simulations are provided to quantify robustness and mismatch sensitivity. The results establish a systematic framework for evaluating BD versus GD architectures under identical technology and power constraints, offering practical design guidelines and optimized self-cascoded topologies for next-generation energy-autonomous systems.

1. Introduction

The relentless demand for energy-autonomous electronic devices within the frameworks of the Internet of Things (IoT) [1], wearable, biomedical, and implantable microsystems [2,3,4,5,6], and even in sectors not traditionally related, such as automotive electronics [7], continues to grow. As a result, analog integrated circuit (IC) design has been pushed toward the deep ultra-low-voltage (ULV) and ultra-low-power (ULP) frontiers. Operating circuits with supply voltages (V_DD) significantly below 1 V, often approaching or even falling below the threshold voltage (Vth) of the CMOS process, with current consumption in the range of a few nanoamperes, is no longer a niche requirement. Such operation is necessary to maximize battery longevity and enable operation from purely energy-harvested sources.

In this framework, conventional gate-driven (GD) MOS configurations in strong inversion (SI) face severe headroom limitations. Since the gate-to-source voltage (V_GS) must exceed Vth to maintain sufficient inversion levels, the input common-mode range (ICMR) becomes severely constrained [8]. To mitigate these limitations, operating devices in the subthreshold (specifically, weak inversion, WI) regime is particularly advantageous. This approach allows for a significant reduction in the required overdrive voltage while maximizing the transconductance-to-current (g_m/I_D) ratio [9]. In this region, the MOS transistor behavior shifts from a square-law dependency to an exponential relationship, effectively mimicking the operation of a bipolar junction transistor. However, even in the subthreshold, GD implementations remain “voltage constrained.” Consider, for instance, a standard n-type differential pair, M₁-M₂, with a tail current source M₃. The minimum input common-mode voltage ensuring saturation of the transistor implementing the tail current generator is limited by V_ICM,min = V_GS1,2 + V_DS3,sat.

In ULV designs where V_DD is scaled down to 500 mV or less, this requirement can consume nearly the entire supply rail, limiting the input signal to a narrow window near V_DD and leaving zero headroom for signal swings. While complementary parallel p- and n-type structures can achieve rail-to-rail operation, they introduce significant complexity and the challenge of maintaining a constant total transconductance [8,10].

To circumvent these topological bottlenecks, the bulk-driven (BD) (a.k.a. body-driven) technique has emerged as a compelling alternative [11,12,13,14,15]. By applying the signal to the body terminal, the Vth requirement is effectively decoupled from the signal path, allowing for rail-to-rail or even supra-rail ICMR. This represents a fundamental shift from a voltage-limited path to a current-modulated path, where the bulk terminal acts as a secondary gate with no DC voltage requirement relative to channel formation, thereby enabling true deep ULV functionality that remains robust even as Vth exceeds V_DD.

Despite these potential advantages, the BD approach is often regarded as unsuitable for high-performance analog VLSI applications and still receives limited acceptance in industrial practice. This perception stems from the inherently lower transconductance associated with the bulk terminal (g_mb is approximately 0.1–0.25 times g_m) and concerns regarding device modeling, robustness and reliability. Indeed, the bulk terminal was historically treated as a parasitic back-gate for which PVT (Process, Voltage, and Temperature) modeling accuracy was considered inferior to that of gate-driven operation. Additional drawbacks include the need for accessible bulk terminals (requiring triple-well or independent-well technologies), potential latch-up phenomena, and the need to avoid forward-biasing the bulk–source junction. However, several of the aforementioned issues have been progressively addressed, as demonstrated in the recent literature, including the recent work by the authors [15]. In particular, advances in processes, device modeling, circuit technologies and layout strategies have shown that bulk-driven implementations can achieve performance and robustness levels compatible with practical ULV-ULP (low-frequency) analog applications. Moreover, supply voltages below 0.4 V prevent significant forward-biasing of the body–source junction, thereby inherently avoiding latch-up.

Nevertheless, while several works have explored BD and GD amplifiers separately, a rigorous head-to-head comparative framework based on the same technology and comparable power budgets is still lacking. Building upon these premises, this paper presents an extensive and systematic analytical comparison between a BD OTA and a comparable GD counterpart, extending previous preliminary communication by the authors [16]. Both designs leverage the self-cascode (SC) structure to significantly enhance the intrinsic gain by providing a very high output resistance, thereby compensating for the reduced transconductance of the BD stage [17,18,19]. Specifically, the new contributions of this work include the following:

• A detailed analytical derivation of the self-cascode gain enhancement in subthreshold BD vs. GD stages, providing formal design equations for ULV operation.
• An expanded investigation into dynamic performance, demonstrating how the lower compensation requirements of BD OTAs can lead to a superior slew rate (SR) while maintaining comparable CMRR and PSRR.
• A comprehensive sensitivity analysis including Monte Carlo simulations for mismatch and PVT variations, quantifying the robustness of both architectures in deep-subthreshold regimes.

The paper is organized as follows: Section 2 describes the theoretical background of subthreshold operation. Section 3 explains the self-cascode structure, whereas Section 4 describes the architectural implementations of GD and BD designs using SC. Section 5 provides a formal theoretical comparison of the small-signal, large-signal and noise parameters. Section 6 discusses the pre-layout simulation results, corners and PVT simulation results, while Section 7 draws the final conclusions.

2. Theoretical Background

To accurately compare GD and BD architectures in the ULV regime, the physical behavior of the MOS transistor in weak inversion [20,21,22] must be first characterized. In the subthreshold region, the drain current, I_D, is dominated by diffusion rather than drift, as expressed in (1):

$$I_D=I_{D0}{\displaystyle \frac{W}{L}}{e}^{{\displaystyle \frac{V_{GS}-V_{th0}}{n{V}_T}}}{e}^{{\displaystyle \frac{(n-1)V_{BS}}{n{V}_T}}}(1-e^{-{\displaystyle \frac{V_{DS}}{V_T}}})$$

(1)

where I_D0 is the process-dependent current at V_GS = V_th0, W/L is the aspect ratio, V_T = kT/q is the thermal voltage (T is the absolute temperature, k is the Boltzmann constant, and q is the charge of the electron), and n is the subthreshold slope factor. Parameter n represents the nonideal capacitive coupling between the gate voltage and the channel surface potential equal to (1 + C_dep/C_ox), and usually ranges from 1.2 to 1.4 in standard CMOS processes. For a device operating in subthreshold saturation (V_DS ≥ 3V_T ~ 4V_T with good approximation), the term in parentheses approaches unity in (1), so that the drain current can be expressed as

$$I_D=I_S{e}^{{\displaystyle \frac{V_{GS}-V_{th0}}{n{V}_T}}}{e}^{{\displaystyle \frac{(n-1)V_{BS}}{n{V}_T}}}$$

(2)

where I_S = I_D0 (W/L).

To ensure operation in the weak inversion region, where the g_m/I_D (g_m is the gate transconductance) ratio reaches its maximum and remains approximately constant, the following condition is imposed:

$$V_{th0}-4V_T<V_{GS}<V_{th0}-3V_T$$

(3)

As is well known, at room temperature (300 K), 4V_T is approximately 100 mV. For lower values of V_GS (V_GS < V_th0 − 4V_T), we enter the deep-subthreshold region, which should be avoided because device mismatch increases, leakage currents become comparable to I_D, and mobility degradation and trap effects appear.

We can also evaluate, from (2), the small-signal gate and bulk transconductances in weak inversion:

$$g_m={\displaystyle \frac{\partial I_D}{\partial V_{GS}}}={\displaystyle \frac{I_D}{n{V}_T}}$$

(4)

$$g_{mb}={\displaystyle \frac{\partial I_D}{\partial V_{BS}}}=\left(n-1\right)g_m$$

(5)

For comparison purposes, Table 1 summarizes the primary analytical differences between strong and weak inversion regimes.

Table 1. Comparison of MOS parameters: strong vs. weak inversion.

Parameter	Strong Inversion (Saturation)	Weak Inversion (Saturation)
Drain Current (ID)	${\displaystyle \frac{1}{2}}\mu C_{ox}{\displaystyle \frac{W}{L}}{(V_{GS}-V_{th0})}^2$	$I_0{\displaystyle \frac{W}{L}}{e}^{{\displaystyle \frac{V_{GS}-V_{th0}+(n-1)V_{BS}}{n{V}_T}}}$
Gate Transconductance (gm)	${\displaystyle \frac{2I_D}{V_{GS}-V_{th0}}}$	${\displaystyle \frac{I_D}{n{V}_T}}$
Bulk Transconductance (gmb)	$\eta g_m$	$(n-1)g_m$
Efficiency (gm/ID)	${\displaystyle \frac{2}{V_{GS}-V_{th0}}}\left(\mathrm{Lower} \mathrm{efficiency}\right)$	${\displaystyle \frac{1}{n{V}_T}}\left(\mathrm{maximum}/\mathrm{constant} \mathrm{efficiency}\right)$
Saturation Condition (VDS,sat)	$V_{DS}\ge V_{GS}-V_{th0}$	$V_{DS}\ge 3V_T\sim 4V_T$

In strong inversion, η represents the ratio of the bulk transconductance g_mb to the gate transconductance g_m, and is given as

$$\eta ={\displaystyle \frac{g_{mb}}{g_m}}={\displaystyle \frac{\gamma }{2\sqrt{\left|2{\varphi }_F-V_{BS}\right|}}}$$

(6)

While the analytical expressions for g_m and g_mb differ between inversion regions due to the dominant transport mechanisms (drift vs. diffusion in strong and weak inversion, respectively), the ratio g_mb/g_m remains physically linked to the capacitive coupling between the gate and the bulk. In both cases, this ratio is a direct manifestation of the substrate sensitivity, numerically represented by the term (n − 1) or η. In strong inversion, the depletion capacitance C_dep is defined as

$$C_{dep}={\displaystyle \frac{{\epsilon }_{si}}{x_d}}=\sqrt{{\displaystyle \frac{q{\epsilon }_{si}{N}_A/2}{\left|2{\varphi }_F-V_{BS}\right|}}}$$

(7)

Since $\gamma ={\displaystyle \frac{\sqrt{2q{\epsilon }_{si}{N}_A}}{C_{ox}}}$, substituting this into Equation (6) yields

$$\eta ={\displaystyle \frac{\sqrt{2q{\epsilon }_{si}{N}_A}}{C_{ox}2\sqrt{\left|2{\varphi }_F-V_{BS}\right|}}}={\displaystyle \frac{C_{dep}}{C_{ox}}}$$

(8)

Therefore,

$$\eta ={\displaystyle \frac{C_{dep}}{C_{ox}}}=n-1$$

(9)

Since n is typically between 1.2 and 1.4, the value of η is typically between 0.2 and 0.4. Both in SI and WI, the bulk is then less effective at controlling the channel than the gate, but driving the MOS from the bulk remains the only solution when we want to circumvent the threshold-limited topological bottlenecks of the GD approach. In this way, the Vth requirement is effectively decoupled from the signal path, allowing for rail-to-rail input swings. Because the BD OTA has such a wide ICMR, a single differential pair can be used to cover the whole range, whereas a GD OTA would require a complex (and power-hungry) complementary (nMOS parallel pMOS) differential input stage to achieve similar results, which also requires special and complex structures to ensure constant g_m at different CM input levels.

3. The Self-Cascode Structure

Before discussing full OTA architectures, we analyze the self-cascode composite structure as a basic building block. In this manuscript, g_m and g_mb denote the intrinsic gate and bulk transconductances of individual MOS transistors, respectively, whereas G_mi represents the effective transconductance of the i-th OTA stage or equivalent small-signal block.

3.1. Topology

In ULV design, traditional cascoding is often avoided because it requires an additional biasing voltage and increases the minimum output voltage, which limits the signal swing. The self-cascode composite transistor (SCCT) configuration, shown in Figure 1a, provides a compelling solution [17,18,19]. It consists of two transistors (M_casc and M_main) of the same type (nMOS or pMOS) connected in series, with their gates tied together.

Figure 1. (a) N-type self-cascode topology. (b) N-type self-cascode with different threshold transistors: SVT, standard (higher) threshold; MVT, medium (lower) threshold.

The self-biasing effect occurs because the lower transistor (M_main) is typically designed with a much larger W/L ratio or a longer channel length than the upper transistor (M_casc). This sizing ensures that both transistors and specifically M_main remain biased in saturation. In both SI and WI regimes, this composite structure behaves as a single transistor with a significantly higher effective output resistance (r_out,eff):

$$\begin{array}{c}{r}_{out,eff}=r_{ds,casc}+r_{ds,main}+\left(g_{m,casc}+g_{mb,casc}\right)r_{ds,casc}{r}_{ds,main}\\ \approx \left(g_{m,casc}+g_{mb,casc}\right)r_{ds,casc}{r}_{ds,main}\end{array}$$

(10)

where the bulks of M_main and M_casc are assumed to be connected to V_SS. This cascode effect multiplies the intrinsic resistance of the main transistor by the product of intrinsic gain and intrinsic resistance of the cascode device, significantly reducing the impact of channel-length modulation. The effective transconductance (g_m,eff) of the composite device can be approximated by considering the small-signal current generated by both transistors. However, because they are in series, the same current must flow through both. Analytically, the effective transconductance of the self-cascode is expressed as

$$g_{m,eff}={\displaystyle \frac{g_{m,main}}{1+\frac{1}{r_{ds,main}(g_{m,casc}+g_{mb,casc}+g_{ds,casc})}}}\approx g_{m,main}$$

(11)

Since the denominator approaches unity in saturation, the effective transconductance is almost entirely defined by the transconductance of the M_main transistor. The total voltage gain (A_v) of the self-cascode stage is then the product of its effective transconductance and its effective output resistance:

$$A_v=g_{m,eff}{r}_{out,eff}\approx g_{m,main}\left[\left(g_{m,casc}+g_{mb,casc}\right)r_{ds,casc}{r}_{ds,main}\right]$$

(12)

When both devices operate in the saturation of weak inversion, the high transconductance efficiency (g_m/I_D) yields a very high A_v. This makes the self-cascode an ideal candidate for high-gain, single-stage OTA designs where power consumption and supply voltage are constrained.

3.2. Trade-Offs in W/L Sizing and Threshold Voltage Selection

When sizing the SCCT structure for operation in weak inversion, the design space is defined by a compromise between transconductance efficiency, output impedance, and silicon area.

• W/L Sizing for Efficiency and Area

Case I: Fixed Current (I_D,GD = I_D,BD): To offset the lower transconductance of the BD-OTA (g_mb = η g_m), we use a large (W/L)_BD. This ensures that the device operates at the absolute peak of the g_m/I_D curve. While W/L does not increase g_m beyond the I_D/(nV_T) limit, it ensures we do not drop below that limit due to moderate inversion.

Case II: Fixed Transconductance (G_m,GD = G_m,BD): To match GD performance, the BD-OTA requires 1/η more current. Consequently, (W/L)_BD is typically scaled up by a factor of 1/η, accepting the trade-off of higher parasitic capacitances.

2.

Output Resistance and Channel Length

To maximize the DC voltage gain, M_casc can be designed with a longer channel length than M_main. This minimizes channel-length modulation, increasing r_ds,casc and boosting the total r_out,eff, as derived in (10).

3.

Threshold Voltage

Commercial CMOS processes usually offer standard-, medium- and low-threshold transistors, with decreasing values of the threshold, respectively. As proposed by the authors in [15], using a medium-Vth (MVT) device for M_casc and a standard-Vth (SVT) device for M_main, as shown in Figure 1b, we ensure that M_main remains in the saturation region (V_DS ≥ 3V_T) even under extremely low supply voltages. This approach decouples the sizing of the cascode from the need to provide high voltage headroom.

4.

Noise

If g_m is fixed, the thermal noise power spectral density (4kTγ/g_m) remains constant. However, using a large W/L allows us to keep the transistor in weak inversion, where g_m is at its maximum possible value for a specific drain current. Furthermore, a large W/L provides a direct benefit in reducing flicker (1/f) noise. By scaling up the width to maintain weak inversion, we inherently increase the total area, which significantly reduces the 1/f noise contribution of the input pair.

In conclusion, for bulk-driven OTAs, where the effective input transconductance is inherently limited by the lower body transconductance (g_mb), maximizing the intrinsic gain of the input stage is particularly important. The self-cascode configuration directly addresses this limitation by increasing the effective output resistance of the input branch without requiring additional voltage headroom or extra bias current. Hence, the SC structure allows bulk-driven input stages to recover a significant portion of the gain typically lost compared to gate-driven implementations, while still preserving the ultra-low-voltage capability essential for sub-0.5 V analog design.

4. OTA Topologies

4.1. Gate-Driven OTA

The topology of the gate-driven (GD) OTA, illustrated in Figure 2, represents a complete two-stage OTA. To improve the output resistance and intrinsic gain, all transistors throughout the amplifier consistently utilize the SCCT structure. A regular/thicker gate line drawing style indicates medium/standard threshold voltage transistors. The input stage is configured as a conventional differential pair where the differential input signal (V_in+–V_in−) is applied directly to the gate terminals of the p-channel composite transistors (M_1a,b and M_2a,b). To achieve similar biasing conditions with the BD counterpart, the bulk of differential stage input transistors in GD is connected to a constant bias voltage, V_A.

Figure 2. SCCT-based gate-driven OTA.

The tail current for this differential pair is established by the p-channel current source M₇. The gate of this tail transistor, along with those of the output stage current load (M_5a,b), mirrors a weighted copy of the reference current (I_B) irrespective of supply voltage fluctuations, which is crucial for maximizing the power-supply rejection ratio (PSRR). The differential pair’s output current is converted from differential to single-ended by the active current mirror load, comprising the n-channel SCCT structures M_3a,b and M_4a,b. The single-ended output signal from the first stage is then fed to the second gain stage implemented by an n-channel common-source composite transistor M_6a,b with M_5a,b serving as the load devices.

Regarding voltage levels and regions of operation, the vertical stack of composite transistors combined with the tail transistor (M₇) necessitates 5 V_DS,SAT (M₇, M_1a, M_1b, M_3a and M_3b) to maintain subthreshold saturation for all devices, assuming a V_DS,SAT of typically 100 mV requires a supply voltage of 500 mV. The use of different threshold flavors helps to balance the threshold requirements of the cascoded stack.

Finally, frequency compensation, essential for stability, is implemented via a current buffer Miller compensation scheme which exploits capacitor C_C and the inherent current buffer behavior of transistor M_2b [23,24].

4.2. Bulk-Driven OTA

The first stage of the schematic in Figure 3 is composed of a tail-less differential input pair formed by transistors M_1a,b and M_2a,b. Transistors M_3a,b and M_4a,b operate as an active load and simultaneously perform the differential-to-single-ended conversion. The second gain stage is realized through a gate-driven common-source configuration using M_6a,b, with M_5a,b serving as the load devices. The bulk terminal of M_5a,b is connected to the inverting input $V_{in-}$, enabling class AB operation, in which the maximum sourcing and sinking output currents are not limited by the bias current.

Figure 3. SCCT-based bulk-driven OTA.

The bias current is established by the current source I_B together with transistors M_7a,b–M_10a,b. This network generates the bias voltage V_B, which is applied to the gates of both the differential input pair and the output load devices, thereby setting the operating currents in the differential and output branches independently of the supply voltage $V_{DD}$ and the input common-mode level [15,25].

A decrease (increase) in V_in,cm causes V_B to increase (decrease), as transistors M_7A,B–M_8A,B inherently adapt their source-gate voltage to fit their constant bias current. The V_B increase (decrease) determines then the bias current of M_1A,B–M_2A,B constantly and independently of supply and common-mode voltage, resulting in an improved common-mode rejection ratio (CMRR) and power-supply rejection ratio (PSRR).

Note that this common-mode stage feedback arrangement also provides a differential response from the otherwise pseudo-differential pair M_1a,b–M_2a,b.

Finally, because the architecture stacks up to four transistors vertically (M_1a, M_1b, M_3a and M_3b), a voltage headroom of 4V_DS,SAT is required. Assuming a typical V_DS,SAT of 100 mV, the minimum necessary supply voltage is 400 mV.

5. Comparative Analysis: GD vs. BD OTA Performance

This section provides a detailed comparative analysis of the proposed GD and BD OTA topologies, focusing on key figures of merit including gain, bandwidth, noise, and rejection ratios.

5.1. Differential DC Gain

For a two-stage OTA, the overall differential-mode DC gain (A_DM) can be expressed as the product of the individual stage gains:

$$A_{DM}(0)=G_{m1}{R}_{o1}{G}_{m2}{R}_{o2}$$

(13)

where R_o1 and R_o2 represent the output resistances of the first and second stages, respectively. These resistances are designed to be approximately equivalent in both GD and BD configurations. Similarly, the second-stage transconductance, G_m2, is approximately identical for both cases and corresponds to the transconductance of the common-source transistor M_6b.

The fundamental difference lies in the first-stage transconductance, G_m1. For the GD OTA, G_m1 is the gate transconductance (g_m1,2), whereas, for the BD OTA, it is the bulk transconductance (g_mb1,2). Since, from (6), g_mb = η g_m, the intrinsic gain of the BD stage is significantly lower. Consequently,

$${\displaystyle \frac{A_{DM}^{GD}(0)}{A_{DM}^{BD}(0)}}={\displaystyle \frac{g_{m1\mathrm{a},2\mathrm{a}}}{g_{mb1\mathrm{a},2\mathrm{a}}}}={\displaystyle \frac{1}{\eta }}$$

(14)

5.2. Compensation Capacitor and Gain–Bandwidth Product

The Gain–Bandwidth Product (GBW) is the product of the dc gain and the dominant pole frequency. In a two-stage OTA, the dominant pole is established by Miller compensation, where ω_p1 = 1/(R_o1G_m2R_o2C_C). From (13), the GBW is the ratio of the first-stage transconductance to the compensation capacitance:

$$GBW={\displaystyle \frac{G_{m1}}{C_C}}$$

(15)

The second pole (ω_p2), which primarily limits stability and high-frequency performance, is located at the output of the second stage. Its frequency is determined by the transconductance of the second stage (g_m2) and the load capacitance (C_L). The stability of the amplifier is quantified by the phase margin (ϕ_m). In a Miller-compensated system, if we neglect the right-half-plane (RHP) zero (often mitigated by a nulling resistor or a current buffer), the phase margin can be expressed as the difference between 180° and the phase shift contributed by the poles at the unity-gain frequency.

Since the dominant pole contributes a 90° phase shift at GBW, the phase margin is determined by the proximity of the second pole:

$${\varphi }_m=90°-\arctan \left({\displaystyle \frac{GBW}{{\omega }_{p2}}}\right)$$

(16)

Substituting the expressions for GBW and ω_p2, we obtain

$${\varphi }_m=90°-\arctan \left({\displaystyle \frac{G_{m1}}{G_{m2}}}{\displaystyle \frac{C_L}{C_C}}\right)$$

(17)

Equation (17) highlights an advantage of bulk-driven architecture. In a BD stage, the transconductance G_m1 = g_mb is naturally lower than the gm of a GD stage. To maintain the same phase margin and load capacitance as a GD OTA, the BD design allows for a proportional reduction in the compensation capacitor. Specifically,

$$C_C^{BD}\approx \eta C_C^{GD}$$

(18)

Because in (15) both the numerator (G_m1) and the denominator (C_C) of the GBW expression scale by the same factor η, the resulting Gain–Bandwidth Product remains theoretically constant between the two architectures, despite the weaker driving capability of the bulk terminal.

5.3. Slew Rate Performance

In two-stage OTA topologies, the slew rate (SR) is governed by two distinct mechanisms related to the charging/discharging of the compensation capacitor and the load capacitor, referred to as the internal and external SR, respectively. For a given bias (tail) current (I_bias), the internal slew rate is defined as

$$S{R}_{\mathrm{int}}={\displaystyle \frac{I_{bias}}{C_C}}$$

(19)

As established in the previous section, BD OTAs require a smaller C_C to maintain stability compared to their GD counterparts. Consequently, for the same current budget, BD architectures inherently exhibit a superior internal SR. Furthermore, tail-less BD stages often benefit from intrinsic class AB behavior [26]. These characteristics enhance the transient response, resulting in a more responsive amplifier under large-signal conditions.

5.4. Noise Analysis

The dominant noise contributions in an OTA are primarily localized within the input stage, specifically originating from the input differential pair and the active load current mirrors. In architectures employing self-cascode composite transistors (SCCTs), the noise is predominantly generated by the common-source transistors, while the contribution of the cascode transistors remains negligible. Similarly, the noise from the second stage is attenuated when referred to the input by the high gain of the first stage.

The equivalent input-referred noise power spectral density (PSD), accounting for both thermal (white) and flicker (1/f) components, can be expressed as

$$S_{v,in}(f)\approx {\displaystyle \frac{8kT\gamma }{G_{m1}}}\left(1+{\displaystyle \frac{g_{m3b,4b}}{G_{m1}}}\right)+{\displaystyle \frac{K_f}{C_{OX}^{2}WLf}}$$

(20)

In this expression, γ represents the thermal noise coefficient (typically 2/3 for long-channel devices). While advanced sub-micron technologies may require more sophisticated models to account for short-channel effects, (20) serves as a valid basis for a comparative assessment.

The general analytical conclusion is that BD OTAs exhibit higher thermal noise levels due to the inherently lower transconductance (G_m1 = g_mb). Furthermore, the term inside the parentheses in (20) cannot be considered negligible in BD OTAs, whereas typically in GD OTAs it is as long as g_m3b,4b << g_m1a,2a. Finally, flicker noise performance in BD devices is often degraded; the flicker noise coefficient (K_f) can be larger due to the body effect, and the bulk terminal is more susceptible to substrate noise and interface traps, further increasing the 1/f noise floor.

5.5. CMRR and PSRR

The common-mode gain, A_CM, is evaluated by applying a common-mode signal v_i,CM to the inputs of the two OTAs. The CMRR is obtained as A_DM/A_CM, where the gain contribution of the second OTA stages does not play any role because it appears on both A_DM and A_CM.

The CMRR at DC of the GD OTA is expressed as

$$CMR{R}^{GD}(0)\approx 2{\displaystyle \frac{g_{m1,2}+g_{mb1,2}}{\epsilon }}{r}_{d7}$$

(21)

where r_d7 is the output resistance of the tail current generator (M₇ in Figure 2) and ε is the M_3B–M_4B current mirror relative error (i.e., i_d4/i_d3 = 1 + ε).

Regarding the PSRR of the GD OTA, it is simulated as an AC signal superimposed on V_DD and is treated by the OTA as a common-mode signal. Consequently, it can be demonstrated that the following relation between PSRR (0) and CMRR (0) exists:

$$PSR{R}^{GD}(0)\approx 2{\displaystyle \frac{g_{m1,2}}{\epsilon }}{r}_{\mathrm{d}7}\approx {\displaystyle \frac{g_{m1,2}}{g_{m1,2}+g_{mb1,2}}}CMR{R}^{GD}(0)$$

(22)

Hence, PSRR (0) is almost equal to CMRR (0) in the GD OTA.

For the BD OTA, by inspection of the auxiliary common-mode/biasing section, the voltage v_B,CM caused by the common-mode input is

$$v_{B,CM}=-{\displaystyle \frac{2g_{mb7\mathrm{A},8\mathrm{A}}{R}_{oB}}{1+2g_{m7\mathrm{A},8\mathrm{A}}{R}_{oB}}}{v}_{i,CM}$$

(23)

where $R_{oB}={\left(g_m{r}_d\right)}_{9\mathrm{A}}{r}_{d9\mathrm{B}}$ is the equivalent small-signal resistance offered by transistors M_9A,B. This voltage is applied to the gates of transistors M_1A-2A, and the resulting small-signal drain current of M_2A is therefore

$$i_{d1\mathrm{A},2\mathrm{A},CM}=g_{m1\mathrm{A}2\mathrm{A}}{v}_{B,CM}+g_{mb1A,2\mathrm{A}}{v}_{i,CM}$$

(24)

Substituting (23) in (24),

$$i_{d1\mathrm{A},2\mathrm{A},CM}={\displaystyle \frac{g_{mb1A,2\mathrm{A}}}{1+2g_{m7\mathrm{A},8\mathrm{A}}{R}_{oB}}}\left[1+2R_{oB}\left(g_{m7\mathrm{A},8\mathrm{A}}-g_{m1\mathrm{A},2\mathrm{A}}{\displaystyle \frac{g_{mb7\mathrm{A},8\mathrm{A}}}{g_{mb1A,2\mathrm{A}}}}\right)\right]v_{i,CM}$$

(25)

As a result, $v_{o1,CM}=i_{d1\mathrm{A},2\mathrm{A},CM}{R}_{o1}{\epsilon }^{\prime }$, where ε’ is the M_3B–M_4B current mirror relative error. Remembering that $A_{DM}^{BD}(0)=g_{mb1\mathrm{a},2\mathrm{a}}{R}_{o1}$, the CMRR at DC is

$$CMR{R}^{BD}(0)={\displaystyle \frac{1+2g_{m7\mathrm{A},8\mathrm{A}}{R}_{oB}}{\left[1+2\left(g_{m7\mathrm{A},8\mathrm{A}}-g_{m1\mathrm{A},2\mathrm{A}}\frac{g_{mb7\mathrm{A},8\mathrm{A}}}{g_{mb1A,2\mathrm{A}}}\right)R_{oB}\right]{\epsilon }^{\prime }}}$$

(26)

Comparing (21) and (26), one important distinction lies in the denominator of (26), which contains the subtractive term (g_m7A,8A − (g_m1A,2A g_mb7A,8A/g_mb1A,2A)). If the auxiliary transistors (M₇–M₈) in Figure 3 are perfectly matched and proportionally scaled to the main input transistors (M₁–M₂) in Figure 3, this term cancels out. In this ideal scenario, the denominator reduces simply to ε’, whereas the numerator is dominated by 2g_m7A,8AR_oB. Since R_oB >> r_d7, the massive gain provided in the numerator is more than enough to compensate for the degradation introduced by the transconductance mismatch in the denominator. Therefore, despite the added sensitivity to mismatch between the auxiliary and main pairs, the BD OTA will exhibit a comparable or even greater DC CMRR to the GD OTA.

In a similar manner to (22), the BD OTA exhibits a strong correlation between CMRR (0) and PSRR (0), as any disturbance on the V_DD rail is processed by the circuit as a common-mode input.

In summary, the adopted SCCT structure and biasing sub-circuit are expected to yield competitive DC gain, PSRR, and CMRR for the BD OTA.

6. PVT and Corner Simulations

To enable a consistent performance comparison, the circuits shown in Figure 2 and Figure 3 were implemented using the same 180 nm CMOS technology from TSMC. Both designs employ two different “flavors” of transistors. Specifically, medium-threshold and standard-threshold n-channel (p-channel) MOSFETs, with V_TH0 values of 310 mV and 500 mV (−240 mV and −490 mV), respectively, were used for the cascode and common-source topologies in the SCCT structures.

The aspect ratios are optimized to achieve subthreshold saturation criteria of |V_DS| = 100 mV as summarized in Table 2, together with the bias current of 10 nA and voltage supply (V_DD) of 400 mV and 500 mv for BD and GD OTA, respectively.

Table 2. Transistor aspect ratios and main design settings.

BD OTA		GD OTA
Device	W/L (μm/μm)	Device	W/L (μm/μm)
M1A, M2A, M7A, M8A	11/1	M1A, M2A, M8A	11/1
M1B, M2B, M7B, M8B	1/1	M1B, M2B, M8B	1/1
M5A	22/1	M5A, M7	22/1
M5B	2/1	M5B	2/1
M3A, M4A, M10A	14/1	M3A, M4A	14/1
M3B, M4B, M10B	26/1	M3B, M4B	26/1
M6A, M9A	28/1	M6A	28/1
M6B, M9B	52/1	M6B	52/1
Settings
VDD	0.4 V	VDD	0.5 V
IB	10 nA	IB	10 nA
CC	600 fF	CC	1.8 pF

The main small-signal parameters (transconductances and resistances) are summarized in Table 3, and by utilizing these values, the very important comparison parameter η was extracted as ${\left({\displaystyle \frac{g_{mb1\mathrm{a},2\mathrm{a}}}{g_{m1\mathrm{a},2\mathrm{a}}}}\right)}_{\mathrm{B}\mathrm{D}}={\displaystyle \frac{105.8 \mathrm{n}\mathrm{S}}{276.2 \mathrm{n}\mathrm{S}}}=0.38$ and ${\left({\displaystyle \frac{g_{mb1\mathrm{a},2\mathrm{a}}}{g_{m1\mathrm{a},2\mathrm{a}}}}\right)}_{\mathrm{G}\mathrm{D}}={\displaystyle \frac{101.1 \mathrm{n}\mathrm{S}}{264.2 \mathrm{n}\mathrm{S}}}=0.38$. To achieve a similar PM for fair comparison, the C_C required is different, as shown in Table 2. Observe that the C_C’s ratio is not exactly η, in order to take into account second order effects (e.g., different output resistance values between GD and BD OTAs and the neglected second poles) and to achieve a similar phase margin in both OTAs.

Table 3. Small-signal parameters in nominal condition.

BD OTA		GD OTA
Parameter	Value	Parameter	Value
Gm1 (gmb1a,2a) (nS)	105.8	Gm1 (gm1a,2a) (nS)	264.2
gm1a,2a	276.2	gmb1a,2a	101.1
Gm2 (gm6b) (nS)	614	Gm2 (gm6b) (nS)	591
gm2b (nS)	291	gm2b (nS)	274.9
Ro1 (GΩ)	6	Ro1 (GΩ)	6.4
Ro2 (GΩ)	3	Ro2 (GΩ)	4.8

In [15], the bulk-driven OTA solution was experimentally validated across all process corners. This was one of the most comprehensive characterizations of BD OTAs in the literature and showed a very good agreement with pre- and post-layout simulations, indicating that the effects of layout parasitics and mismatch were limited for the fabricated BD OTA. Due to the lack of experimental data for the GD counterpart, we base the present comparison on pre-layout simulation results for both designs.

Figure 4 illustrates the frequency response (magnitude and phase) of both the GD and BD designs, showing a DC gain of 136.3 dB and 124.7 dB, respectively. While the GD design exhibits superior gain (+12 dB, compared to the theoretical 20 log(1/η) = 8.4 dB), both architectures achieve, as expected, a comparable Gain–Bandwidth Product (GBW) through a deliberate design trade-off. This results in nearly superimposed roll-off characteristics, as the higher DC gain of the GD design is balanced by the higher dominant pole frequency of the BD design. However, a slight discrepancy is observed in the unity-gain frequency (UGF), with the GD achieving 30.9 kHz compared to 19.35 kHz for the BD. This difference is primarily attributed to the peaking effect near the UGF in the GD response, which extends its crossover point despite the matching of the sub-Hertz slopes. This peaking stems from complex-conjugate poles, as evidenced by the steeper phase variation in the GD above the UGF. Consequently, the GD topology is inherently more challenging to compensate due to the presence of these poles, which are absent in the BD topology. The GBW of both the topologies is well suited for low-frequency application, specifically for biomedical signals, which range from mHz to a maximum of 10 kHz [27]. Therefore, the proposed OTAs provide a sufficient bandwidth margin for biopotential acquisition systems such as ECG, EEG, and EMG front-ends, while maintaining ultra-low-power consumption. Figure 4b illustrates that the phase margin is 43.19° and 44° for BD and GD, respectively. This lower phase margin represents an acceptable trade-off between stability and bandwidth under ULV/ULP regimes. Because of the inherently lower g_mb, increasing the PM would require a larger C_C, severely penalizing the GBW and slew rate. Finally, as reported in [15], this PM parameter exhibits high stability against PVT variations.

Figure 4. Frequency response of GD and BD OTAs: (a) magnitude and (b) phase.

Figure 5 presents the magnitude of CMRR and PSRR versus frequency. The BD design achieves a higher CMRR (0) of 115 dB compared to 106 dB for the GD design, maintaining superior rejection across the entire frequency range. In contrast, the GD design exhibits a marginally higher PSRR (0) of 107 dB over the BD’s 104.5 dB. The primary advantage of the GD architecture, however, lies in its superior frequency response, as it provides a much wider PSRR bandwidth, providing, for example, a rejection level of 50 dB even at frequencies (10 kHz) where the BD response has already significantly deteriorated.

Figure 5. CMRR and PSRR magnitude versus frequency of GD and BD OTAs.

Figure 6a illustrates the small-signal step response for a 20 mV peak-to-peak input. Positive/negative 1% settling time is 95.47/79.83 (µs) for the BD OTA and 112.9/98.37 (µs) for the GD OTA. Figure 6b displays the large-signal step response for a 300 mV peak-to-peak input. Under the same quiescent current, the BD design achieves a significantly higher slew rate, as evidenced by the steeper slope and faster settling time. This enhanced speed is a direct result of the smaller C_C required for BD architecture.

Figure 6. (a) Small-step response and (b) large-step response of GD and BD.

The effect of the intrinsically lower g_mb is reflected in the increased flicker and thermal noise for the BD OTA, as seen in Table 4. Interestingly, the ratio between the flicker noise of GD and BD designs (96.4/36.7 = 2.6) is approximately equal to that of the white noise ratio (1.45/0.56 = 2.6) among them. Furthermore, this ratio is approximately equal to 1/η = 2.6.

Table 4. OTA noise performance comparison.

Parameter	GD	BD
Flicker Noise @10 mHz$\left(\mathsf{\mu }\mathrm{V}/\sqrt{\mathrm{H}\mathrm{z}}\right)$	36.7	96.4
White Noise @ 1 kHz $\left(\mathsf{\mu }\mathrm{V}/\sqrt{\mathrm{H}\mathrm{z}}\right)$	0.56	1.45
Corner Frequency (Hz) (1.4 × White Noise @ 1 kHz)	35.9	36.7
Integrated Noise Summary (μV) in the Range 0.5 mHz to 70 kHz
Total Summarized Noise	189.7	303
Total Input Referred Noise	125.7	403.4

Table 5 summarizes the performance metrics of both topologies, clearly reflecting the trends discussed in Section 5 under the process corners. The considerably larger intrinsic gate transconductance provides a GD architecture with higher DC gain and lower noise. Also, offset is lower in the GD OTA. Conversely, the lower C_C required to achieve the same PM results in better SR and settling time for BD architecture. While PSRR (0) values are similar, the BD architecture shows superior CMRR (0). Nonetheless, both topologies demonstrate robust performance, resulting in low sensitivity in all the process corners.

Table 5. OTA performance under process corner variation at 27 °C.

Parameters	TT		FF		FS		SS		SF
	GD	BD	GD	BD	GD	BD	GD	BD	GD	BD
DC Gain (dB)	136.3	124.7	132	124.7	133.4	121.9	136.5	123	128.8	122.9
GBW (kHz)	30.9	19.35	30.4	19.55	31.5	19.95	31.4	18.95	23.12	18.83
PM (deg)	44	43.19	43.5	43.19	42.1	42.2	44.2	48.93	51.2	43.36
Offset (μV)	0.5	1.7	0.9	2.6	0.6	2.2	0.4	2.1	1.4	2.1
tset1%+/tset1%− (μs)	112.9/ 98.37	95.47/ 79.8	112.6/ 99.2	121.8/ 105.2	124.2/ 114.2	94.59/ 78.2	125.4/ 98	91.89/ 59	80.2/ 65.6	98.85/ 83.1
SR+/SR− (V/ms)	1.3/ 16	1.98/ 26.1	1.2/ 16.9	1.98/ 26.1	1.28/ 21.1	1.98/ 23.7	1.27/ 14.5	1.98/ 22	1.25/ 11.8	1.98/ 25.4
CMRR (0) (dB)	106	115.3	104.3	115.3	102.7	110.5	102.2	128.7	84.5	106.7
PSRR (0) (dB)	107	104.5	105.7	104.5	100.3	131.4	101.8	89.04	101.5	86.8
IRN a @ 1 kHz $\left(\mathsf{\mu }\mathrm{V}/\sqrt{\mathrm{H}\mathrm{z}}\right)$	0.56	1.45	0.55	1.46	0.57	1.43	0.57	1.44	0.56	1.47

^a: input-referred noise.

The impact of process mismatches is summarized in Table 6, based on 1000-iteration Monte Carlo simulations. Both architectures exhibit comparable standard deviation values. Meanwhile, Figure 7 illustrates the histogram for gain, GBW and CMRR of both BD and GD topologies, clearly reflecting the results of Table 6.

Table 6. OTA performance under Monte Carlo simulation results at 27 °C.

Parameters	Mean		Std. Dev
	GD	BD	GD	BD
DC Gain (dB)	134.9	122.7	4.6	6.2
GBW (kHz)	30.6	19.24	1.8	0.6
PM (deg)	44.13	43.01	2.7	2.1
Offset (μV)	−3.5	−7.9	1635	4166
tset1%+/tset1%− (μs)	115.5/98.0	101.2/79.5	7.9/15.5	13.1/10.4
SR+/SR− (V/ms)	1.3/16.1	7.98/25.81	0.04/2.5	0.07/2.4
CMRR (0) (dB)	92.9	91.29	9.4	12.1
PSRR (0) (dB)	107.2	79.75	9.6	12.9
IRN @ 1 kHz $\left(\mathsf{\mu }\mathrm{V}/\sqrt{\mathrm{H}\mathrm{z}}\right)$	0.56	1.45	0.005	0.02

Figure 7. Histogram from 1000 Monte Carlo simulations for gain, GBW and CMRR of BD and GD at 27 °C.

Table 7 illustrates the performance summary of both GD and BD OTAs under temperature variations. It is seen that the GD architecture maintains superior DC gain and GBW across all temperatures, despite a common performance degradation at 80 °C. Conversely, the BD architecture excels in large-signal metrics, delivering faster settling times and higher slew rates. Both designs exhibit stable phase margins, ensuring consistent frequency compensation. Notably, BD architecture demonstrates significantly better CMRR at high temperatures compared to the GD counterpart.

Table 7. OTA performance under temperature variations and TT corner.

Parameters	T = 0 °C		T = 27 °C		T = 80 °C
	GD	BD	GD	BD	GD	BD
DC Gain (dB)	139.9	125.3	136.3	124.7	109.7	97.04
GBW (kHz)	34.03	20.55	30.9	19.35	24.4	16.08
PM (deg)	43.38	43.1	44	43.19	46.8	43.97
Offset (μV)	0.3	2	0.5	1.7	11.8	22
tset1%+/tset1%− (μs)	118.6/91.3	92.1/76.6	112.9/98.4	95.5/79.8	112.1/101.2	111/95.0
SR+/SR− (V/ms)	1.3/14.5	2.1/26.9	1.3/16	1.98/26.1	1.2/17.5	1.9/17.9
CMRR(0) (dB)	104	103.1	106	115.3	88.7	135.1
PSRR(0) (dB)	104	84.59	107	104.5	87.9	78.9
IRN @ 1 kHz $\left(\mathsf{\mu }\mathrm{V}/\sqrt{\mathrm{H}\mathrm{z}}\right)$	0.52	1.35	0.56	1.45	0.65	1.64

Table 8 illustrates the performance of both the GD and BD OTAs under a supply variation of V_DD ± 50 mV. Both designs respond conventionally to supply voltage variations. However, the BD architecture sensitivity is comparably higher than GD due to the reliance of bulk transconductance being strongly affected by bias and substrate conditions.

Table 8. OTA performance under supply voltage variations and TT corner at 27 °C.

Parameters	GD			BD
VDD (mV)	450	500	550	350	400	450
DC Gain (dB)	135.7	136.3	136.5	102.7	124.7	125
GBW (kHz)	30.5	30.9	31.1	16.9	19.35	19.8
PM (deg)	45.1	44	43.7	41.1	43.19	42.7
Offset (μV)	−0.2	0.5	0.7	5.8	1.7	1.7
tset1%+/tset1%− (μs)	114.3/99.1	112.9/98.37	112.8/98.2	135.4/96.6	95.47/79.83	94.14/77.43
SR+/SR− (V/ms)	1.3/13.01	1.3/16	1.3/17.9	1.9/23.7	1.98/26.1	2/18.5
CMRR (0) (dB)	90.3	106	108.1	89.2	115.3	107.8
PSRR (0) (dB)	88.4	107	111.7	71.2	104.5	115.4
IRN @ 1 kHz $\left(\mathsf{\mu }\mathrm{V}/\sqrt{\mathrm{H}\mathrm{z}}\right)$	0.58	0.56	0.56	1.48	1.45	1.42

Table 9 shows the performance of both the GD and BD architectures against input common-mode (ICM) voltage variations. The results clearly demonstrate the near-rail-to-rail behavior of the BD architecture. The BD OTA maintains acceptable performance levels even when the input common-mode voltage approaches the positive and lower supply rails, whereas the GD OTA performance deteriorates significantly under the same conditions. Nevertheless, the GD topology still exhibits a wider operating range compared to conventional strong inversion operation.

Table 9. Performance against input common-mode value TT corner and at 27 °C.

ICM (mV)	DC Gain (dB)		GBW (kHz)		PM (deg)		SR+/SR− (V/ms)		tset1%+/tset1%− (μs)
	GD	BD	GD	BD	GD	BD	GD	BD	GD	BD
10	5.7	40.3	5.6	13.1	101.3	72.4	1.2/7.8	1.8/45.6	127.6/35.4	76.7/104.4
50	54	71.2	11.8	19.9	26.2	44.7	1.2/9.4	1.8/39.5	264.2/233.6	91.2/57.9
100	86	94.8	15.2	19.9	36.3	43.1	1.2/11.4	1.9/33.2	126.4/151.2	92.9/77.8
200	136.3	124.7	30.9	19.35	44	43.19	1.3/16	1.98/26.1	112.9/98.37	95.5/79.8
300	132.8	97.3	30.72	18.5	45.2	44	1.3/19.4	2.01/23	132.4/114.6	99.3/83.7
350	115.1	74.6	27.9	17.4	36.7	44.9	0.9/18.1	2.04/18.7	218.7/164.1	107.7/85.8
390	105.7	44.3	21.7	9.3	16.4	53.3	1.2/24.2	2/15.1	577.7335.9	128.6/95.6

Table 10 presents the state-of-the-art comparison of recently reported ULV/ULP OTAs. The area of the GD circuit presented in this manuscript is estimated based on the implemented BD circuit by considering both the reduction in area due to the smaller number of transistors and the increase in area caused by the larger compensation capacitor. The comparison provides a clear overview of the relative performance of the proposed architectures with respect to existing BD and GD designs. Both OTAs discussed in this manuscript achieve high DC gain, CMRR, and PSRR under ultra-low-voltage operation. Furthermore, among the two proposed architectures, the BD OTA achieves a higher FoM_L due to its faster slew rate, whereas the GD OTA achieves a higher FoM_S owing to its larger GBW.

Table 10. State-of-the-art ULV/ULP OTAs.

Parameters	This Work		[28] a	[29] a	[30] a	[31] c	[32] a	[33] a	[13] a	[34] a
	BD [15] a	GD c	BD	BD	BD	BD	BD	BD	BD	GD
Year	2024	2025	2026	2022	2022	2021	2025	2023	2024	2016
# of stages	2	2	1	2	1	1	2	3	3	2
Technology (nm)	180	180	180	180	180	180	180	130	65	180
Area (µm2)	3864	3600 b	2400	7900	11,530	8800	3300	2340	52,000	18,200
VDD	0.4	0.5	0.4	0.4	0.5	0.5	0.4	0.3	0.35	0.5
Power (nW)	24 a	30	1.9	24	24.8	160.8	39.1	33.7 c	490	70
DC Gain (dB)	124.7	136.3	74.7	60	26.5	31.2	75.2	86.8	55	77
GBW (kHz)	19.35 (18.1 a)	30.9	1.6	7	0.225	0.212	35.2	10.32	15.4	4
CL (pF)	15	15	1	15 d	20	20	20 d	35	300	40
PM (°)	44 (43.3 a)	43.2	89.1	60	89	88.5	65	58.3	65	56
SRav (V/ms)	14.04 (12.7 a)	8.65	1.02	79	-	-	40.2	3.74	17.9	2
Output voltage swing (%)	97 a	70	85	-	-	-	-	73		-
PSRR (dB)	104.5 (52.3 @ 50 Hz) a	107	42.5	76.3	52	37.26	101	46.59 c	26.5	52
CMRR (dB)	115.3	106	44.5	85.4	84	90.07	117	57.8 c	58	55
IRN (µV/Hz1/2) @ 1 kHz	1.45 c	0.56	4.6 c	0.31 c	5.32 c	-	0.61	2.86 @ 10 kHz c	0.83 c	-
Offset (mV)	0.0017 (−1.4) a	0.0005	4.5	2.4	-	-	-	-	6.4	−4.8 e
FOMS (kHz×pF/nW)	12.1	15.5	0.8	4.4	0.2	0.03	18	10.7	9.4	2.3
FOML ((V×pF)/(ms×nW))	8.8	4.3	0.5	49.4	-	-	20.6	3.9	11	1.14

^a: measured; ^b: estimated; ^c: simulated; ^d: single-ended; ^e: avg. of four samples.

7. Conclusions

This work presented a comprehensive, head-to-head comparison between gate-driven (GD) and bulk-driven (BD) operational transconductance amplifiers operating in the deep-subthreshold, ultra-low-voltage (ULV) and ultra-low-power (ULP) regimes. By leveraging the self-cascode composite transistor (SCCT) structure under identical biasing conditions, a rigorous and fair evaluation framework was established.

This paper addresses common misconceptions surrounding BD designs, offering a more nuanced understanding of the true strengths and limitations of two-stage BD OTAs. Theoretical analysis and extensive simulations demonstrate that, while the inherently higher gate transconductance (g_m) of the GD OTA ensures superior small-signal performance, specifically in terms of DC gain, the BD architecture presents notable advantages for ULV analog design. Most prominently, the BD approach enables a true rail-to-rail input common-mode range without the structural complexity of complementary input pairs. Furthermore, the BD OTA excels in large-signal transient metrics; the improved slew rate and faster settling times stem directly from the lower compensation capacitance for the same GBW. Alongside these dynamic benefits, the BD OTA can also achieve comparable CMRR and PSRR performance.

However, the inherently lower bulk transconductance (g_mb) makes noise a persistent challenge for BD topologies, resulting in a distinct degradation of both thermal and flicker noise profiles. Ultimately, the analysis confirms that there is no universally optimal architecture. From a practical design perspective, the choice between GD and BD topologies hinges on strict, application-specific design priorities. GD architecture is more suitable for applications requiring higher gain, lower input-referred noise, and wider bandwidth. BD architectures, on the other hand, are preferable for ultra-low-voltage systems demanding rail-to-rail input operation and improved large-signal transient behavior. Therefore, the selection of either topology should primarily depend on the target supply voltage, noise constraints, bandwidth requirements, and input signal range of the intended application.