Feature Papers of Chips

A special issue of Chips (ISSN 2674-0729).

Deadline for manuscript submissions: 31 March 2027 | Viewed by 701

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Guest Editor
Dipartimento di Ingegneria Elettrica Elettronica e Informatica, Università di Catania, I-95125 Catania, Italy
Interests: low-power electronics; cmos integrated circuits; operational amplifiers; integrated circuit design; cmos logic circuits; cmos analogue integrated circuits
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Guest Editor
Department of Electrical Engineering and Centre for Intelligent Multidimensional Data Analysis, City University of Hong Kong, Hong Kong
Interests: high-performance & customisable biomedical and bioinformatics computing; AIoT designs; reconfigurable trusted computing; VLSI/FPGA circuit designs; cryptography; system-on-chip architecture; embedded system designs

Special Issue Information

Dear Colleagues,

Integrated electronics represents a continuously expanding market facing constantly evolving challenges. The purpose of this Special Issue is to publish a set of original, cutting-edge research papers, as well as in-depth reviews of the state of the art for microelectronics in emerging groundbreaking and challenging technologies.

We expect these papers to be widely read and influential within the field.

Topics of interest include, but are not limited to, the following:

  • Analog, digital, and mixed circuits and systems;
  • RF circuits and systems;
  • Integrated optoelectronics and photonics;
  • Power integrated circuits and integrated power management;
  • >Design of integrated flexible electronics;
  • Cry-CMOS;
  • Testing of chips;
  • Quantum computing;
  • Integrated circuits and systems for AI.

Prof. Dr. Gaetano Palumbo
Prof. Dr. Ray C. C. Cheung
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 250 words) can be sent to the Editorial Office for assessment.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-anonymized peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Chips is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1000 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • analog, digital, and mixed circuits and systems
  • RF circuits and systems
  • integrated optoelectronics and photonics
  • power integrated circuits and integrated power management
  • design of integrated flexible electronics
  • Cry-CMOS
  • testing of chips
  • quantum computing
  • integrated circuits and systems for AI

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Further information on MDPI's Special Issue policies can be found here.

Published Papers (2 papers)

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Research

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21 pages, 4346 KB  
Article
Bulk-Driven vs. Gate-Driven OTAs in Deep-Subthreshold ULV Operation: Analytical and Robustness Comparison in Self-Cascode Architectures
by Salvatore Pennisi, Marco Privitera and Muhammad Omer Shah
Chips 2026, 5(2), 14; https://doi.org/10.3390/chips5020014 - 14 Jun 2026
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Abstract
This work presents a comprehensive analytical and simulation-based comparison between bulk-driven (BD) and gate-driven (GD) operational transconductance amplifiers (OTAs) operating in the deep-subthreshold ultra-low-voltage regime. While BD techniques are traditionally considered unsuitable for high-performance analog design due to their lower transconductance efficiency, this [...] Read more.
This work presents a comprehensive analytical and simulation-based comparison between bulk-driven (BD) and gate-driven (GD) operational transconductance amplifiers (OTAs) operating in the deep-subthreshold ultra-low-voltage regime. While BD techniques are traditionally considered unsuitable for high-performance analog design due to their lower transconductance efficiency, this study demonstrates that, when combined with self-cascode structures, BD architectures achieve competitive intrinsic gain, enhanced input common-mode range, and improved slew rate efficiency under nanoampere bias conditions. To support these claims, closed-form analytical derivations, dynamic analysis, and comprehensive Monte Carlo and PVT simulations are provided to quantify robustness and mismatch sensitivity. The results establish a systematic framework for evaluating BD versus GD architectures under identical technology and power constraints, offering practical design guidelines and optimized self-cascoded topologies for next-generation energy-autonomous systems. Full article
(This article belongs to the Special Issue Feature Papers of Chips)
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55 pages, 32580 KB  
Tutorial
DIGOTA Tutorial: Current State of the Art and Future Perspectives
by Tiago Barrocas, Alexandra Matos, Pedro Toledo, Miguel Coelho, Francisco Janeiro, Luciano Radrigan, Miguel Durán, Bruno Marques, Pedro Zanetta, Jorge Fernandes and João Vaz
Chips 2026, 5(2), 15; https://doi.org/10.3390/chips5020015 (registering DOI) - 15 Jun 2026
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Abstract
DIGOTA architectures have attracted growing interest as a means of addressing the problems that arose with the extreme miniaturization of the MOS transistor in analog design. Despite the increasing number of proposed architectures, the literature remains fragmented, with differences in design goals, structural [...] Read more.
DIGOTA architectures have attracted growing interest as a means of addressing the problems that arose with the extreme miniaturization of the MOS transistor in analog design. Despite the increasing number of proposed architectures, the literature remains fragmented, with differences in design goals, structural choices, and evaluation criteria that make direct comparison difficult. This paper presents a comprehensive survey of DIGOTA architectures reported in the literature so far. This review study is organized according to key architectural characteristics, including biomedical applications, flexible electronics, and low-power amplifiers. Based on this analysis, the paper discusses major trends, common trade-offs, strengths, and limitations across current approaches. The survey also identifies open issues and promising directions for future research. By providing a structured overview of the field, this work serves as a useful reference for researchers seeking to understand, compare, and develop DIGOTA architectures. Full article
(This article belongs to the Special Issue Feature Papers of Chips)
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