Adaptive Virtual-Reactance-Based Fault-Current Limiting Method for Grid-Forming Converters in EV Charging Stations

Abstract

To satisfy the requirements of voltage support and fault-current limitation for electric-vehicle (EV) charging stations connected to weak distribution networks, an increasing number of charging infrastructures are adopting grid-forming (GFM) converters and vehicle-to-grid (V2G) control strategies. Under AC short-circuit faults and voltage-sag conditions, limiting the fault current injected by the converter is essential to reduce overcurrent risk to power semiconductor devices. For this, an adaptive virtual-impedance-based low-voltage ride-through (LVRT) method is proposed for GFM converters in EV charging stations. First, an overcurrent grading criterion is constructed based on real-time current measurements. In the moderate-overcurrent region, an adaptive virtual reactance is introduced to achieve soft current limiting. In the severe-overcurrent region, hard current limiting is implemented by further increasing the virtual reactance and blocking overcurrent bridge arm. In addition, a virtual-reactance recovery mechanism is designed to ensure smooth post-fault restoration. Based on an RCP + HIL platform, experiments are conducted to validate the proposed fault current-limiting method. Experiment results demonstrate that the proposed method can rapidly suppress fault current, maintain voltage-support capability, and shorten post-fault restoration time.

1. Introduction

In recent years, the rapid growth in electric-vehicle (EV) adoption has accelerated the deployment of high-power charging stations in industrial parks, transportation hubs, and highway service areas [1,2]. Compared with conventional dispersed loads, high-power charging stations are characterized by high power density and diverse operating modes. Their points of connection are often located at the end of feeders or at buses with limited short-circuit capacity, which may aggravate voltage fluctuations, weaken transient voltage support, and complicate protection coordination [3,4]. To address these issues, in the coordinated “charging station–energy storage–vehicle” scenario, upgrading the grid-connected converters in charging stations from grid-following (GFL) control to grid-forming (GFM) control can provide reactive power–voltage support under weak-grid conditions.

However, short-circuit faults or voltage sags in distribution networks may cause a sharp rise in the grid current of GFM converters, posing a serious threat to equipment safety [5]. In low short-circuit ratio (SCR) scenarios, the increased equivalent grid impedance further intensifies the coupling between the voltage-support behavior of GFM converters and the line impedance, leading to more severe change in current during faults [6,7]. Overcurrent conditions not only increase the thermal stress of power semiconductor devices, but may also induce dc-link voltage fluctuations, ac-side voltage distortion, and even control instability. Therefore, achieving fast and adaptive current limiting for GFM converters during faults has become one of the key challenges in both engineering practice and theoretical research.

To cope with overcurrent control and current-limiting requirements in grid-connected converters, a variety of approaches have been reported in the literature. Current limiting based on dq-axis current magnitude saturation and active/reactive power priority reallocation constrains the output current by adjusting the current references; however, under severe faults and low-SCR conditions, voltage-support capability is often compromised [8,9]. Virtual-impedance or virtual-reactance-based methods introduce a fixed virtual impedance into the inner current loop to emulate the current-limiting effect of series reactors [10,11]. Nevertheless, an excessively large virtual impedance can significantly reduce the bandwidth of the inner current loop and deteriorate dynamic damping, while parameter tuning is largely empirical. In addition, voltage- and power-saturation mechanisms have been incorporated into grid-forming virtual synchronous generator (VSG) control to indirectly suppress fault currents by limiting the output voltage and power [12]. However, the impacts of SCR variations and the coupling between inner and outer loops are not sufficiently addressed, and the adaptability under multiple operating conditions remains limited. The strategy in [13], which improved the outer active and reactive control by current limiting, may lead to a long post-fault restoration time, whereas the method in [14] also cause a slower rate of current decrease during the recovery process. Overall, existing methods either require the relative balance between current-limiting capability and grid-support performance, or lack a quantitative analysis of the relationship between virtual-impedance parameters and control stability [15,16,17,18,19], and further improvements are still needed to enhance the robustness of GFM converter under weak-grid and complex fault scenarios.

Compared with existing current-limiting methods for grid-forming (GFM) converters, the proposed adaptive-virtual-reactance-based segmented strategy achieves effective fault-current limiting with fast post-fault recovery and improved robustness under complex fault scenarios.

Therefore, the remainder of this paper is organized as follows:

Section I introduces the topology of the grid-forming converter for high-power EV charging stations and the baseline VSG (GFM) control structure.

Section II presents the control scheme with the embedded virtual reactance loop, and formulates the corresponding control equations/modeling basis for subsequent analysis and design.

Section III proposes an adaptive virtual-reactance-based piecewise current-limiting LVRT strategy, including fault/overcurrent grading, soft limiting in the moderate-overcurrent region, and hard limiting in the deep-overcurrent region (with auxiliary gate blocking logic).

Section IV establishes the EMT simulation model (StarSim-RCP + StarSim-HIL platform) and verifies the effectiveness of the proposed strategy under typical fault scenarios.

2. Topology and Control Scheme of the Grid-Forming Converter

The topology of the grid-forming converter (GFM) grid-connected system is shown in Figure 1. Each bridge leg consists of two switching devices. The converter generates a two-level output voltage, which is connected to the grid through an LC filter. In Figure 1, u_A, u_B, u_C, i_A, i_B, i_C, denote the phase voltages and phase currents at the point of common coupling (PCC), respectively; L and C are the filter inductance and capacitance; e_A, e_B, e_C are the grid phase voltages; L_e is the line inductance; and U_dc is the dc-side input voltage of the GFM converter. The three-phase PCC voltages u_A, u_B, u_C and currents i_A, i_B, i_C are transformed into the synchronous rotating reference frame to obtain the voltage components u_gd, u_gq and current components i_gd, i_gq, which are then fed into the power calculation module to derive the converter output active power P_e and reactive power Q_e Based on the power feedback and the corresponding setpoints, the VSG control loop generates the virtual machine terminal voltage and phase angle, and further provides the current references idref and iqref. The inner current loop performs fast tracking regulation to produce the voltage control commands. Subsequently, a virtual-reactance loop is introduced, where an equivalent reactance voltage drop is superimposed on the voltage reference to enhance damping, improve adaptability to weak grids, and suppress fault-induced inrush currents. Finally, the modified U_gdref and U_gqref are transformed back to generate the three-phase reference voltages U_iref (i represent A phase, B phase, C phase), which are used for PWM modulation to drive the switching devices of the converter. The system parameters are listed in Appendix A.

Figure 1. The grid-forming converter system: (a) Electrical Topology of the VSG Converter, (b) Control Structure of the VSG.

In Figure 1, abc denotes the three-phase stationary reference frame, and dq0 denotes the synchronous rotating dq0 reference frame.

3. Control Scheme with a Virtual-Reactance Loop

The VSG control consists of an active-power control loop, a reactive-power/voltage control loop, a virtual-reactance loop, and an inner current loop. Specifically, the active-power control loop generates the frequency deviation Δω based on the error between the active-power reference P_ref and the measured active power P_g through the VSG dynamic block. The resulting Δω is added to the nominal angular frequency ω₀ and then integrated to obtain the virtual voltage angle θ_v, thereby emulating the P–f characteristic and inertia support of a synchronous machine. The reactive-power control loop takes the deviation between the PCC voltage U_g and its reference as the input. Through the Q–U droop and reactive-power regulation, together with the reactive-power setpoint Q_ref, the reactive-power command Q* is obtained. By comparing Q* with the measured reactive power Q_e, the voltage magnitude adjustment is produced and superimposed on the virtual electromotive force E_v, which realizes the Q–U droop behavior and voltage support. On this basis, the inner current loop employs the errors between the current references i_dref, i_qref provided by the virtual-reactance loop and the measured currents i_gd, i_gq to generate the dq voltage references U_gdref, U_gqref via PI regulation, cross-coupling decoupling, and voltage feedforward. The resulting dq-axis voltage references are then transformed back to produce the three-phase modulation signals U_iref (i represent A phase, B phase, C phase), which are applied to the PWM modulator to drive the switching devices and generate the two-level output voltages.

As shown in Figure 2, the active-power control loop of the VSG can be expressed by Equation (1):

$${\displaystyle \frac{{\mathrm{P}}_{\mathrm{ref}}}{{\omega }_0}}-{\displaystyle \frac{{\mathrm{P}}_{\mathrm{e}}}{{\omega }_0}}-D_0(\omega -{\omega }_0)=J_0{\displaystyle \frac{d\omega }{dt}}$$

(1)

Figure 2. Control scheme of the grid-forming converter.

In the above equation, J₀ denotes the virtual inertia of the VSG, and D₀ denotes the damping coefficient.

For the VSG with constant ac-voltage control, the active-power control loop can be expressed by Equation (2):

$$\left\{\begin{array}{l}{Q}^{*}=Q_{ref}+K_{\mathrm{u}}(U_0-U_{\mathrm{g}})\\ {\displaystyle \frac{d(E_{\mathrm{v}}-U_0)}{dt}}=K_0(Q^{*}-Q_{\mathrm{e}})\end{array}\right.$$

(2)

In the above equation, K_u denotes the voltage droop coefficient, and K₀ denotes the integral gain.

The virtual-reactance control loop with internal electromotive-force droop can be expressed by Equation (3):

$$\left\{\begin{array}{l}0-u_{\mathrm{gq}}=-i_{\mathrm{dref}}{\omega }_0{L}_{\mathrm{v}}\\ E_{\mathrm{v}}-u_{\mathrm{gd}}=i_{\mathrm{qref}}{\omega }_0{L}_{\mathrm{v}}\end{array}\right.$$

(3)

4. Current-Limiting Strategy Based on Adaptive Virtual Reactance

4.1. Fault Detection Criterion

Based on the control framework of the grid-forming converter, an adaptive virtual-reactance-based segmented current-limiting strategy driven by current measurements is proposed. During a fault, the proposed strategy adaptively adjusts the virtual reactance according to the severity of the output current exceeding its limit, thereby enabling coordinated soft current limiting in the moderate overcurrent region and hard current limiting in the severe overcurrent region. After fault clearance, a virtual-reactance recovery mechanism is employed to restore the converter to its steady-state operating point.

To implement the segmented current-limiting control, it is first necessary to establish a current-measurement-driven fault criterion and an overcurrent grading logic. In the synchronous rotating dq reference frame, the magnitude of the converter output current is defined as:

$$I_m(t)=\sqrt{i_{gd}^2(t)+i_{gq}^2(t)}$$

(4)

To distinguish different levels of overcurrent severity, the rated current is denoted by I_n, and the maximum allowable current is set to I_M = 2I_n. A moderate-overcurrent threshold I_th1 = 1.5I_n is defined between them. Accordingly, the output-current grading logic is given as:

$$S_I(t)=\left\{\begin{array}{l}0,\hspace{1em}\hspace{1em}{I}_m(t)\le I_{\mathrm{th}1}\\ 1,\hspace{1em}{I}_{\mathrm{th}1}<I_m(t)\le I_M \\ 2,\hspace{1em}\hspace{1em}{I}_m(t)>I_M\end{array}\right.$$

(5)

where S_I = 0 indicates that the current does not exceed the limit, S_I = 1 corresponds to the moderate overcurrent region, and S_I = 2 indicates that the converter has entered the severe overcurrent region, in which a strong current-limiting action is required. After fault clearance, a recovery criterion is introduced to restore the virtual reactance to its steady-state base value. Let the current recovery threshold be I_rec ≈ 1.05I_n [10,14]; then, the virtual-reactance recovery criterion is given as:

$$S_C(t)=\left\{\begin{array}{c}1,\hspace{1em}\hspace{1em}{I}_m(t)>I_{\mathrm{rec}}\\ 0,\hspace{1em}\hspace{1em}{I}_m(t)\le I_{\mathrm{rec}}\end{array}\right.$$

(6)

where S_c = 1 indicates that the post-fault condition has not yet recovered, whereas S_c = 0 indicates that the system has basically returned to a near-rated operating condition, and thus the virtual-reactance recovery process can be initiated.

4.2. Construction of the Current-Limiting Strategy

Under the VSG control scheme, a series virtual reactance is introduced to realize fault current limiting and damping enhancement. Its equivalent expression in the synchronous dq reference frame is given by:

$$Z_v\text{}(t)=j{X}_v\text{}(t)$$

(7)

where X_v(t) denotes the virtual resistance and virtual reactance. Under steady-state fault-free operation, the initial value of the virtual reactance is calculated from the rated grid voltage U_n and the rated apparent power S_n of the converter according to Equation (8) [20].

$$X_0=0.1{\displaystyle \frac{3U_n^2}{S_n}}\text{}$$

(8)

(1). When SI = 1, the system operates under a voltage sag with moderate overcurrent. In this case, a drastic increase in the virtual reactance may compromise the closed-loop stability of the inner current loop. Therefore, while keeping the virtual resistance unchanged, the virtual reactance is increased to achieve a soft limitation on the current rising rate and peak value. The current exceedance is defined as:

$$\Delta I(t)=I_m\text{}(t)-I_{th1}\text{}$$

(9)

When ΔI(t) ≤ 0, the current does not exceed the moderate overcurrent threshold and no additional current limiting is required. When ΔI(t) > 0, the increment of the virtual reactance is ΔXAVR(t) determined by the following nonlinear adaptive law:

$$\Delta X_{\mathrm{AVR}}(t)=\left\{\begin{array}{l}0,\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em} \Delta I(t)\le 0 \\ k_{x1}\Delta I(t)+k_{x2}\left(1-e^{-\gamma \Delta I(t)}\right),\hspace{1em}\Delta I(t)>0\end{array}\right.\text{}$$

(10)

where k_x1 > 0 is the linear gain that determines the sensitivity of the virtual reactance to the current exceedance; k_x2 > 0 and γ > 0 regulate the saturation level and variation rate of the exponential term, which smooths the virtual-reactance variation and avoids abrupt disturbances to the inner current loop.

The virtual reactance in the moderate overcurrent region is expressed as:

$$X_v\text{}(t)=X_0\text{}+\Delta X_{AVR}\text{}(t),\hspace{1em} S_I\text{}=1$$

(11)

(2). When S_I = 2, the system enters the severe overcurrent region, and the output current has exceeded the maximum allowable value I_M. In this case, the virtual-reactance-based soft current limiting is insufficient to constrain the current within a safe range, and an adaptive equivalent virtual-reactance calculation based on the voltage vector is required so that the fault current magnitude can be hard-limited around I_M. During the fault, the current-driving force through the virtual reactance is determined by the difference between the converter internal emf and the minimum value of the PCC three-phase voltage, denoted as U_samp. The required magnitude of the equivalent reactance should satisfy:

$$X_{REQ}(t)={\displaystyle \frac{\left|\left|E_v(t)\right|-U_{\mathrm{samp}}(t)\right|}{I_M}}\text{}$$

(12)

Since an adaptive virtual-reactance term ΔX_AVR(t) has been introduced in the moderate overcurrent region, to ensure continuity between the severe and moderate overcurrent regions at the boundary I_m→I_M, the saturation value of the soft current-limiting component at the severe-overcurrent boundary is defined as:

$$\Delta X_{\mathrm{AVR}}^{\max }=\underset{I_m\to I_M}{\lim }\Delta X_{\mathrm{AVR}}(I_m)\text{}$$

(13)

Accordingly, the piecewise expression of the virtual reactance in the severe overcurrent region is given as:

$$X_v\text{}(t)=X_0\text{}+\Delta X_{AVR}^{\max }\text{}+\Delta X_{REQ}\text{}(t),S_I\text{}=2$$

(14)

In the above equation, ΔX_REQ denotes the increment of the virtual reactance in the severe overcurrent region.

To suppress the instantaneous current spikes caused by control delays and modulation saturation in the severe overcurrent region, in addition to the hard current limiting achieved by calculating the equivalent virtual reactance according to Equations (12)–(14), a blocking logic based on the instantaneous phase-current magnitude is further incorporated into the IGBT gate signals. Specifically, the instantaneous currents of each phase are first compared with the allowable device peak threshold I_max = 1.2I_M to produce the corresponding gate-enable signals en_a, en_b, and en_c, as described in Equation (15). The enable signals are then logically ANDed with the original PWM gating pulses gk to obtain the final drive signals gk*, as given in Equation (16). When the rms value of any phase current exceeds I_max, the gating pulses of both the upper and lower switches in the corresponding phase leg are synchronously blocked, thereby coordinating with the virtual-reactance-based current limiting.

$$\left\{\begin{array}{c}e{n}_{\mathrm{a}}(t)=H(I_{max}-|i_A(t)|)\\ e{n}_b(t)=H(I_{max}-|i_B(t)|)\\ e{n}_c(t)=H(I_{max}-|i_C(t)|)\end{array}\right.$$

(15)

In the above equation, H denotes the step function: it takes the value of 1 when the quantity inside the parentheses is greater than or equal to 0, and 0 otherwise.

$$\left\{\begin{array}{c}{g}_1^{\prime }(t)=g_1(t)\wedge e{n}_a(t),g_4^{\prime }(t)=g_4(t)\wedge e{n}_a(t)\\ g_3^{\prime }(t)=g_3(t)\wedge e{n}_b(t),g_6^{\prime }(t)=g_6(t)\wedge e{n}_b(t)\\ g_5^{\prime }(t)=g_5(t)\wedge e{n}_c(t),g_2^{\prime }(t)=g_2(t)\wedge e{n}_c(t)\end{array}\right.$$

(16)

The blocking logic flowchart based on the instantaneous phase-current magnitude is shown in Figure 3:

Figure 3. The blocking logic flowchart based on the instantaneous phase-current magnitude.

Overall, by combining the IGBT hardware gate-blocking logic with the adaptive regulation of virtual reactance, the proposed fault current-limiting method can theoretically not only effectively suppress overcurrent under different fault severities, but also further shorten the post-fault current recovery time through adaptive virtual-reactance adjustment according to the specific overcurrent level.

5. Experimental Validation

Based on the StarSim-RCP + StarSim-HIL experimental platform, according to Figure 4, an electromagnetic transient (EMT) simulation model of an EV charging converter (GFM) was established and the main parameters are listed in Table 1 to verify the effectiveness of the proposed virtual-reactance-based fault current-limiting method.

Figure 4. Experimental platform based on StarSim-RCP and StarSim-HIL.

Table 1. Parameters of the experimental model.

Parameter	Value
Converter rated apparent power (VA)	20,000
Grid line-to-line voltage ug (V)	380
DC-link voltage Udc (V)	800
Grid frequency (Hz)	50
Filter inductance L (mH)	8.2
Filter capacitance C (uF)	10
Carrier frequency f (Hz)	10 k
Sampling period Tc (us)	10
Control frequency (Hz)	20 k
Virtual inertia J (kg m2)	3.2
Damping coefficient D	63.66
Reactive-power outer-loop Kp	7.37
Reactive-power outer-loop Ki	131.23
Current-loop Kp	3
Current-loop Ki	400

The experimental parameters are listed in Table 1. The converter is set to Pref = 15 kW and Qref = 0, and the rated phase current is I_N = 20 A.

(1)

Verification of the Current-Limiting Strategy in the Moderate Overcurrent Region

The location of the fault point K is shown in Figure 1. A three-phase grounding fault occurs at t0 with a fault transition resistance of 4 Ω, and it is cleared after 0.01 s. The fault duration is 10 ms. The simulated PCC voltage and current waveforms are shown in Figure 5 and Figure 6, respectively. Without the current-limiting strategy, the peak current of the most severely affected fault phase (phase B) reaches 50 A (blue curve), and the phase current returns to the rated value within 55 ms after fault clearance. With the proposed current-limiting strategy, the phase-current peak is reduced to 42 A, and the rms value is 29 A (below 1.5IN = 30 A); moreover, the phase current recovers to the rated value within 35 ms after fault clearance.

Figure 5. PCC voltage and current waveforms under moderate overcurrent without current−limiting.

Figure 6. PCC voltage and current waveforms under moderate overcurrent with current−limiting strategy.

(2)

Verification of the Current-Limiting Strategy in the Severe Overcurrent Region

A three-phase grounding fault occurs at t0 with a fault transition resistance of 0.7Ω, and it is cleared after 0.025 s. The fault duration is 25 ms. The simulated PCC voltage and current waveforms are shown in Figure 7 and Figure 8, respectively. Without the current-limiting strategy, the peak current of the most severely affected fault phase (phase B) reaches 90 A (blue curve), and the phase current returns to the rated value within 65 ms after fault clearance. With the proposed current-limiting strategy, the phase-current peak is reduced to 62 A, and the rms value is 43 A, which is below 2.2IN = 44 A. Moreover, the phase current recovers to the rated value within 45 ms after fault clearance.

Figure 7. PCC voltage and current waveforms under severe overcurrent without current−limiting strategy.

Figure 8. PCC voltage and current waveforms under severe overcurrent with current−limiting strategy.

6. Conclusions

In this paper, for the moderate overcurrent region, a soft current-limiting action is achieved via adaptive virtual reactance, whereas for the severe overcurrent region, a hard current-limiting action is realized by further increasing the virtual reactance and blocking overcurrent bridge arm. The two current-limiting actions are unified into a piecewise virtual-reactance formulation, which ensures current limiting while shortening the post-fault restoration time. Experimental results demonstrate that, without significantly degrading the voltage-support capability, the proposed method effectively limits the fault-current peak, improves the dynamic performance of the inner current loop, and enhances the LVRT capability and operational reliability of grid-forming converters. In future research, the proposed method will be extended to asymmetric fault conditions, and its performance under very weak grid conditions with extremely low SCR will be further investigated.