An Error-Compensated Configurable Approximate Recursive Multiplier for Energy-Efficient Image Processing and CNN Inference

Abstract

The growing demand for energy-efficient arithmetic circuits, particularly for edge-based image processing and deep learning inference, has sustained research interest in approximate computing. However, existing approximate recursive multipliers often suffer from error accumulation in recursive structures and limited flexibility in balancing accuracy and hardware efficiency. To address these limitations, this paper proposes a configurable approximate recursive multiplier based on an Error-Compensated Recursive Structure (ECRS). The design integrates partial carry truncation with a novel w3_2 compressor for localized error reduction. Meanwhile, the ECRS dynamically optimizes compensation columns to suppress error propagation in higher-order multiplications, with tunable precision achieved via optimized 4 × 4 building blocks. Synthesized in TSMC 28 nm CMOS, the high-precision configuration (W8_1) reduces area, power, and delay by 11.87%, 12.71% and 20.25% versus the exact multiplier, while the low-power configuration (W8_6ct4) achieves over 58% area reduction. In Gaussian image smoothing, W8_1 maintains a PSNR of 54.73 dB and an SSIM of 99.93%. In quantized CNN inference, W8_1 achieves accuracy close to the exact baseline across a range of models and datasets, with most tested configurations exhibiting a loss of 0.2% or less and only a few exceptions where architectural sensitivity leads to slightly larger degradation.

1. Introduction

The rapid proliferation of Internet of Things devices and the growing demand for artificial intelligence at the edge have created an urgent need for embedded systems that can perform complex computations under stringent power and area constraints [1,2]. Applications such as real-time image processing, speech recognition, and autonomous decision-making rely heavily on arithmetic-intensive algorithms like the convolutional neural network (CNN). In these algorithms, multipliers are fundamental and power-hungry units [3,4]. This makes the development of high-energy-efficiency multipliers a critical research focus for enabling the next generation of edge computing.

In this context, approximate computing has gained significant traction as a promising paradigm [5,6]. By leveraging the intrinsic error resilience of many end-user applications (e.g., where human perception is the final judge or where machine learning algorithms are robust to small numerical variations), it deliberately trades off computational exactness for substantial gains in power consumption, silicon area, and processing speed [7]. Approximate multipliers, as a key enabler, have been extensively studied. Previous works have explored techniques such as logic simplification [8], voltage over-scaling [9], and truncation of partial products or carry chains [10,11]. Recent efforts also focus on designing efficient approximate compressors and recursive structures to build larger multipliers [12,13].

However, a notable gap remains between circuit-level optimization and system-level application readiness. Many existing approximate multipliers offer a static trade-off point between accuracy and efficiency, lacking the flexibility to adapt to diverse application requirements [14]. More importantly, their evaluation often lacks comprehensive validation in complex, algorithm-level scenarios such as modern deep learning pipelines, leaving their practical impact uncertain. A hardware solution that provides a configurable accuracy-efficiency trade-off and is rigorously validated across both classic signal processing and state-of-the-art neural network tasks would be of considerable value for the edge computing ecosystem.

To bridge this gap, this paper proposes a configurable approximate recursive multiplier architecture based on partial carry truncation with dynamic error compensation. The main contributions are summarized as follows:

• We design two optimized 4 × 4 approximate multiplier blocks, W1 and W2, incorporating a novel w3_2 compressor for localized error reduction. These blocks serve as configurable building blocks, enabling flexible trade-offs between accuracy and hardware efficiency.
• We construct 8 × 8 recursive multipliers with tunable precision. The high-precision configuration (W8_1) restricts approximation to the least significant block (aLbL) to minimize accuracy loss. An error-compensated recursive structure (ECRS) is introduced to dynamically optimize the number of compensation columns, yielding a low-power multiplier (W8_6ct4) that maintains improved precision under aggressive power savings.
• We provide a comprehensive cross-layer evaluation framework. Circuit-level performance is assessed using industry-standard synthesis tools (TSMC 28 nm). Application-level validation encompasses image smoothing (PSNR, SSIM) and quantized CNN inference (CIFAR-10, MNIST), demonstrating practical suitability for error-resilient edge AI workloads.

Compared with prior approximate recursive multipliers that typically employ fixed approximation strategies, this work explores configurable building blocks, analyzes the effect of compensation column count on error in the recursive summation stage, and validates the design on deep convolutional network datasets. This suggests broader applicability across different task domains.

The rest of this paper is organized as follows: Section 2 reviews the background of recursive and approximate multipliers. Section 3 details the proposed design methodology. Section 4 presents the experimental results and analysis. Section 5 concludes the paper.

2. Related Work

Approximation techniques for multipliers can be applied at multiple design levels—from low-level circuit and logic simplification to architectural modifications and algorithmic adaptations. This section reviews prior work most relevant to our approach, which primarily operates at the circuit and architecture levels.

2.1. Recursive Multiplier

The recursive multiplier is an algorithm that employs a divide-and-conquer strategy to perform large-number multiplication. Its core idea is to decompose a large multiplication problem into several smaller sub-problems, solve these sub-problems recursively, and finally combine their results to obtain the final product [15,16]. The 4 × 4 multiplier is selected as the fundamental building block because it represents a widely adopted granularity in recursive multiplier design. Smaller blocks (e.g., 2 × 2) offer finer modularity but require more levels of recursive summation, increasing both the adder tree complexity and the accumulation of approximation errors. Larger blocks (e.g., 8 × 8 used directly) provide less opportunity for modular approximation and configurable trade-offs. The 4 × 4 granularity thus offers a balanced compromise between design flexibility, hardware efficiency, and error controllability. By effectively deconstructing the problem through this strategy, the recursive multiplier makes the multiplication of large numbers simpler and more efficient. This approach utilizes a building-block structure, which grants the recursive multiplier modularity and scalability. The building blocks modularize the multiplication operation: each block operates independently, and their computation results are subsequently integrated into the final result. As shown in Figure 1, an 8 × 8 multiplier is implemented using four 4 × 4 multiplication building blocks, denoted as aLbL, aHbL, aLbH, and aHbH, which correspond to four distinct multiplier modules. Among these, aLbL represents the least significant block, while aHbH represents the most significant block.

Figure 1. Structure of 8 × 8 recursive multiplier constructed from four 4 × 4 building blocks.

A recursive multiplier can employ building blocks with varying levels of precision and approximation depending on the specific requirements. This allows the overall multiplier design to be tailored to its intended performance targets. For instance, in application scenarios demanding high speed, optimized low-power and high-speed building blocks can be adopted. Conversely, for scenarios prioritizing high accuracy, precise building blocks can be utilized in the most significant bit positions. Through this divide-and-conquer and modular approach, the recursive multiplier becomes capable of not only performing large-scale multiplication operations but also being optimized for diverse performance needs [17].

2.2. Precise 4 × 4 Array Multiplier

The precise 4 × 4 array multiplier is the baseline of our proposed approximate design, which computes the exact product of two 4-bit binary inputs with an 8-bit output. As shown in Figure 2, it adopts a regular array structure composed of full adders (FAs) and half adders (HAs). This structure completes the partial product summation through a carry-propagation chain. This modular, regular structure is highly suitable for VLSI implementation and is widely used as the building block for recursive higher-order multipliers [18,19].

Figure 2. Circuit structure of precise 4 × 4 array multiplier.

3. Approximate Multiplier Based on Partial Carry Truncation

Carry truncation refers to selectively discarding portions of the lower-order carry chain to reduce computational operations, significantly lower power consumption and area requirements, and minimize signal propagation delays [20]. The primary design approach involves truncating low-order carries while preserving the high-order carry calculation for critical bits. Since partial carry truncation multipliers directly discard carry signals beyond a certain bit (without propagating them backward) during partial product addition, this introduces a negative-direction error (i.e., underestimation) in the overall result. Therefore, an error analysis proposes a novel approximate compressor to compensate for part of this error.

3.1. Analysis of Truncated Digits

In previous work, the carry-truncation section of multipliers has employed either XOR-based methods for precise partial sum calculation or OR-based methods for approximate partial sum calculation [21,22]. While XOR gates yield precise partial sums, the nature of carry truncation causes final results to be underestimated. Replacing XOR gates with OR gates introduces an error offset to balance the result while simultaneously reducing critical path delay and enhancing circuit speed. This modification optimizes overall circuit design for greater speed and efficiency without compromising computational accuracy. Building upon the array multiplier structure, this research primarily focuses on truncation using OR gates. For clarity, the rightmost column of the partial product array is designated as the first column. In a 4 × 4 multiplier, seven partial-product columns are counted from right to left. Multipliers requiring discussion are named W4_ctX, where X denotes the truncated column number, based on the truncated column count and summation strategy. Table 1 presents the Mean Error Distance (MED) and the Difference (DIF) from the MED of the preceding truncated column number for these multipliers.

Table 1. Comparison of error metrics for 4 × 4 multipliers with different numbers of truncated columns.

Design	MED	DIF
exact	0	-
W4_ct2	0.13	0.13
W4_ct3	0.81	0.68
W4_ct4	3.34	2.53
W4_ct5	6.09	2.75
W4_ct6	8.09	2

As the number of truncated columns increases, all error measures grow. Since no new carry occurs after truncating the sixth column, subsequent operations remain unaffected. Therefore, the error from truncating the seventh column is identical to that from truncating the sixth column and is not repeated in the table. This phenomenon reflects the accumulation of truncation errors in arithmetic. Consequently, careful selection of the number of truncated columns is essential in high-precision calculations to minimize errors within acceptable limits.

3.2. Approximate 3_2 Compressor

When an approximate compressor is introduced into a carry-truncated multiplier, the core design goal is to simplify the circuit while introducing a controllable positive expected error to offset the negative systematic bias caused by carry truncation. To address this, we establish an error model of the approximate compressor through probabilistic analysis, to guide the selection of the optimal compressor design.

3.2.1. Error Modeling and Probability Analysis

Let the compressor inputs A, B, and C be independent binary random variables; in the absence of prior information, assume they follow a uniform distribution:

$$P(A=1)=P(B=1)=P(C=1)={\displaystyle \frac{1}{2}}$$

(1)

The output logic of an exact full adder is:

$$Su{m}_{\mathrm{exact}}=A\oplus B\oplus C,Carr{y}_{\mathrm{exact}}=C(A+B)+AB$$

(2)

Its expected output is:

$$E[Su{m}_{\mathrm{exact}}]=P(Su{m}_{\mathrm{exact}}=1)={\displaystyle \frac{1}{2}},E[Carr{y}_{\mathrm{exact}}]={\displaystyle \frac{1}{2}}$$

(3)

Define the expected error as $E[D]=E[Outpu{t}_{\mathrm{pprox}.}]-E[Outpu{t}_{\mathrm{exact}}]$. The design objective is to introduce positive error to offset the negative bias caused by carry-clipping, while preventing the error from propagating to higher bits. It should be noted that this analysis assumes input bits are independent and uniformly distributed, which serves as a tractable baseline for deriving expected error metrics and guiding initial design decisions. In practical applications, operand statistics may deviate from uniformity; the impact of such deviations is examined empirically in the application-level evaluations presented in Section 5.

This paper presents a theoretical analysis of four candidate compressors; the results are listed in Table 2.

Table 2. Ablation experiment results for different candidate approximate 3-2 compressors.

Design	Logical Expression	MED
Use an exact full adder	$\begin{array}{c}Sum=A\oplus B\oplus C\end{array}$ $\begin{array}{c}Carry=C\left(A+B\right)+AB\end{array}$	3.344
Retain the exact carry and keep an XOR gate in the and bit selection	$\begin{array}{c}Sum=A\oplus B+C\end{array}$ $\begin{array}{c}Carry=C\left(A+B\right)+AB\end{array}$	3.391
Retain the exact carry and select the OR gate instead of the XOR gate for the AND bit	$\begin{array}{c}Sum=A+B+C\end{array}$ $\begin{array}{c}Carry=C\left(A+B\right)+AB\end{array}$	3.328
Without retaining precise carry, use OR gates instead of XOR gates in the AND bit selection	$\begin{array}{c}Sum=A+B+C\end{array}$ $Carry=\overline{\left(\overline{AB}+C\right)}$	5.281

Design 1 (Precise Full Adder): As a baseline, $E[D_{Sum}]=0,\mathrm{E}[D_{Carry}]=0$.

Design 2 (preserving exact carry, where the sum bit is $A\oplus B+C$): First, calculate the distribution of $A\oplus B$: $P(A\oplus B=1)=P(A=1,B=0)+P(A=0,B=1)={\displaystyle \frac{1}{4}}+{\displaystyle \frac{1}{4}}={\displaystyle \frac{1}{2}}$.

The probability that the digit in the ones place is 1 is:

$$P(Sum=1)=P(A\oplus B=1)+P(A\oplus B=0)\cdot P(C=1)={\displaystyle \frac{1}{2}}+{\displaystyle \frac{1}{2}} \times {\displaystyle \frac{1}{2}}={\displaystyle \frac{3}{4}}$$

(4)

Therefore, $E[D_{Sum}]={\displaystyle \frac{3}{4}}-{\displaystyle \frac{1}{2}}=+{\displaystyle \frac{1}{4}}$, which is carried over exactly, and $E[D_{Carry}]=0$.

Design 3 (w3_2 compressor, preserving exact carry, sum bit set to $A+B+C$):

The probability that the three-input OR gate outputs 1 is:

$$P(Sum=1)=1-P(A=0)P(B=0)P(C=0)=1-{\left({\displaystyle \frac{1}{2}}\right)}^3={\displaystyle \frac{7}{8}}$$

(5)

Therefore, $E[D_{Sum}]={\displaystyle \frac{7}{8}}-{\displaystyle \frac{1}{2}}=+{\displaystyle \frac{3}{8}}$, with precise carry, $E[D_{Carry}]=0$.

Design 4 (does not preserve precise carry, sum bit is $A+B+C$, carry bit is $A\cdot B+C$):

The probability that the carry logic ‘Carry = AB + C’ is 1 is:

$$P(Carry=1)=P(AB=1)+P(AB=0)\cdot P(C=1)={\displaystyle \frac{1}{4}}+\left(1−{\displaystyle \frac{1}{4}}\right) \times {\displaystyle \frac{1}{2}}={\displaystyle \frac{1}{4}}+{\displaystyle \frac{3}{8}}={\displaystyle \frac{5}{8}}$$

(6)

Therefore, $E[D_{Carry}]={\displaystyle \frac{5}{8}}-{\displaystyle \frac{1}{2}}=+{\displaystyle \frac{1}{8}}$. Compared to Design 3, the position error is +3/8, resulting in a significant increase in total error.

3.2.2. Theoretical Conclusion and Experimental Verification

From the above derivation, we can conclude that:

The w3_2 compressor (Design 3) has the largest positive bit error (+0.375) and is most effective at offsetting the negative bias caused by carry truncation. The carry-preserving design precisely prevents errors from propagating to higher bits through the carry chain, thereby preventing error accumulation. Although Design 4 has the same bit error, the carry error compromises high-order precision, leading to a deterioration in overall performance.

To verify the theoretical analysis, the four compressors were applied to a 4 × 4 multiplier truncated to the fourth column, and the Mean Error Distance (MED) was compared. The experimental results are shown in Table 2: Design 3 has a MED of 3.328, which is lower than that of Design 2 (3.391) and Design 1 (3.344), while Design 4 has a high MED of 5.281. The theory and experiments are highly consistent, confirming the effectiveness of the w3_2 compressor. Its circuit structure is shown in Figure 3.

Figure 3. Circuit structure of the proposed w3_2 approximate 3-2 compressor.

3.3. Approximate Partial Carry Truncation Multiplier

The data in Table 1 show that the multiplier error grows with the number of truncated carry columns. Notably, the error increases significantly when columns 4 to 7 are truncated. If adjustments and error compensation are applied to columns 4 to 7, the overall error of the multiplier should be significantly reduced, leading to more accurate calculations. However, experimental observation alone cannot reveal the underlying mechanism of error compensation. Therefore, this section first establishes an error model for the partial product array and mathematically derives the impact of different truncation and compensation strategies on the final error, thereby guiding the structural design of W1 and W2.

3.3.1. Error Analysis for Partial Carry Truncation

Let the output of the exact 4 × 4 multiplier be $P_{exact}$, and the output of the approximate multiplier be $P_{approx}$, with error $\Delta =P_{exact}-P_{approx}$. Due to carry truncation, $\Delta$ is typically positive (i.e., the result is smaller). Our goal is to introduce a compensation term $C$ through local logic optimization to minimize the expected error $E[\mid \Delta -C\mid ]$.

Consider the $i$-th column of the partial product array (numbered 1 to 7 from right to left). In the exact multiplier, the sum bit $S_i$ of the $i$-th column is obtained by adding the partial products in that column and the carry from the lower column. When carry truncation is applied, the carry $C_{in,i-1}$ from the $\left(i−1\right)$-th column is discarded, causing a negative error in $S_i$. If the logic for calculating $S_i$ is changed from XOR to OR, according to Boolean algebra, the OR gate outputs 1 for inputs (1,0) or (0,1), consistent with XOR. Only for input (1,1) does OR output 1 while XOR outputs 0. For a given column, when both partial products are 1, using an OR gate yields a result of 1, whereas the exact sum would be 0. This reduces the overall error compared to simply truncating the carry, because the OR gate partially corrects the underestimation caused by carry truncation. Therefore, using OR gates in lower columns is an effective strategy for error reduction.

3.3.2. Design of the W1 Multiplier

Based on the theoretical analysis above, the structure of the proposed approximate carry-truncation multiplier W1 is shown in Figure 4. The design logic is as follows: OR gates are used in columns 2, 3, and 4, and carries are truncated, replacing exact addition. These columns are in lower positions with smaller weights, so the introduced error has a smaller impact on the final result. According to the probability analysis, OR gates help reduce the error in these columns by partially correcting the underestimation caused by carry truncation, thereby improving the overall accuracy from a mathematical expectation perspective. Column 5 has a higher weight, and with more partial products, the error impact is greater. Therefore, the specially designed w3_2 compressor is used here. The core of this compressor lies in preserving the precise carry signal for propagation. For the input vector (1,1,1), the OR gate outputs a sum of 1, matching the exact modulo-2 sum. However, in the larger summation tree, this input combination represents an arithmetic sum of 3. In an exact calculation, this scenario would generate a carry. By preserving the precise carry and propagating it to the next column, while using an OR gate to compute the sum bit, the design achieves accurate carry propagation to the higher bit at this column while reducing the error in the local sum bit, thereby mitigating the error accumulated from low-bit truncation.

Figure 4. Circuit structure of the proposed approximate 4 × 4 multiplier W1.

3.3.3. Design of the W2 Multiplier

The circuit structure of the W2 multiplier is shown in Figure 5. Unlike W1, W2 does not use the w3_2 compressor but adopts a more aggressive approximation strategy: OR gates are used for direct summation in columns 2 to 5 (without propagating carries); a half-adder is used in column 6, and its carry output is directly used as the highest bit of the product, while column 7 directly takes the partial product $a_3{b}_3$ as the value of S6. This design further reduces hardware complexity compared to W1 while retaining some high-bit information through clever carry reuse.

Figure 5. Circuit structure of the proposed approximate 4 × 4 multiplier W2.

In the exact calculation, column 6 involves the two partial products $a_3{b}_2,a_2{b}_3$ and the carry $Cou{t}_5$ from column 5. A fully accurate implementation would require a full adder. W2 chooses to sum the two partial products using only a half-adder and directly outputs the carry generated by the half-adder as the highest bit. The physical meaning of this is: the half-adder outputs the sum $S_5=a_3{b}_2\oplus a_2{b}_3$, discarding the carry from column 5, thus introducing an error. However, the half-adder carry $C3=a_3{b}_2\cdot a_2{b}_3$ is elevated to the highest bit $S_7$. This operation is equivalent to preserving the potentially lost high-bit information in a simplified form.

From an error statistics perspective, if the carry were completely ignored (i.e., $S_5=a_3{b}_2\oplus a_2{b}_3, S_7=0$), the expected error of $S_5$ would be approximately −0.125, and all high-bit information would be lost. By outputting $C3$ as $S_7$, the highest bit becomes 1 for the input combination $\left(a_3{b}_2,a_2{b}_3)=(\mathrm{1,1}\right)$ (probability $\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$4$}\right.$), while the exact $S_7$ being 1 has a probability of about 0.125. Therefore, this design introduces compensation to the highest bit with a relatively high probability, partially mitigating the impact of the lost low-bit carry, while avoiding the need for an additional full adder.

Column 7 in the exact multiplier should be $a_3{b}_3\oplus Cou{t}_6$, where $Cou{t}_6$ is the carry from column 6. W2 directly takes $S_6=a_3{b}_3$, ignoring $Cou{t}_6$. Although this introduces an expected error of about −0.125, it retains the main component of the most significant bit of the product with zero hardware overhead. Since $Cou{t}_6$ is partially mapped to $S_7$, the overall high-bit information is not completely lost.

In summary, both W1 and W2 follow a common design approach based on partial carry truncation. In lower-weight columns, exact adders are replaced with OR gates for summation, which simplifies the circuit but introduces a systematic negative bias. This bias is then compensated by different strategies: W1 employs the w3_2 compressor in column 5 to provide local positive error correction, while W2 adopts a more aggressive truncation and uses a half-adder in column 6 with its carry output elevated to the highest bit. The two designs thus represent different trade-off points within the same design framework.

3.4. Error-Compensated Recursive Structure (ECRS)

A recursive multiplier implements higher-order multiplication by combining multiple lower-order multipliers, as shown in Figure 6. When approximate multipliers are used as basic modules, the errors from each module accumulate. To control the overall error, this paper introduces a dynamic compensation strategy in the recursive summation stage: the w3_2 approximate compressor is used to replace some of the exact full adders, performing error compensation on a column-by-column basis.

Figure 6. Structure of the proposed Error-Compensated Recursive Structure for multiplier design.

3.4.1. Error Propagation Model

Suppose an 8 × 8 multiplier consists of four 4 × 4 submodules, with the output given by:

$$P=P_{LL}+2^4(P_{HL}+P_{LH})+2^8{P}_{HH}$$

(7)

where $P_{LL},P_{HL},P_{LH},P_{HH}$ are the products of the four submodules, respectively. When the submodules are approximate multipliers, each product has an error ${\Delta }_{LL},{\Delta }_{HL},{\Delta }_{LH},{\Delta }_{HH}$. The total error is:

$$\Delta ={\Delta }_{LL}+2^4({\Delta }_{HL}+{\Delta }_{LH})+2^8{\Delta }_{HH}$$

(8)

During the summation process, the outputs of the submodules are aligned by bit and added. Errors from lower modules propagate to higher bits through the addition chain. Traditional exact adders faithfully propagate carries, causing low-bit errors to be directly superimposed onto higher bits. To suppress error propagation, the ECRS uses the w3_2 approximate compressor to replace some of the full adders. The theoretical basis for error blocking is as follows. According to the error propagation model in Equation (8), errors from lower sub-modules are amplified by factors of $2^4$ and $2^8$ when propagating to higher bits through the carry chain. This amplification is the primary cause of error accumulation in recursive multipliers. The w3_2 compressor retains the exact carry output logic of a full adder. Consequently, even if an error occurs in the sum bit of the current column, the carry signal propagated to the higher column remains identical to that of exact computation.

A numerical example is used to illustrate this mechanism: when the sum of the current column is 3 (inputs 1,1,1), the exact full adder outputs Sum = 1, Carry = 1; the w3_2 compressor also outputs Sum = 1, Carry = 1, with no error. When the sum of the current column is 1 (inputs 1,0,0), the exact full adder outputs Sum = 1, Carry = 0; the w3_2 compressor also outputs Sum = 1, Carry = 0, with no error. Only when the sum of the current column is 2 (inputs 1,1,0), the exact full adder outputs Sum = 0, Carry = 1, while the w3_2 compressor outputs Sum = 1, Carry = 1: only the sum bit has a fixed error of +1, and the carry output remains completely accurate.

This characteristic ensures that the error of the w3_2 compressor is always limited to the current column and will not be amplified by the bit weight through the carry chain, thus fundamentally suppressing error accumulation in the recursive multiplication process.

3.4.2. Optimal Number of Compensation Columns

The choice of the number of compensation columns in the ECRS requires a trade-off: insufficient compensation may not fully cancel the low-bit negative error, while excessive compensation can cause the positive error introduced by the w3_2 itself to accumulate excessively.

Let the expected cumulative error at bit $i$ be $E[{\Delta }_i]$, which may be negative without compensation. Introducing $k$ compensation columns, i.e., using the w3_2 compressor for the lowest $k$ bits, introduces an expected positive compensation of $\delta =+0.375$ per bit (though the actual effective compensation is affected by the propagation path). The net error at bit $i$ after compensation is:

$$E[{\Delta }_i^{\left(k\right)}]=E[{\Delta }_i]+\mathrm{m}\mathrm{i}\mathrm{n}(i,k)\cdot \alpha$$

(9)

where $\alpha$ is the average effective contribution per column of compensation ($0<\alpha <0.375$, as some compensation may be weakened by subsequent addition). The optimal number of compensation columns $k^{*}$ should minimize some norm of the total error, explaining why different designs have different optimal $k$ values.

4. Experiments and Result Analysis

We conducted a comprehensive comparison between the proposed multiplier and another multiplier [23,24,25,26] that also employs a recursive structure, evaluating the advantages and disadvantages of different design approaches in terms of performance, power consumption, and area efficiency. The W8 × 8 series of multipliers is composed of different combinations of the 4 × 4 multipliers (W1 and W2) and the precise 4 × 4 multiplier. Table 3 details the designs for constructing the 8 × 8 multiplier using different 4 × 4 multiplier submodules.

Table 3. Composition of sub-modules for constructing 8 × 8 approximate multipliers.

Design	$\mathit{a}\mathit{H}\mathit{b}\mathit{H}$	$\mathit{a}\mathit{H}\mathit{b}\mathit{L}$	$\mathit{a}\mathit{L}\mathit{b}\mathit{H}$	$\mathit{a}\mathit{L}\mathit{b}\mathit{L}$
PCTM8 [23]	exact	exact	exact	PCTM4
M8-1 [24]	M1	M1	M1	M1
M8-2 [24]	M2	M2	M2	M2
M8-3 [24]	exact	M1	M1	M1
M8-4 [24]	exact	M2	M2	M2
M8-5 [24]	exact	exact	exact	M1
M8-6 [24]	exact	exact	exact	M2
AxRM1 [25]	exact	exact	exact	Mul2b4
AxRM2 [25]	exact	exact	Mul2b4	Mul2b4
AxRM3 [25]	exact	Mul2a4	Mul2b4	Mul2b4
N8-5 [26]	exact	exact	exact	N1
N8-6 [26]	exact	exact	exact	N2
N8-L1 [26]	exact	N1	N1	OR-Based
N8-L2 [26]	exact	N2	N2	OR-Based
W8_1	exact	exact	exact	W1
W8_2	exact	exact	exact	W2
W8_3	exact	W1	W1	W1
W8_4	exact	W2	W2	W2
W8_5	W1	W1	W1	W1
W8_6	W2	W2	W2	W2

4.1. Error Analysis and Evaluation

Error analysis for approximation circuits primarily focuses on Error Distance (ED). Error distance refers to the distance between the output of the approximation circuit and the ideal output. A smaller error distance indicates a lower degree of precision loss in the circuit’s approximation results. When evaluating the performance of approximation multipliers, MED and Normalized Mean Error Distance (NMED) are two key metrics used to quantify the deviation between the approximated result and the exact result. Another important metric is the Mean Relative Error Distance (MRED), which evaluates the error distance between approximate and exact results by calculating the relative error for each input pair. Mean Square Error (MSE) assesses overall error fluctuation by summing the squares of errors across the entire data domain and averaging them, measuring the distribution of errors. A low MSE indicates reduced fluctuation, signifying the approximator’s stable output performance across varying inputs. The MSE value can also be used to calculate the Number of Effective Bits (NoEB), representing how many binary digits of the multiplier are genuinely reliable and contain meaningful information. NoEB is based on the statistical distribution and power of errors, comprehensively considering error scenarios across all possible inputs. It provides a more robust reflection of the multiplier’s long-term precision performance [27,28]. The calculation formulas for all the above metrics are as follows (10)–(15). All error metrics reported in this section are obtained through exhaustive simulation over the complete input space, and therefore represent the exact population statistics under the assumed uniform input distribution.

$$MED={\displaystyle \frac{\sum ED\mathrm{i}}{2^{2n}}}$$

(10)

$$NMED={\displaystyle \frac{MED}{{\left(2^n-1\right)}^2}}$$

(11)

$$RE{D}_i={\displaystyle \frac{E{D}_i}{{\omega }_i}}\left(\forall {\omega }_i\ne 0\right)$$

(12)

$$MRED={\displaystyle \frac{\sum RE{D}_i}{2^{2n}}}$$

(13)

$$MSE={\displaystyle \frac{\sum E{D}_i^2}{2^{2^n}}}$$

(14)

$$NoEB=2n-{\log }_2\left(1+\sqrt{MSE}\right)$$

(15)

4.1.1. Error Index of Approximate 4 × 4 Multipliers and the 8 × 8 Multipliers They Constitute

Carry truncation is the primary source of error generation. The error conditions for the 4 × 4 and 8 × 8 multipliers designed in this paper are evaluated separately below. To comprehensively validate the accuracy and performance of the multipliers, we employed the Modelsim SE-64 10.4 to conduct exhaustive functional verification on the implemented designs. By performing exhaustive testing on all possible input combinations, we ensured the correctness and reliability of the designed approximate multipliers, thereby guaranteeing their efficiency and stability in practical applications. Table 4 and Table 5 list the error metrics for the 4 × 4 multiplier and the 8 × 8 multiplier constructed from it, respectively.

Table 4. Error performance metrics of different 4 × 4 approximate multipliers.

Design	MED	MRED (%)	NoEB	ER (%)
PCTM4 [23]	3.78	5.89	4.93	35.94
M1 [24]	3.91	6.06	4.89	35.94
M2 [24]	6.22	7.87	4.20	35.94
Mul2b4 [25]	16.78	51.28	3.36	75.00
N1 [26]	3.97	4.89	4.83	35.94
N2 [26]	5.50	6.36	4.42	37.11
W1	3.32	4.47	5.12	35.94
W2	6.81	7.15	4.06	37.11

Table 5. Error performance metrics of different 8 × 8 approximate multipliers.

Design	MED	NMED	MRED(%)	NoEB
CDM8_51 [22]	14.25	2.2$\times {10}^{-4}$	0.40	11.29
CDM8_74 [22]	157.25	$2.4 \times {10}^{-3}$	2.41	8.08
CDM8_95 [22]	777.25	$1.2 \times {10}^{-2}$	7.66	5.81
CDM8_aa [22]	4713.25	$7.3 \times {10}^{-2}$	21.45	2.85
PCTM8 [23]	3.78	$5.8 \times {10}^{-5}$	0.12	12.93
M8-1 [24]	1075.65	$1.7 \times {10}^{-2}$	6.09	5.04
M8-2 [24]	1795.68	$2.8 \times {10}^{-2}$	8.42	4.22
M8-3 [24]	114.91	$1.8 \times {10}^{-3}$	1.60	8.51
M8-4 [24]	204.82	$3.2 \times {10}^{-3}$	2.26	7.62
M8-5 [24]	3.91	$6.0 \times {10}^{-5}$	0.12	12.88
M8-6 [24]	6.22	$9.6 \times {10}^{-5}$	0.18	12.20
AxRM1 [25]	16.78	$2.6 \times {10}^{-4}$	0.77	11.36
AxRM2 [25]	278.63	4.3 × ${10}^{-3}$	5.62	7.38
AxRM3 [25]	340.95	$5.2 \times {10}^{-3}$	7.57	7.19
N8-5 [26]	3.97	$6.1 \times {10}^{-5}$	0.12	12.83
N8-6 [26]	5.50	$8.5 \times {10}^{-5}$	0.16	12.42
N8-L1 [26]	168.41	$2.6 \times {10}^{-3}$	2.36	8.01
N8-L2 [26]	221.71	$3.4 \times {10}^{-3}$	2.92	7.64
W8_1	3.32	5.1 × ${10}^{-5}$	0.10	13.12
W8_2	6.81	$1.0 \times {10}^{-4}$	0.18	12.05
W8_3	96.18	$1.5 \times {10}^{-3}$	1.30	8.79
W8_4	205.71	$3.2 \times {10}^{-3}$	2.28	7.62
W8_5	915.04	$1.4 \times {10}^{-2}$	5.09	5.30
W8_6	1884.31	$2.9 \times {10}^{-2}$	8.44	4.12

Compared to the approximate multipliers proposed in [23,24,25,26], it is evident that W1 demonstrates significant advantages across multiple key metrics. W1 achieves a NoEB of 5.12, which is 0.19 higher than PCTM4 [23] (4.93) and 0.23 higher than N1 [26] (4.83), indicating improved precision and reliability. Similarly, the 8 × 8 recursive multiplier W8_1, composed of W1 and an exact multiplier, stands out in multiple core metrics after comprehensive evaluation against multipliers with similar structures. Its introduced MED and MRED are only 3.32% and 0.10%, respectively. This evaluation result further validates the significant progress in the design and implementation of W1. W8_1 not only inherits W1’s high precision and reliability but also demonstrates exceptional performance in recursive operations, meeting the demands of more precise computational tasks.

4.1.2. Analysis of Error Compensation Performance in ECRS

The fully approximate multipliers W8_5 and W8_6, constructed entirely from approximate units, exhibit significant inherent error. To enhance their precision, the proposed ECRS based on the w3_2 approximate compressor is introduced, aiming to counteract the systematic negative error dominated by carry truncation. As shown in Table 6, for both the W8_5 and W8_6 series, the MED initially decreases and then increases with the number of compensated columns in the ECRS: W8_5 reaches its optimum at 3 compensated columns (rc3, MED = 908.25), while W8_6 reaches its optimum at 4 columns (rc4, MED = 1852.93). This trend indicates the existence of a clear optimal point for the ECRS; beyond this point, excessive positive error introduced by the compensation circuitry itself becomes the dominant error source. Consequently, the optimized W8_5rc3 and W8_6rc4 demonstrate an increased NoEB, verifying that ECRS can provide adaptive compensation tailored to the multiplier’s error characteristics, serving as an effective means for co-optimizing accuracy and energy efficiency.

Table 6. Error comparison of 8×8 multipliers with different numbers of compensation columns in Error-Compensated Recursive Structure.

Design	MED	NMED
W8_5	915.04	$1.41 \times {10}^{-2}$
W8_5rc1	913.28	$1.40 \times {10}^{-2}$
W8_5rc2	911.00	$1.40 \times {10}^{-2}$
W8_5rc3	908.25	$1.40 \times {10}^{-2}$
W8_5rc4	926.43	$1.42 \times {10}^{-2}$
W8_5rc5	1000.36	$1.54 \times {10}^{-2}$
W8_5rc6	1125.85	$1.73 \times {10}^{-2}$
W8_5rc7	1419.13	$2.18 \times {10}^{-2}$
W8_5rc8	2150.71	$3.31 \times {10}^{-2}$
W8_6	1884.31	$2.90 \times {10}^{-2}$
W8_6rc1	1882.00	$2.89 \times {10}^{-2}$
W8_6rc2	1877.19	$2.89 \times {10}^{-2}$
W8_6rc3	1862.78	$2.86 \times {10}^{-2}$
W8_6rc4	1852.93	$2.85 \times {10}^{-2}$
W8_6rc5	1875.69	$2.88 \times {10}^{-2}$
W8_6rc6	1951.36	$3.00 \times {10}^{-2}$
W8_6rc7	2143.28	$3.30 \times {10}^{-2}$
W8_6rc8	2565.08	$3.94 \times {10}^{-2}$

It is instructive to interpret the seemingly marginal 1.66% MED improvement of W8_6rc4 over W8_6 (from 1884.31 to 1852.93) through the lens of the error propagation model in Equation (8). In the fully approximate W8_6 configuration, all four sub-modules employ the W2 multiplier, which has an MED of 6.81 according to Table 4. The dominant error term in Equation (8) is therefore 2⁸ΔHH, which scales the error of the highest-weight aHbH block by a factor of 2⁸ = 256. This term alone introduces an error component on the order of 2⁸ × 6.81 to the total MED, fundamentally constraining the overall accuracy. The ECRS mechanism operates within the summation tree and can only compensate for errors arising from carry propagation during the addition of sub-module outputs. Its maximum possible positive compensation is bounded by the bit-weights of the columns where the w3_2 compressors are inserted. Consequently, the absolute error reduction remains small relative to the dominant 2⁸ΔHH term. Nevertheless, the U-shaped trend observed in Table 6—where the MED reaches a distinct minimum at rc4 for W8_6—indicates that the ECRS successfully balances under-compensation and over-compensation, identifying the configuration that minimizes error propagation within the summation tree under the given sub-module approximations. The limited percentage improvement is therefore a direct consequence of the error floor imposed by the W2 sub-modules. These observations confirm that the ECRS provides a systematic means of optimizing error performance in recursive approximate multipliers.

4.2. Hardware Analysis and Evaluation

For a fair comparison, all designs and benchmarks—including the competing approximate multipliers—were re-implemented at the gate level in Verilog HDL and synthesized using the identical TSMC 28 nm CMOS process and constraints. Logic synthesis was performed in the Synopsys Design Compiler with identical load and drive constraints, a unified optimization goal, and the compile_ultra strategy to ensure result comparability. All designs were synthesized under a standard 1V supply voltage at 25 °C (room temperature), with critical path delay adopted as the primary timing metric to accurately capture the circuit’s practical operating response. The Power–Delay Product (PDP), a key metric for evaluating hardware performance, was used to assess the energy efficiency of the designs. Furthermore, the Power–Area–Delay–Error Product (PADEP) was introduced to evaluate the overall performance of designs with different error levels, providing a more comprehensive assessment perspective. Here, NMED is selected as the error product term, and the formula is shown in (16). Table 7 summarizes the area, power, delay, PDP, and PADEP for the exact multiplier, the proposed 8×8 multipliers, and other comparative multipliers.

$$PADEP=Area\times Power\times Delay\times NMED$$

(16)

Table 7. Hardware performance metrics of different 8 × 8 multipliers under 1V supply voltage at 25 °C.

Design	Area (μm2)	Power (μW)	Delay (ns)	PDP	PADEP
Exact	152.84	67.79	0.79	50.84	0
CDM8_51 [22]	129.15	53.11	0.67	35.58	1.01
CDM8_74 [22]	109.12	45.14	0.58	26.18	6.86
CDM8_95 [22]	97.40	40.46	0.56	22.66	26.48
CDM8_aa [22]	76.90	32.58	0.54	17.59	98.76
PCTM8 [23]	135.20	59.21	0.63	36.71	0.29
M8-1 [24]	84.04	36.34	0.58	21.08	30.11
M8-2 [24]	72.58	29.18	0.52	15.17	30.84
M8-3 [24]	100.30	43.81	0.62	27.16	4.90
M8-4 [24]	92.86	38.03	0.55	20.92	6.22
M8-5 [24]	135.20	60.02	0.63	37.81	0.31
M8-6 [24]	132.80	58.76	0.63	37.02	0.47
AxRM1 [25]	137.34	60.00	0.71	42.60	1.52
AxRM2 [25]	122.22	58.76	0.69	36.31	19.08
AxRM3 [25]	117.81	51.82	0.63	37.31	22.86
N8-5 [26]	134.06	59.21	0.63	37.30	0.31
N8-6 [26]	130.79	57.92	0.63	36.49	0.41
N8-L1 [26]	77.62	29.03	0.45	13.06	2.64
N8-L2 [26]	73.21	26.81	0.45	12.06	3.00
W8_1	134.69	59.17	0.63	37.28	0.26
W8_2	130.91	57.92	0.63	36.49	0.48
W8_3	101.93	43.46	0.61	26.51	4.05
W8_4	87.44	37.49	0.57	21.37	5.98
W8_5	86.31	34.90	0.60	20.94	25.30
W8_6	66.78	28.22	0.52	14.67	28.42
W8_5ct3	78.75	29.96	0.54	16.18	17.84
W8_6ct4	63.25	23.49	0.46	10.81	19.82

Under the condition of 1V and 25 °C, compared to the exact multiplier, the W8_1 design exhibits an area reduction of 11.87%, a power saving of 12.71%, and a delay reduction of 20.25%, while also achieving the lowest PADEP. The favorable PADEP of W8_1 relative to comparably accurate designs such as PCTM8 [23] and N8-5 [26] is largely due to the w3_2 compressor, which maintains exact carry propagation while simplifying the sum logic, thereby reducing hardware overhead without compromising error performance. W8_6 achieves area, power, and delay reductions of 56.06%, 58.37%, and 34.18%, respectively, compared to the exact multiplier. Building upon this, the W8_6ct4 multiplier further optimizes area and power, resulting in the most compact and power-efficient design within this series. Specifically, it reduces area by 58.61%, power by 65.35%, and delay by 41.77% compared to the exact multiplier, leading to an optimal Power–Delay Product (PDP). Compared to N8-L2 [26], W8_6ct4 achieves area, power, and delay reductions of 12.85%, 19.50%, and 11.54%, respectively. These results indicate that W8_6ct4 achieves competitive hardware metrics, making it suitable for low-power applications. The reduction in hardware overhead primarily stems from the removal of numerous low-order logic cells via partial carry truncation. The decrease in delay is directly attributed to the replacement of complex full-adder chains with approximate logic units (such as OR gates and the w3_2 compressor) on the critical path, thereby shortening the propagation delay of the combinational logic. Additionally, the simplified structure reduces the overall switching activity of the circuit, which collectively contributes to the significant lowering of power consumption.

The hardware improvements observed for the proposed designs can be attributed to two architectural factors. First, the partial carry truncation in lower-significance columns reduces the number of logic gates along the critical path, directly lowering both area and delay. Second, the use of the w3_2 compressor in W8_1 replaces a full-adder structure with a simplified OR-based sum logic while preserving exact carry propagation, which maintains accuracy without incurring the full hardware cost of exact addition. The more aggressive truncation in W8_6ct4 further eliminates logic in higher-weight columns, resulting in additional area and power savings at the cost of increased error. These trade-offs are consistent with the design intent of providing configurable accuracy–hardware operating points.

For a comprehensive evaluation, the proposed approximate multipliers were compared with other designs in terms of the NoEB, area, power, and delay. A comparative visualization is provided in Figure 7, which illustrates the trade-offs between accuracy (represented by NoEB) and hardware performance for the different multipliers. In this representation, a position closer to the x-axis for a given NoEB value generally indicates more favorable hardware efficiency.

Figure 7. Comparative analysis of hardware efficiency versus accuracy for approximate 8 × 8 multipliers under 1V at 25 °C: (a) Area versus Number of Effective Bits; (b) Power consumption versus Number of Effective Bits; (c) Delay versus Number of Effective Bits. Designs located closer to the upper-left corner represent more favorable trade-offs. Several proposed configurations lie on or near this favorable region.

From a Pareto perspective, W8_1 and W8_6ct4 occupy distinct regions of the accuracy–efficiency space, illustrating that the configurable approach allows selection of different operating points according to application needs.

5. Experimental Validation in Application Scenarios

5.1. Validation in Image Processing: Quality Assessment

Vision provides one of the most direct human perceptions and is a rich source of information. The multiplication operator plays a critical role in image processing, as it underlies a vast number of arithmetic operations, such as convolution and filtering. For these reasons, this work investigates the integration of approximate multipliers into image smoothing operations. A two-dimensional rotationally symmetric a 3 × 3 Gaussian low-pass filter with a standard deviation of 1.5 is selected as the smoothing kernel. Its coefficients are scaled by 2¹⁰ and rounded to integers to make them suitable for an 8-bit input multiplier. This processing converts the kernel into an integer format for practical image blurring. The original and modified kernels are listed in Table 8. Furthermore, a 128 × 128 pixel grayscale house image was used, converted into a matrix via built-in MATLAB R2023b functions. Figure 8 presents a comparison of smoothed images generated by all approximate multipliers. The same processing is applied using an exact multiplier to serve as a reference for comprehensive comparison. By comparing these images against the reference image processed with the exact multiplier, quantitative metrics—namely the Structural Similarity Index (SSIM) and Peak Signal-to-Noise Ratio (PSNR)—are obtained. This process provides concrete numerical indicators for evaluating the performance of the approximate multipliers in this application [29]. The comparative results for all approximate multipliers are summarized in Table 9. It can be observed that designs including W8_1, W8_2, PCTM8, M8-5, and M8-6 achieve PSNR values greater than 50 dB and SSIM values above 99%. W8_1 achieves a PSNR of 54.73 dB and an SSIM of 99.93%, which are comparable to the exact multiplier (54.84 dB and 99.93%). These results indicate that the proposed carry-truncation schemes achieve hardware savings while maintaining PSNR above 50 dB and SSIM above 99%, demonstrating their suitability for image processing applications.

Table 8. Original and modified 3 × 3 Gaussian smoothing kernels.

Original			Modified
0.095	0.118	0.095	97	121	97
0.118	0.148	0.118	121	151	121
0.095	0.118	0.095	97	121	97

Figure 8. Comparison of smoothed images generated by exact multiplier and different approximate 8 × 8 multipliers.

Table 9. Image processing performance metrics of different 8 × 8 approximate multipliers.

Design	PSNR (dB)	SSIM (%)
PCTM8 [23]	54.73	99.93
M8-1 [24]	26.79	92.30
M8-2 [24]	20.58	85.25
M8-3 [24]	42.37	99.29
M8-4 [24]	42.66	99.14
M8-5 [24]	54.84	99.93
M8-6 [24]	52.60	99.90
AxRM1 [25]	49.24	99.80
AxRM2 [25]	38.94	98.74
AxRM3 [25]	37.29	98.69
N8-5 [26]	54.73	99.93
N8-6 [26]	52.58	99.90
N8-L1 [26]	44.59	99.36
N8-L2 [26]	42.64	99.08
W8-1	54.73	99.93
W8-2	52.60	99.90
W8-3	43.67	99.29
W8-4	42.72	99.15
W8-5	23.57	89.82
W8-6	20.40	85.91
W8-5rc3	23.84	89.96
W8-6rc4	20.43	86.08

5.2. Validation in Deep Learning: Impact on Quantized CNN Inference

To evaluate the practical utility of the approximate multipliers under complex computational loads, they were integrated into the quantized inference pipeline of CNN. The experiment adopted a static INT8 quantization strategy, where the critical INT8 × INT8 multiplication operations were replaced by the different approximate recursive multiplier modules proposed in this work [30]. All CNN models were trained prior to inference evaluation. Training was performed for 100 epochs with a batch size of 128, using the Adam optimizer and a learning rate of 0.01. The training was conducted using full-precision (FP32) arithmetic, after which the models were quantized to INT8 for inference. Through software simulation, a systematic test was conducted to assess their impact on the classification accuracy of various CNN models using the CIFAR-10 and MNIST datasets. The performance of the proposed multipliers across these different datasets is presented in Table 10 and Table 11, respectively.

Table 10. Classification accuracy of different CNN models on CIFAR-10 dataset with various 8 × 8 multipliers.

	Original Model	Quantification	W8_1	W8_2	W8_3	W8_4	W8_5	W8_5rc3	W8_6	W8_6rc4
resnet18	90.87%	90.66%	90.55%	90.25%	89.94%	89.70%	87.74%	89.38%	87.05%	86.15%
LeNet	74.33%	73.33%	72.56%	72.41%	72.92%	71.73%	72.57%	72.26%	71.99%	69.60%
AlexNet	85.31%	85.35%	85.16%	85.25%	85.13%	85.24%	84.38%	84.14%	84.53%	83.21%
VIT	79.63%	79.58%	79.59%	79.58%	79.43%	79.33%	78.58%	78.92%	78.72%	78.92%
googlenet	89.53%	89.64%	89.63%	89.55%	89.11%	88.65%	86.54%	87.57%	85.53%	83.68%
vgg16	90.73%	90.70%	90.65%	90.68%	90.50%	90.53%	89.91%	90.08%	89.66%	88.65%

Table 11. Classification accuracy of different CNN models on MNIST dataset with various 8 × 8 multipliers.

	Original Model	Quantification	W8_1	W8_2	W8_3	W8_4	W8_5	W8_5rc3	W8_6	W8_6rc4
resnet18	99.11%	99.05%	96.51%	96.53%	91.52%	87.10%	69.51%	83.55%	64.62%	55.08%
LeNet	99.25%	99.27%	99.14%	99.15%	99.12%	99.15%	99.05%	99.02%	98.99%	98.98%
AlexNet	99.31%	99.26%	99.11%	99.14%	99.08%	99.05%	99.06%	98.96%	99.05%	98.86%
VIT	99.06%	99.02%	98.50%	98.49%	98.47%	98.36%	98.05%	98.11%	97.95%	98.12%
googlenet	99.73%	99.73%	99.55%	99.55%	99.52%	99.49%	98.41%	99.51%	97.5%	99.41%
vgg16	99.06%	99.03%	98.5%	98.49%	98.47%	98.36%	98.05%	98.11%	97.95%	98.12%

W8_1 achieves a classification accuracy of 90.55% on ResNet-18 with CIFAR-10, which is 0.11 percentage points lower than the exact baseline (90.66%) and 0.56 percentage points higher than W8_2 (90.25%). As shown in the tables, on the relatively complex CIFAR-10 dataset, W8_1 maintains classification accuracy close to that of the exact INT8 multiplication across all tested models. This advantage stems from its core design strategy: employing the optimized approximate unit W1 only in the least significant aLbL block, while preserving exact computation in the high-weight blocks. This strategy confines the computational error to the lower effective bits of the output from the outset. It allows the error to be absorbed by the intrinsic error resilience of deep networks, thereby resulting in nearly no loss in final task accuracy. Notably, W8_1 exhibits a larger accuracy drop on ResNet-18 for MNIST (2.54%), which stems from error accumulation through residual connections, exacerbated by the near-perfect baseline accuracy of the dataset. A milder effect is observed for W8_1 on CIFAR-10 LeNet (0.77%), where the shallow architecture offers limited capacity for error absorption. These cases highlight that sensitivity to approximate multiplication varies with network topology and task difficulty.

W8_5 achieves a classification accuracy of 87.74% on ResNet-18 with CIFAR-10, which is 2.92 percentage points lower than W8_1, while W8_6rc4 achieves 86.15%, which is 4.40 percentage points lower. This reveals that in deep learning applications, the impact of computational error on system-level accuracy exhibits a non-linear, cumulative effect, which becomes particularly pronounced when processing complex data and deep networks. Conversely, in the simpler MNIST task, all types of approximate multipliers demonstrate high error tolerance, which further supports the principle that approximate computing requires targeted design tailored to specific application scenarios.

In summary, W8_1 successfully achieves an optimal balance between algorithmic accuracy and hardware overhead. Its design validates the effectiveness of the “precision-controllable approximate computing” concept: through meticulous management of error distribution, it achieves considerable reductions in power, area, and delay (as shown in Table 7) with almost no sacrifice in the classification performance of deep learning models. This makes it a highly promising arithmetic unit solution for high-efficiency edge AI inference accelerators.

6. Conclusions

This paper proposes a configurable approximate recursive multiplier architecture with an Error-Compensated Recursive Structure (ECRS). It aims to solve the error accumulation problem in traditional approximate recursive multipliers and achieve a flexible trade-off between hardware efficiency and computational accuracy for diverse error-resilient applications. The core innovations of this work include three aspects: first, a novel w3_2 approximate compressor with precise carry retention is designed, which introduces controllable positive errors to offset the negative systematic bias caused by carry truncation, while avoiding error propagation to higher bits; second, two configurable 4 × 4 approximate multiplier building blocks (W1 and W2) are optimized, which serve as the basis for constructing higher-order multipliers with tunable precision; third, the ECRS with dynamically optimized compensation columns is proposed, which fundamentally suppresses error accumulation in recursive multiplication, and the optimal number of compensation columns is derived through theoretical modeling and experimental verification (3 columns for W8_5 and 4 columns for W8_6).

Comprehensive cross-layer experiments are conducted to validate the effectiveness of the proposed design. At the circuit level, the high-precision configuration W8_1 achieves significant reductions in area, power and delay under the TSMC 28 nm CMOS process while maintaining higher computational accuracy than mainstream state-of-the-art approximate multipliers; the low-power configuration W8_6ct4 achieves aggressive hardware savings, making it suitable for ultra-low-power embedded scenarios. At the application level, W8_1 exhibits near-ideal performance in Gaussian image smoothing, with output quality almost identical to that of exact arithmetic. In quantized CNN inference, the proposed design shows strong adaptability across different datasets and network architectures: on the complex CIFAR-10 dataset, W8_1 maintains classification accuracy close to the exact baseline across mainstream deep models, with most configurations exhibiting a loss of 0.2% or less; on the MNIST dataset, it achieves negligible accuracy loss for lightweight models and maintains acceptable inference performance for all tested networks.

This work bridges the gap between circuit-level approximate arithmetic design and system-level application validation, and the proposed configurable multiplier family can be flexibly adapted to different accuracy and hardware overhead requirements. Compared with the exact multiplier, the high-precision configuration W8_1 reduces area, power, and delay by 11.87%, 12.71%, and 20.25%, respectively, while the low-power configuration W8_6ct4 achieves reductions of 58.61%, 65.35%, and 41.77%. The experimental results confirm that the proposed design provides a practical and efficient arithmetic unit solution for edge image processing, deep learning inference and other error-resilient computing scenarios. Future work will focus on three directions: (1) extending the ECRS-based architecture to 16 × 16 and 32 × 32 multipliers to adapt to wider high-precision computing scenarios; (2) exploring runtime-adaptive precision control schemes to dynamically adjust the multiplier configuration according to workload characteristics; and (3) integrating the proposed multipliers into a complete edge AI accelerator for tape-out and system-level verification.