TPSTA: A Tissue P System-Inspired Task Allocator for Heterogeneous Multi-Core Systems

Abstract

Heterogeneous multi-core systems (HMCSs) typically face a dilemma: heuristics (e.g., Linux CFS) are fast but blind to global constraints, while meta-heuristics (e.g., GAs) are globally optimal but too slow for real-time OS interaction. To bridge this gap without relying on “black-box” neural networks, we introduce the Tissue P System-Inspired Task Allocator (TPSTA). By mapping HMCS and parallel task scheduling to Tissue P System models and vectorized linear algebra problems, TPSTA achieves a computational complexity of $\mathrm{O}\left(\mathrm{M}/\mathrm{W}\right)$, effectively compressing the decision space. Our rigorous evaluation across four dimensions reveals a system strictly bound by physical constraints rather than algorithmic heuristics. (1) Under sufficient resource provisioning (four chips), TPSTA achieves a 0.00% Deadline Miss Ratio (DMR). Crucially, stress tests on constrained hardware (two chips) show graceful degradation to a 12.88% DMR, matching the optimal theoretical bound of EDF, whereas standard heuristics collapse to failure rates > 68%. On a massive 4096-core cluster, TPSTA outperforms the Linux GTS scalar baseline by 14.4×, maintaining low latency where traditional algorithms fail (>8 s). (3) Adaptability: The system demonstrates adaptive routing in handling hardware heterogeneity; without explicit rule-coding, it autonomously prioritizes data locality during NUMA transfers and migrates compute-bound tasks during thermal throttling events. (4) Physical Limits: Finally, our roofline analysis confirms that while the algorithmic speedup is theoretically linear, practical performance saturates at ~375× due to the Memory Wall, validating the isomorphism between synaptic bandwidth and hardware memory channels.

1. Introduction

With the breakdown of Dennard scaling and the stagnation of Moore’s Law [1], the microprocessor industry has been stepping towards heterogeneous multi-core systems (HMCSs). Modern architectures, such as ARM big.LITTLE and CPU-GPU heterogeneous clusters [2,3], promise to circumvent the “power wall” by mapping diverse workloads to the most energy-efficient processing units. However, unlocking this potential relies on efficient task scheduling, a problem theoretically proven to be NP-hard [4].

In practice, scheduling solutions for HMCS typically fall into three categories, each with distinct limitations:

The first category comprises System-Level Heuristics, such as the Linux Completely Fair Scheduler (CFS) [5] or list-based algorithms like HEFT (Heterogeneous Earliest Finish Time) [6]. These methods are computationally inexpensive and widely deployed. However, they rely on greedy local decisions and lack global foresight regarding task heterogeneity. As noted in comparative studies [7], such static heuristics often lead to resource fragmentation, resulting in high Deadline Miss Ratios (DMRs) under mixed workloads.

The second category involves meta-heuristic global optimization, such as Genetic Algorithms (GAs) [8] and Particle Swarm Optimization (PSO) [9]. While these bio-inspired methods can theoretically explore the search space to find near-optimal schedules, they suffer from prohibitive runtime overhead. The iterative convergence process often takes hundreds of milliseconds [10], which is unacceptable for real-time systems where tasks may have sub-millisecond deadlines.

The third and most recent category is Deep Reinforcement Learning (DRL) [11]. Approaches like DeepRM [12] have demonstrated the ability to learn complex scheduling policies directly from experience. However, DRL methods face significant deployment hurdles: they function as “black boxes” with poor interpretability [13], and more critically, they require extensive, computationally expensive offline training phases. This makes them ill-suited for embedded environments that demand training-free online adaptivity [14].

Consequently, there remains a critical gap for a scheduler that retains the global optimization capabilities of bio-inspired methods without the latency costs of GAs or the training burden of DRL.

Membrane computing (P Systems), initiated by Păun [15,16], offers a new view to bridge this gap. Inspired by the biochemical processes in living cells, P Systems process information through parallel distributed rule evolution. Specifically, the Tissue-like P System [17], where cells communicate via channels (synapses), creates a natural topological isomorphism with multi-core SoCs. Prior research has successfully applied membrane algorithms to combinatorial optimization problems, including the Job Shop Scheduling Problem (JSSP) [18], data clustering [19,20], fault classification in photovoltaic arrays [21], image processing [22], the nurse rostering problem [23], and quality of service (QoS)-aware cloud web service composition [24].

Despite these successes, applying P Systems to hard real-time OS scheduling faces two unresolved challenges: conventional simulation frameworks (e.g., P-Lingua [25], SNPCS [26], and MeCoSim [27]) emulate parallel membrane rules serially on CPUs. This results in execution overheads similar to GAs, negating the theoretical speed advantage of P Systems. Most existing membrane algorithms [28,29] focus on “best-effort” makespan minimization rather than strict deadline constraints required by safety-critical systems. Recent works [30,31] have applied membrane computing models to IoT, but they typically focus on multi-objective optimization rather than the strict microsecond-level latency required for kernel scheduling.

To address these challenges, this paper proposes the Tissue P System-Inspired Task Allocator (TPSTA). We introduce a Vectorized Rule Execution Engine that replaces iterative evolution with matrix algebra, enabling maximal parallelism with negligible overhead. Furthermore, we design an urgency-driven membrane potential mechanism to strictly enforce QoS.

The main contributions of this paper are as follows:

Bio-Silicon Mapping: We establish a formal mapping between Tissue P Systems and heterogeneous scheduling, where symport/antiport rules act as hardware interactions.

Vectorized Parallelism: We propose a matrix-based rule firing algorithm that achieves a ~14.4× speedup over Linux GTS, solving the “simulation inefficiency” bottleneck.

Statistical Reliability: Validated by comparison with five different systems, TPSTA achieves a 0.00% Deadline Miss Ratio under sufficient resources, significantly outperforming traditional heuristics (16–23% failure rates) while maintaining training-free interpretability compared to DRL.

The remainder of this paper is organized as follows:

Section 2 reviews related work in heterogeneous scheduling and provides the mathematical preliminaries of Tissue-like P Systems.

Section 3 formulates the heterogeneous scheduling problem and maps it to the P System topology.

Section 4 details the proposed TPSTA framework, elaborating on the Vectorized Rule Execution Engine and the urgency-driven membrane potential mechanism.

Section 5 presents the experimental setup and performance metrics, comparing TPSTA against state-of-the-art baselines.

Finally, Section 6 concludes the paper and outlines directions for future research.

2. Background and Related Works

2.1. Task Scheduling in Heterogeneous Systems

The scheduling problem in heterogeneous multi-core systems (HMCSs) is formally defined as mapping a directed acyclic graph (DAG) of tasks onto a set of unrelated processors to minimize makespan or energy. Existing approaches can be broadly categorized into three classes:

Heuristic Approaches. Static heuristics, such as the Heterogeneous Earliest Finish Time (HEFT) [6] and the Linux Completely Fair Scheduler (CFS) [5], employ greedy strategies. HEFT, for instance, ranks tasks by upward rank and maps them to the processor minimizing the Earliest Finish Time. While these algorithms have low time complexity O(N·P), they inherently lack a global optimization perspective. Consequently, they are prone to local optima, often causing resource fragmentation where high-performance cores are blocked by low-priority tasks [7].

Meta-Heuristic Approaches. To overcome local optima, evolutionary algorithms like Genetic Algorithms (GAs) [8] and Particle Swarm Optimization (PSO) [9] have been widely adopted. These methods utilize population-based search to explore the solution space globally. However, their reliance on iterative selection, crossover, and mutation operations introduces significant computational overhead. For real-time systems, the latency required for a GA to converge (typically hundreds of milliseconds) often exceeds the deadlines of the tasks themselves, rendering them impractical for online scheduling [10].

Learning-Based Approaches. Recently, Deep Reinforcement Learning (DRL) has shown promise in learning scheduling policies [11]. While DRL can outperform heuristics, it requires extensive offline training and large amounts of labeled data. Furthermore, the “black-box” nature of neural networks raises concerns regarding interpretability and safety in mission-critical environments [12].

In summary, a trilemma exists in current HMCS scheduling: schedulers cannot simultaneously achieve low latency (like heuristics), global optimization (like GA), and training-free explainability (unlike DRL). This paper aims to address these trade-offs by introducing a lightweight, vectorized bio-inspired approach.

2.2. Tissue-like P Systems in Optimization

Membrane computing, or P Systems, is a distributed parallel computing paradigm inspired by the structure and functioning of living cells [15,16]. Unlike Cell-like P Systems which use a hierarchical membrane structure, Tissue-like P Systems [17,31] model a network of processors (cells) communicating via channels (synapses).

According to classical definitions in membrane computing [15,16,32,33], a Tissue-like P System of degree m is a construct:

Π = (O, E, M₁, …, M_m, R, i_out)

where

(1)

O is the finite alphabet of objects. In our scheduling model, objects represent tasks and control signals.

(2)

E ⊆ O represents a set of objects initially placed in the environment of the system, all of which are available in a certain number of copies.

(3)

M_i (1 ≤ i ≤ m) represents the finite multiset of objects initially present in cell i.

(4)

R is a finite set of rules of the following forms:

–

Symport rules: (i, u/λ, j), where 0 ≤ i ≠ j ≤ m, u ∈ O;

–

Antiport rules: (i, u/v, j), where 0 ≤ i ≠ j ≤ m, u, v ∈ O.

When a symport rule (i, u/λ, j) is applied, the multiset u of objects is sent from region i to region j, while an antiport rule (i, u/v, j) indicates that the multiset u of objects is sent from region i to region j, and the multiset v of objects is sent from region j to region i simultaneously.

(5)

i_out ∈ {0, 1, 2, …m} represents the finite multiset of objects initially present in cell i.

Tissue-like P Systems have demonstrated strong combinatorial optimization capabilities. For instance, Tian et al. [18] applied hybrid membrane algorithms to JSSP. Recent works by Tuo et al. [30,31] extended this to IoT task offloading, considering energy and security constraints. Sharif et al. [23] utilized it for nurse rostering.

However, these approaches typically rely on abstract software simulations (e.g., MeCoSim [25]) that execute rules sequentially on a CPU. This “simulation overhead” creates a performance bottleneck, preventing membrane algorithms from being used as real-time OS schedulers.

2.3. From Theoretical Parallelism to Hardware-Aware Scheduling

A fundamental feature of P Systems is the maximally parallel execution mode [15,16]. In a theoretical membrane system, all applicable rules fire simultaneously in a single time step, regardless of the system size. However, implementing this non-deterministic parallelism on conventional von Neumann architectures presents a significant challenge. Standard simulation tools typically serialize these parallel rules into sequential CPU instructions, causing the execution overhead to scale linearly with the number of objects ($O\left(N\right)$), which negates the theoretical speed advantage of membrane computing. To bridge the gap between theoretical parallelism and physical execution, modern processor architectures offer Single-Instruction, Multiple-Data (SIMD) extensions, such as Intel AVX-512 [34]. SIMD allows the processor to perform the same operation on multiple data points in a single clock cycle. This hardware capability provides a physical realization of the “maximal parallelism” concept: by mapping membrane objects to vector registers, the evolution of the entire system can be computed in constant or near-constant time steps, governed by the Roofline Model [35] rather than scalar instruction latency.

Furthermore, the deployment of such specialized scheduling logic requires bypassing the rigidity of traditional kernel-space schedulers. The feasibility of user-space scheduling delegation has been validated by Google’s GhOSt [36] framework, which demonstrates that delegating scheduling decisions to user-space agents can achieve microsecond-scale granularity while maintaining system stability. This architectural trend is currently being standardized in the Linux kernel through the eBPF (Extended Berkeley Packet Filter) [37] ecosystem and the extensible scheduler class [38] (sched_ext), enabling the safe injection of custom, high-performance policies like TPSTA without modifying the kernel source code.

3. System Modeling

In this section, we formulate the heterogeneous scheduling problem and establish a formal mapping between the hardware architecture and the proposed Tissue P System model.

3.1. From Bio-Inspired Membrane Models to Silicon Chips

Before formally defining the system model, we establish the theoretical foundation for mapping heterogeneous multi-core architectures to membrane computing. As illustrated in Figure 1, there exists a natural topological isomorphism between a heterogeneous multi-core system (HMCS) and a Tissue-like P System.

Figure 1. This shows an isomorphism between a heterogeneous multi-core system and bio-inspired Tissue-like P System. (a) Physical Architecture: Heterogeneous cores (CPU/GPU) connected via high-speed interconnects. (b) Bio-Inspired Abstraction: Each core maps to a membrane, and interconnects map to synaptic channels (syn).

A physical cluster consists of discrete processing units (cores) communicating via a shared interconnect (bus/NoC). Similarly, a Tissue P System consists of discrete membrane regions (cells) exchanging objects via synaptic channels. This graph-based topology (${\mathsf{\sigma }}_{\mathrm{i}}\leftrightarrow {\mathsf{\sigma }}_{\mathrm{j}}$) mirrors the hardware layout ($\mathrm{C}\mathrm{o}\mathrm{r}{\mathrm{e}}_{\mathrm{i}}\leftrightarrow \mathrm{C}\mathrm{o}\mathrm{r}{\mathrm{e}}_{\mathrm{j}}$), unlike the hierarchical tree structure of Cell-like P Systems, which fails to capture the peer-to-peer nature of modern SoCs. Functional Similarity: In hardware, task execution is driven by the interaction between data (workload) and functional units (ALUs). In membrane computing, system evolution is driven by the reaction between objects (tasks) and rules (instructions). HMCS relies on parallelism (SIMD/MIMD) to maximize throughput. Tissue P Systems rely on biological guaranteed maximal parallelism, where all applicable rules fire simultaneously. Based on these intrinsic similarities, we abstract the HMCS as a Tissue P System-inspired struct, where physical constraints (bandwidth, latency) are modeled as synaptic properties, and scheduling decisions are modeled as evolutionary rules. This abstraction allows us to leverage the formal verification and parallel execution properties of P Systems to solve the NP-hard scheduling problem.

3.2. Heterogeneous Hardware Abstraction

TPSTA assumes a Run-to-Completion (RTC)/non-preemptive execution model. In modern HMCS, preempting hardware accelerators (e.g., GPUs, NPUs, and DSPs) incurs prohibitive state-saving overheads. Modeling membrane rules as non-preemptive atomic reactions aligns with the high-throughput, latency-sensitive nature of heterogeneous dispatching. Consider a heterogeneous computing cluster consisting of $\mathrm{M}$ processing cores, denoted as $\mathcal{P}=\{p_1,p_2,\dots ,p_M\}$. Unlike traditional scheduling models that represent cores as discrete objects (Array of Structures, AoS), which suffer from scalar processing bottlenecks, we model the system state using a Structure of Arrays (SoA) layout to enable SIMD parallelism.

The system state at time $\mathrm{t}$ is defined by three high-dimensional feature vectors, aligned with the hardware vector register width $W$ (e.g., $W=16$ for AVX-512):

• Capability Vector ($\mathit{C}\in {\mathit{R}}^{\mathit{m}}$): This represents the computational throughput of each core (e.g., GFLOPS):

$$\mathit{C}={\left[c_1,c_2,\dots ,c_M\right]}^{\mathrm{T}}$$

2.

Load Vector ($\mathit{L}\in R^m$): This records the busy-until timestamp of each core, indicating when it will become available:

$$\mathit{L}={\left[l_1,l_2,\dots ,l_M\right]}^{\mathrm{T}}$$

3.

Bandwidth Vector ($\mathit{B}\in R^M$): This denotes the data transfer rate of the interconnect associated with each core:

$$\mathit{B}={\left[b_1,b_2,\dots ,b_m\right]}^T$$

This vectorized abstraction allows the scheduler to evaluate the suitability of all $M$ cores simultaneously using matrix algebra, rather than iterating through them sequentially.

3.3. Task Model and Optimization Goal

The workload consists of a stream of independent tasks $\mathcal{T}$. Each task $T_k$ is characterized by a tuple $\left(w_k,d_k,D_k\right)$, where $w_k$ is the computational workload, $d_k$ is the data volume, and ${\mathrm{D}}_{\mathrm{k}}$ is the absolute deadline. The Estimated Finish Time (EFT) of task ${\mathrm{T}}_{\mathrm{k}}$ on core $\mathrm{i}$ is modeled as follows:

$$EFT\left(T_k,\mathrm{i}\right)=\max \left(\mathrm{A}\mathrm{r}\mathrm{r}\mathrm{i}\mathrm{v}\mathrm{a}\mathrm{l}\left({\mathrm{T}}_{\mathrm{k}}\right),{\mathrm{l}}_{\mathrm{i}}\right)+{\displaystyle \frac{w_k}{c_i}}+{\displaystyle \frac{d_k}{b_i}}$$

The primary scheduling goal of TPSTA is to satisfy the hard real-time constraints of safety-critical workloads. We define the Deadline Miss Ratio (DMR) as the fraction of tasks that fail to complete before their absolute deadlines.

Formally, let $\mathcal{M}:\mathcal{T}\to \mathcal{P}$ denote the mapping strategy determined by the scheduler. The objective function is to minimize:

$$\mathrm{Minimize} {\mathcal{J}}_{\mathcal{D}\mathcal{M}\mathcal{R}}={\displaystyle \frac{1}{\mathrm{N}}}\sum _{\mathrm{k}=1}^{\mathrm{N}}\mathrm{I}\left(\mathrm{E}\mathrm{F}\mathrm{T}\left({\mathrm{T}}_{\mathrm{k}},\mathcal{M}\left({\mathrm{T}}_{\mathrm{k}}\right)\right)>{\mathrm{D}}_{\mathrm{k}}\right)$$

where

$\mathrm{N}$ is the total number of tasks in the batch.

$\mathrm{E}\mathrm{F}\mathrm{T}\left({\mathrm{T}}_{\mathrm{k}},\mathcal{M}\left({\mathrm{T}}_{\mathrm{k}}\right)\right)$ is the Estimated Finish Time of task $T_k$ on its assigned core.

${\mathrm{D}}_{\mathrm{k}}$ is the absolute deadline of task ${\mathrm{T}}_{\mathrm{k}}$.

$\mathrm{I}\left(\cdot \right)$ denotes the Indicator Function, which evaluates to 1 if the condition (Deadline Miss) is true, and 0 otherwise.

Unlike “best-effort” schedulers (e.g., CFS) that minimize average makespan, TPSTA treats ${\mathcal{J}}_{\mathcal{D}\mathcal{M}\mathcal{R}}$ as the dominant loss function, prioritizing deadline compliance over resource utilization.

3.4. Formal Definition of TPSTA

To solve the scheduling problem, we construct the Tissue P System-Inspired Task Allocator (TPSTA) of degree m. Formally, the system is defined as a tuple:

$${\mathsf{\Pi }}_{TPSTA}=\left(O,E,{\mathsf{\sigma }}_1,\dots ,{\mathsf{\sigma }}_m,syn,\mathcal{R},i_{out}\right)$$

where

$\mathrm{O}$ (Alphabet): The finite set of objects representing tasks, control signals (e.g., update, ack), and resource tokens.

$E \subseteq O$ (Environment): The set of objects present in the environment in arbitrary copies (representing the incoming task queue).

${\mathsf{\sigma }}_1,\dots ,{\mathsf{\sigma }}_m$ (Cells): The $\mathrm{m}$ cells of the system. Each cell ${\mathsf{\sigma }}_{\mathrm{i}}$ represents a physical processing core ${\mathrm{p}}_{\mathrm{i}}$. The contents of ${\mathsf{\sigma }}_{\mathrm{i}}$ at time $\mathrm{t}$ represent the local task queue and the core’s current status (capability/load).

$syn \subseteq \{1, \dots , m\} \times \{1, \dots , m\}$ (Synapses): The set of synapses (channels) connecting the cells. $\mathrm{s}\mathrm{y}\mathrm{n}$ represents the physical interconnects (e.g., PCIe, NoC, or shared memory bus) allowing data and control signals to flow between the scheduler (environment) and cores.

$\mathcal{R}$ (Rules): The finite set of evolution rules, combining both communication and computation logic:

Symport Rules (${\mathcal{R}}_{\mathcal{s}\mathcal{y}\mathcal{m}}$): $\left(i,u,j\right)$ or $\left(\mathrm{e}\mathrm{n}\mathrm{v},\mathrm{u},\mathrm{j}\right)$. This is used for Task Dispatch, moving a task object $\mathrm{u}$ from the environment to cell $\mathrm{j}$.

Antiport Rules (${\mathcal{R}}_{\mathcal{a}\mathcal{n}\mathcal{t}\mathcal{i}}$): $\left(\mathrm{i},\mathrm{u}/\mathrm{v},\mathrm{j}\right)$. This is used for State Synchronization, where a cell $\mathrm{i}$ exchanges status objects $\mathrm{u}$ with the environment’s credit objects $\mathrm{v}$ to update the global state vectors $\mathrm{C}$ and $\mathrm{L}$.

$i_{out}$ (Output): The region where the results (completed tasks) are collected.

4. TPSTA Framework

In this section, we present the implementation details of TPSTA. We first introduce the decoupled scheduling logic from the OS kernel to enable high-frequency decision-making. Then we detail the Vectorized Rule Execution Engine, which transforms the biological evolution of P Systems into efficient linear algebra operations utilizing hardware SIMD instructions.

4.1. Decoupled Scheduling Framework

To overcome the limitations of kernel-space scheduling (e.g., limited floating-point support for matrix operations), TPSTA proposes a Decoupled Decision Architecture. Conceptually, this aligns with the emerging “Sidecar” pattern in distributed systems, where the complex logic (the bio-inspired brain) is separated from execution (the kernel).

Hardware metrics (temperature, IPC) are collected via a low-overhead telemetry agent. In our model, this corresponds to the antiport rules (${\mathcal{R}}_{\mathcal{a}\mathcal{n}\mathcal{t}\mathcal{i}}$), which continuously refresh the global state vectors $\mathbf{C}\mathrm{and}\mathbf{L}$ in a shared memory region. This design avoids blocking the critical path of task submission.

The TPSTA scheduler operates as a logical user-space agent. By decoupling the decision logic from the kernel interrupt context, the scheduler gains the ability to utilize SIMD instructions (AVX-512) and high-performance linear algebra libraries, which are typically restricted in Ring 0.

While this architecture supports physical deployment via modern kernel bypass techniques, this paper focuses on evaluating the algorithmic upper bounds and vectorization scalability. Therefore, we evaluate the system using a high-fidelity Discrete Event Simulation (DES) to isolate the scheduling logic from OS-specific noise (see Section 5).

4.2. Vectorized Rule Execution Engine

As non-deterministic, iterative evolution steps of traditional P Systems are not suitable for task scheduling, TPSTA employs deterministic matrix algebra while running the P System in a Bounded Maximal Mode [33].

Instead of evaluating rules sequentially ($O\left(M\right)$), we treat the entire system evolution as a single vector transformation ($O\left(M/W\right)$).

Before evaluating the completion time, we introduce three Correction Vectors to model the complex hardware behaviors observed in heterogeneous clusters (e.g., Hyper-Threading contention, NUMA topology).

(1)

Contention-Aware Capability ($\mathsf{\alpha }$)

To account for SMT (Simultaneous Multi-Threading) contention, we define a Contention Vector $\mathsf{\alpha }\in R^m$. If a core’s sibling thread carries a heavier load, the effective capability is penalized:

$${\alpha }_i=1.0+0.5\cdot S_i, S_i\in \left\{\mathrm{0,1}\right\}$$

(2)

Heterogeneity Compatibility ($\mathsf{\beta }$)

We define a Compatibility Vector $\mathsf{\beta }\in {\mathrm{R}}^{\mathrm{m}}$ to enforce hardware affinity (e.g., preventing GPU tasks from running on CPUs). A large soft penalty ($\mathsf{\kappa }\gg 1$) is applied to mismatched types:

$${\mathsf{\beta }}_i=\mathsf{\kappa }\hspace{1em}\mathrm{if} \mathrm{Type}\left(p_i\right)\ne \mathrm{Type}\left(Task\right)\hspace{1em}\mathrm{else} 1.0$$

(3)

Locality Coefficient ($\mathsf{\gamma }$)

To minimize data movement costs, we introduce a Locality Vector $\mathsf{\gamma }\in {\mathrm{R}}^{\mathrm{m}}$. If the target core resides on the same chip as the task’s data (Affinity Chip), the bandwidth cost is reduced by a factor $\gamma$ (e.g., 0.5):

$${\mathsf{\gamma }}_i=\mathsf{\delta }\hspace{1em}\mathrm{if} \mathrm{ChipID}\left(p_i\right)==\mathrm{AffinityID}\left(Task\right)\hspace{1em}\mathrm{else} 1.0$$

When a task $T_k=\left(w_k,d_k,D_k\right)$ arrives, the system must evaluate the Estimated Finish Time (EFT) for all $M$ cores simultaneously. For an incoming task $T_k$ with workload $w_k$ and data volume $d_k$, the EFT vector $\mathrm{E}\in R^m$ is computed via a fused operation. To avoid expensive division instructions (~14 cycles), we pre-compute the reciprocal vectors $C^{\circ -1}\mathrm{and}{B}^{\circ -1}$ during initialization. The runtime evaluation becomes a sequence of fused multiply–add (FMA) operations (~4 cycles) with a relative error (<$2^{-14}$) that is negligible for scheduling heuristics:

$$E=\max \left(t_{now},L\right)+\underset{\mathrm{Compute} \mathrm{Time}}{\underbrace{\left(w_k\odot C^{\circ -1}\odot \mathsf{\alpha }\odot \mathsf{\beta }\right)}} + \underset{\mathrm{Data} \mathrm{Time}}{\underbrace{\left(d_k\odot B^{\circ -1}\odot \mathsf{\gamma }\right)}}$$

where

$\odot$ denotes element-wise scalar-vector multiplication (broadcasting).

${\left(\cdot \right)}^{\circ -1}$ denotes the Hadamard Inverse (element-wise reciprocal).

$\max \left(\cdot \right)$ is the element-wise maximum operation.

To enforce the minimum Deadline Miss Ratio (DMR), we introduce an urgency-driven filtering mechanism. We define a penalty vector $\mathrm{P}$ that acts as a “repulsive force” in the membrane system:

$$P_i=\mathrm{\infty },\hspace{1em}\hspace{1em}\mathrm{i}\mathrm{f} E_i>D_k; otherwise P_i=0$$

The final Scheduling Score Vector ($S$) is derived by

$$S=E+P$$

In the vectorized implementation, this conditional logic is executed using masked operations. We generate a predicate mask $\mathrm{K}=\left(\mathrm{E}>{\mathrm{D}}_{\mathrm{k}}\right)$. Cores violating the deadline are masked out (set to infinity) in a single clock cycle, effectively “dissolving” the invalid synaptic channels. The scheduler then selects the core with the minimum score using a vectorized reduction (min-scan) operation.

4.3. Complexity Analysis

We analyze the time complexity of TPSTA relative to the standard scalar approach (e.g., Linux GTS). Let $\mathrm{N}$ be the number of tasks and $\mathrm{M}$ be the number of cores.

Scalar Scheduling: This requires iterating through all cores for each task.

$$T_{scalar}=O\left(N\cdot M\right)$$

Vectorized Scheduling: By processing cores in batches equal to the SIMD width $\mathrm{W}$ (e.g., $\mathrm{W}=16$), the loop count is reduced by a factor of $W$.

$$T_{vector}=O\left(N\cdot ⌈{\displaystyle \frac{M}{W}}⌉\right)$$

While the theoretical speedup is linear with $W$, practical performance is constrained by the Roofline Model, specifically the memory bandwidth required to load state vectors $\mathit{L}$ and $\mathit{C}$ from DRAM to L1 cache. However, as demonstrated in our experiments (Section 5), for typical cluster sizes ($M=4096$) and vector widths ($W=16$), the problem remains compute-bound, allowing TPSTA to achieve near-linear speedups before hitting the Memory Wall.

Then we have the TPSTA Algorithm as Algorithm 1:

Algorithm 1: Vectorized TPSTA Scheduling Flow

Input: Task Stream $\mathcal{T}$, Hardware State Vectors C, L, B

Output: Mapping Decisions $\mathcal{M}\mathrm{x}$

1. //Initialization & Preprocessing

Sort $\mathcal{T}$ by Deadline (EDF Policy);

Pre-compute Reciprocals: $C_{inv}\leftarrow 1/C, B_{inv}\leftarrow 1/B$

2. //Main Dispatch Loop (for each Task $T_k$)

//Step A: Context Vectorization

α←CheckHyperThreadingContention (L);

β←CheckHeterogeneityMatch ($T_k$ type);

γ←CheckNumaLocality ($T_k$ affinity);

//Step B: Fused EFT Calculation (SIMD FMA)

//Calculate $T_{\mathrm{exec}}$ and E in parallel

$T_{\mathrm{e}\mathrm{x}\mathrm{e}\mathrm{c}}\leftarrow \left({\mathrm{w}}_{\mathrm{k}}\odot {\mathrm{C}}_{\mathrm{i}\mathrm{n}\mathrm{v}}\odot \mathsf{\alpha }\odot \mathsf{\beta }\right)+\left({\mathrm{d}}_{\mathrm{k}}\odot {\mathrm{B}}_{\mathrm{i}\mathrm{n}\mathrm{v}}\odot \mathsf{\gamma }\right);$

$E\leftarrow \max \left(t_{now},L\right)+T_{exec};$

//Step C: Urgency-Driven Masking

// Filter out deadline violations

$M_{mask}\leftarrow \left(E>D_k\right);$

$S\leftarrow E+\left(M_{\mathrm{m}\mathrm{a}\mathrm{s}\mathrm{k}}\cdot \mathrm{\infty }\right);$

//Step D: Reduction & Commit

${\mathrm{p}}_{\mathrm{b}\mathrm{e}\mathrm{s}\mathrm{t}}\leftarrow \arg \min \left(\mathrm{S}\right);$

if $S\left[p_{best}\right]<\mathrm{\infty }$

then Assign ${\mathrm{T}}_{\mathrm{k}}\to {\mathrm{p}}_{\mathrm{b}\mathrm{e}\mathrm{s}\mathrm{t}}$        // symport rule

else Trigger Fallback    // Reject Task

The calculation of $\mathrm{E}$ is performed using element-wise vector operations. In a physical implementation (e.g., using Intel AVX-512 or ARM SVE), the reciprocal vectors ${\mathbf{C}}^{\circ -\mathbf{1}}$ are pre-computed, allowing $\mathrm{E}$ to be executed as a fused multiply–add (FMA) instruction sequence. The conditional logic for deadline enforcement is implemented as a branchless masked operation. The predicate mask $M_{mask}$ acts as a biological “filter,” effectively dissolving connections to unsuitable cores without pipeline stalls. The selection of the best core utilizes a parallel reduction tree (e.g., vminps), which has a logarithmic depth of $\mathrm{O}\left(\log W\right)$ rather than the linear scan $\mathrm{O}\left(M\right)$ used in traditional schedulers.

5. Experimental Evaluation

In this section, we validate the performance of TPSTA through a rigorous Discrete Event Simulation (DES) framework based on Python 3.12 and NumPy (to provide Vertex Calculation Support). The experiments are designed to assess the scheduler’s behavior across four dimensions: (1) algorithmic efficiency vs. optimality trade-offs, (2) scalability with cluster size, (3) adaptability to heterogeneous hardware events (NUMA/DVFS), and (4) parallel batch size simulation simulating different SIMD widths. The Simulator source codes can be downloaded, and the URL link is in the Supplementary Materials section.

5.1. Methodology and Experimental Setup

As discussed, NumPy’s BLAS-optimized matrix operations serve as a performance proxy for hardware vector units (AVX-512), allowing us to accurately evaluate the $\mathrm{O}\left(\mathrm{M}/\mathrm{W}\right)$ complexity of the TPSTA engine.

The default experimental platform is configured as a Heterogeneous NUMA Cluster comprising 40 processing cores distributed across four NUMA nodes (chips). Each chip mimics a modern heterogeneous SoC (system-on-chip) layout with the following resource partition:

Accelerators: 1 $\times$ GPU ($\mathrm{C}=12.0 \mathrm{G}$ LOPS, $\mathrm{B}=200$ GB/s) + 1 $\times$ NPU ($C=8.0$ GFLOPS, $B=150$ GB/s).

General-Purpose Cores: 4 $\times$ performance cores (Big, $\mathrm{C}=4.0$) + 4 $\times$ efficiency cores (Small, $\mathrm{C}=1.5$).

Total Topology: 4 Chips $\times$ 10 Cores = 40 Cores.

In a real-world Linux kernel deployment, this topological information (core types, affinities, and latencies) is automatically discovered via the ACPI SRAT (System Resource Affinity Table) and SLIT (System Locality Distance Information Table) during boot time. Our simulator just mocks these hardware description tables.

To ensure physical realism, the penalty coefficients in our Cost Model (Section 4.2) are calibrated against empirical hardware behaviors:

(1)

Hyper-Threading Contention ($\mathsf{\alpha }=1.5$):

We set the SMT penalty to 1.5 based on the resource partitioning of superscalar architectures. Since logical threads share the Re-order Buffer (ROB) and Execution Ports, fully saturating two threads typically yields only ∼$1.35\times$ total throughput. Thus, the effective single-thread performance drops to $1.35/2\approx 0.67$, corresponding to a latency penalty of $\mathsf{\alpha }\approx 1/0.67 \approx 1.5$.

(2)

Heterogeneity Mismatch ($\beta \in \{8, 20\}$):

Executing specialized tasks on general-purpose CPUs incurs a massive penalty due to the lack of hardware acceleration (e.g., Tensor Cores). We define ${\mathsf{\beta }}_{\mathrm{G}\mathrm{P}\mathrm{U}}=20.0$ and ${\mathsf{\beta }}_{\mathrm{N}\mathrm{P}\mathrm{U}}=15.0$ to model the orders-of-magnitude slowdown caused by software-based instruction emulation (e.g., executing CUDA kernels via software interpretation on a CPU).

(3)

NUMA & Locality ($\mathsf{\gamma }\in \{0.5,2.0\}$):

Remote Access ($\mathsf{\gamma }=2.0$): Accessing memory across NUMA nodes via interconnects (e.g., Intel UPI or AMD Infinity Fabric) typically incurs a $1.5\times \sim 2.5\times$ latency overhead compared to local DRAM access. We standardize this penalty at 2.0.

Local Affinity ($\mathsf{\gamma }=0.5$): Conversely, tasks scheduled on their affinity node benefit from maximizing L3 cache hits, modeled as a cost reduction factor.

(4)

Thermal Throttling (DVFS):

In fault injection scenarios (Exp 3), we model thermal throttling by reducing a core’s capability $C$ to 10% of its base value. This reflects the aggressive frequency scaling (e.g., 3.0 GHz $\to$ 300 MHz) triggered by hardware PROCHOT# signals during overheating events.

5.2. Performance Parity and Reliability

To benchmark the scheduler’s performance in a realistic heterogeneous environment, we configured a 40-core heterogeneous cluster (4 NUMA chips × 10 cores/chip). Each chip contains a diverse mix of one GPU, one NPU, four Big Cores (HT-enabled), and four Small Cores. The workload consists of $N=800$ tasks generated using a Pareto distribution to simulate long-tail datacenter traffic types (CPU-Bound, IO-Bound, and Accelerator-Specific).

We compare TPSTA against five representative baselines, covering the spectrum of scheduling strategies:

Real-Time Policies: EDF (Earliest Deadline First) and RM (Rate Monotonic), representing optimal uniprocessor bounds [39].

Heuristics: Linux GTS (Global Task Scheduling, approximating CFS with $\mathrm{O}\left(\mathrm{M}\right)$ complexity) [40] and K8s (Least Requested, representing cluster bin-packing) [41].

Meta-Heuristics: IM-GA (Immunity Genetic Algorithm), representing the theoretical upper bound of global optimization quality [42].

We evaluate three key metrics:

Deadline Miss Ratio (DMR): The strict percentage of tasks violating hard deadlines (lower is better).

Makespan: The total time to complete the batch (lower is better).

Decision Overhead: The wall-clock time consumed by the scheduling algorithm itself.

Results are shown in Table 1 and Figure 2, comparing TPSTA against five baselines.

Table 1. Performance comparison on mixed workload (30 independent runs, N = 800).

Algorithm	Makespan (ms) [Mean ± Std]	DMR (%) [Mean ± Std]	Overhead (ms) [Mean ± Std]	Characteristics
TPSTA	537.81 ± 83.18	0.00% ± 0.00%	53.03 ± 15.28	Vectorized, Global
EDF	537.81 ± 83.18	0.00% ± 0.00%	65.74 ± 17.84	Local, Deadline-based
RM	535.47 ± 78.04	0.00% ± 0.02%	67.81 ± 18.51	Local, Static Priority
Linux GTS	495.58 ± 70.99	49.63% ± 3.07%	66.09 ± 18.14	Greedy, Red-Black Tree
K8s	2278.05 ± 728.94	50.22% ± 5.03%	4.91 ± 1.51	Bin-packing (LeastReq)
IM-GA	14,239.78 ± 1578.01	89.48% ± 1.79%	777.03 ± 193.31	Iterative Evolution

Figure 2. Performance comparison on mixed workload.

As shown in Figure 2, TPSTA achieves a 0.00% Deadline Miss Ratio (DMR), matching the reliability of optimal uniprocessor policies like EDF and RM. This proves that by encoding hardware constraints into the vector masking mechanism, TPSTA effectively prevents “illegal” scheduling decisions that plague standard heuristics.

While K8s (Least Requested) incur minimal overhead ($\approx 6\text{–}42\mathrm{ms}$), it suffers from high failure rates (∼$46\text{–}50\%$ DMR), while Linux GTS offers a larger overhead. These algorithms are heterogeneity-oblivious: they perceive all cores as generic compute slots. Consequently, they greedily assign accelerator-bound tasks to general-purpose CPUs, leading to execution timeouts despite low scheduling latency.

A critical insight from Table 1 is the inefficiency of iterative optimization methods in real-time contexts. IM-GA provides a high-quality global search but requires 700+ ms to converge. In a system where task deadlines are tight (e.g., 500 ms), spending ~400 ms solely on scheduling decisions is untenable, leaving insufficient time for actual execution.

While Deep Reinforcement Learning (DRL) is a popular trend, it shares the “heavyweight” inference overhead of GA and introduces non-determinism. More critically, DRL models operate as “black boxes.” In safety-critical bio-medical systems (e.g., smart wheelchairs), the unexplainable nature of neural networks is a liability. TPSTA, in contrast, offers white-box explainability: every decision is a deterministic result of linear algebraic costs, traceable to specific hardware parameters ($\alpha , \beta , \gamma$).

To probe the scheduler’s resilience, we intentionally starved the system by restricting the cluster to two NUMA nodes, halving the available “membrane space” while maintaining the same workload intensity, shown in Table 2:

Table 2. Performance comparison on 2 NUMA clusters (30 independent runs, N = 800).

Algorithm	Makespan (ms) [Mean ± Std]	DMR (%) [Mean ± Std]	Overhead (ms) [Mean ± Std]	Characteristics
TPSTA	953.83 ± 119.11	29.73% ± 8.26%	28.97 ± 1.56	Vectorized Bin-Packing
EDF	953.83 ± 119.11	29.73% ± 8.26%	19.62 ± 0.83	Scalar Hetero-Aware EDF
RM	971.47 ± 129.99	29.23% ± 8.42%	19.59 ± 0.69	Static Priority Bin-Packing
Linux GTS	1042.29 ± 128.53	71.35% ± 2.51%	19.40 ± 1.83	Greedy, Red-Black Tree
K8s	2313.83 ± 829.88	70.68% ± 3.72%	2.10 ± 0.38	Bin-packing (LeastReq)
IM-GA	22,720.62 ± 2275.20	94.44% ± 1.19%	424.71 ± 14.81	Iterative Evolution

TPSTA’s DMR increased to 29.73%, but this figure is not arbitrary. Crucially, it matches the exact failure rate of the Earliest Deadline First (EDF) policy (29.73%). Since EDF is mathematically proven to be optimal for uniprocessor scheduling, this convergence indicates that TPSTA successfully extracted the theoretical maximum throughput allowed by the physical hardware. The miss rate is a consequence of hardware saturation, not algorithmic inefficiency. In contrast, standard heuristics suffered a performance drop. Linux GTS spiked to a 71.35% failure rate, and K8s to 70.68%. This gap (30% vs. 70%) exposes the fragility of “blind” schedulers. Under pressure, GTS wastes cycles on futile context switching and attempting to schedule tasks that are physically impossible to complete, whereas TPSTA’s vectorized masking mechanism effectively acts as an Admission Control filter, rejecting doomed tasks early to preserve resources for viable ones.

To ensure a fair and rigorous baseline comparison, the EDF and RM baselines in our simulation are implemented as heterogeneity-aware variants. Specifically, they are granted access to the exact same hardware cost oracle and spatial penalty vectors ($\alpha ,\beta ,\gamma$) as TPSTA. As shown in our evaluations, because these baselines share the identical spatial routing oracle, TPSTA mathematically matches the exact Deadline Miss Ratio (DMR) of the heterogeneity-aware EDF.

From a theoretical perspective, finding an optimal schedule for heterogeneous multi-core systems (HMCSs) is an NP-hard bin-packing problem. While standard EDF is mathematically optimal for uniprocessor temporal sequencing, it is inherently spatially blind on multiprocessors. To mitigate this, TPSTA fundamentally adopts a Partitioned Scheduling paradigm. It leverages the EDF gradient as a temporal mechanism to sort incoming tasks, while the vectorized Tissue P System acts as an ultra-fast, hardware-aware spatial bin-packing heuristic.

The DMR observed demonstrates that TPSTA preserves the near-optimal routing quality of the heterogeneity-aware EDF. However, the true contribution of TPSTA lies in architectural acceleration. While the scalar EDF baseline requires an $\mathrm{O}\left(\mathrm{M}\right)$ linear scan to pack each task—fundamentally violating microsecond-level latency constraints at scale—TPSTA maps this complex bin-packing logic into a vectorized physical space.

It is also noteworthy that the foundational philosophy of TPSTA’s temporal injection gradient aligns flawlessly with the recent architectural evolution of the Linux kernel, which is transitioning from CFS to EEVDF (Earliest Eligible Virtual Deadline First) [43,44]. This monumental shift acknowledges that deadline-driven temporal sequencing is fundamentally superior for mitigating tail latencies.

While EEVDF achieves excellent temporal fairness on homogeneous cores, it remains spatially blind to severe heterogeneous penalties (e.g., CPU-GPU mismatches). To bridge this gap, TPSTA functions as a policy-agnostic spatial routing engine. It decouples the state-of-the-art temporal sequencing (handled at the skin membrane) from the hardware-aware spatial bin-packing (handled by the vectorized penalty matrices $\mathsf{\alpha },\mathsf{\beta },\mathsf{\gamma }$).

It is a well-established theorem that EDF loses strict optimality on multiprocessors. Therefore, the exact statistical equivalence observed between TPSTA and the baseline heterogeneity-aware EDF (e.g., identically matching at the 29.73% DMR bound under severe starvation in Table 2) is not intended to claim mathematical optimality. Rather, it empirically validates the Spatial Fidelity (No Spatial Fragmentation) of the TPSTA architecture.

Matching the exact DMR of the scalar oracle proves that TPSTA’s $\mathrm{O}\left(\mathrm{M}/\mathrm{W}\right)$ matrix transformations execute the temporal sequence, introducing least hardware mismatch anomalies or spatial loss. Ultimately, TPSTA provides the architectural acceleration required to execute this high-fidelity spatial routing, making it a complementary spatial engine for modern deadline-centric OS frameworks like EEVDF.

5.3. Scalability and Expansibility

To isolate the algorithmic complexity from hardware heterogeneity, we configured a Pure Homogeneous Cluster consisting exclusively of performance cores (Big Cores). We disabled Hyper-Threading (HT) and accelerators to create a controlled environment. We scaled the cluster size $\mathrm{M}$ from 1 core to 4096 cores while processing a fixed batch of $N=2000$ tasks to measure the pure decision latency.

As shown in Table 3 and Figure 3, vectorized scheduling exhibits a much more gradual increasing trend. For small clusters, TPSTA incurs a constant initialization overhead (~50 ms) related to SIMD context setup, making it slower than the simple pointer arithmetic of GTS. As the cluster scales beyond 64 cores, the $O\left(M\right)$ linear scan of GTS causes latency to grow rapidly. At 4096 cores, GTS becomes unusable for real-time systems (>8 s latency). In contrast, TPSTA effectively “compresses” the search space using matrix operations, maintaining subsecond latency and achieving a 14.4× speedup. This validates the $\mathrm{O}\left(\mathrm{M}/\mathrm{W}\right)$ complexity model.

Table 3. Decision latency vs. cluster size ($\mathrm{N}=2000$, fixed batch).

Configuration	Total Cores	GTS (ms)	TPSTA (ms)	Speedup
1 Chip, 1 Core	1	5.66	55.59	0.10×
1 Chip, 4 Cores	4	11.38	53.67	0.21×
1 Chip, 16 Cores	16	33.97	56.25	0.60×
1 Chip, 64 Cores	64	131.19	63.00	2.08×
4 Chips, 256 Cores	256	523.20	86.78	6.03×
4 Chips, 1024 Cores	1024	2015.61	205.05	9.83×
16 Chips, 4 K Cores	4096	8276.60	573.63	14.43×

Figure 3. Decision latency increase on expansion of cluster size.

5.4. NUMA Affinity and Dynamic Adaptation

We simulated a two-chip NUMA cluster (16 Big Cores, no HT) to evaluate the scheduler’s trade-off analysis between data locality and compute capacity. The workload consists of 1200 tasks with affinity for Chip 0, split into CPU-Bound (compute-intensive) and IO-Bound (data-intensive) types. The experiment proceeds in three phases:

Normal: Baseline operation.

DVFS Event: Chip 0 is thermally throttled to 10% capacity.

Failure: Chip 0 is completely powered down.

Table 4 tracks the distribution of tasks across the local (Chip 0) and remote (Chip 1) nodes.

Table 4. Task distribution dynamics under fault injection.

Phase	Event	Chip 0 (Local)	Chip 1 (Remote)	Behavior Analysis
1	Baseline	CPU: 96/IO: 167	CPU: 104/IO: 33	Locality Awareness: IO tasks stick to local; CPU tasks spill over for load balancing.
2	DVFS (Chip 0)	CPU: 5/IO: 199	CPU: 195/IO: 1	Cost-Driven Trade-off: CPU tasks flee the throttled core; IO tasks stay (comm cost > compute cost).
3	Chip 0 Dead	CPU: 0/IO: 0	CPU: 200/IO: 200	Failover: Hard constraints force full migration.

As shown in Figure 4, in Phase 1, the scheduler correctly identifies that IO-Bound tasks are sensitive to the NUMA penalty ($\mathsf{\gamma }=2.0$) and keeps them local. CPU-Bound tasks, being insensitive to data movement, are distributed to Chip 1 to maximize parallelism. Phase 2 demonstrates adaptive routing. When Chip 0 slows down, CPU tasks migrate to Chip 1 because the remote execution is faster than the throttled local execution. However, IO tasks remain on Chip 0. The scheduler calculates that the penalty of moving large data volumes across the interconnect exceeds the gain from faster compute, effectively choosing to “wait” locally rather than “move” remotely. Phase 3 indicates a completely down situation, where tasks are all scheduled or migrated for Chip 1 for “asylum”.

Figure 4. NUMA and fault detection results.

5.5. SIMD Scalability Simulation

To empirically validate the Roofline Model limits, we fixed the cluster size at 4096 Big Cores (homogeneous, no HT) and varied the Simulated SIMD Width ($\mathrm{W}$) from 1 (scalar) to 4096 (full parallelism). This isolates the memory bandwidth constraints from algorithmic logic, shown in Table 5.

Table 5. Speedup vs. SIMD Width ($\mathrm{M}=4096$ Cores).

SIMD Width	Time (ms)	Speedup
1	27,744.06	1.00×
4	5468.86	5.07×
16	1448.85	19.15×
64	402.90	68.86×
256	151.71	182.88×
1024	92.93	298.55×
4096	74.00	374.94×

The results shown in Figure 5 confirm that TPSTA is primarily compute-bound at standard widths ($\mathrm{W}\le 64$), achieving near-linear speedup. However, as $\mathrm{W}$ approaches 4096, the speedup saturates at ~375× (instead of the theoretical 4096×). This saturation represents the Memory Wall: the bottleneck shifts from arithmetic throughput to the bandwidth required to load the state vectors ($\mathrm{L},\mathrm{C}$) from memory. Nevertheless, the magnitude of acceleration confirms that TPSTA has the potential of maximal parallelism, which is a full implementation of a standard P System, instead of bounded parallelism which is constrained by current von Neumann-based hardware designs.

Figure 5. Parallelism Analysis on Simulated SIMD Width.

5.6. Ablation Study and Parameter Sensitivity

To rigorously isolate the performance contributions of the TPSTA architecture and validate the robustness of the derived penalty vectors ($\mathsf{\alpha },\mathsf{\beta },\mathsf{\gamma }$), we conducted a comprehensive ablation study and sensitivity analysis. The experiment was configured under a highly constrained heavy-load environment (2 NUMA nodes, 800 mixed tasks) across 10 independent Monte Carlo runs.

Ablation Study: We selectively disabled specific spatial penalty matrices within the Tissue P System rules to evaluate their individual necessity. The results are presented in Table 6.

Table 6. Ablation and sensitivity analysis on penalty matrices (2 NUMA nodes, 10 runs).

Configuration/Variant	DMR (%) [Mean ± Std]	Makespan (ms) [Mean ± Std]	Theoretical Implication
Full TPSTA (All Active)	32.21% ± 8.53%	1017.70 ± 131.28	Optimal Vectorized P-EDF
$\mathrm{No} \mathrm{HT} (\alpha$ OFF)	22.31% ± 5.96%	1018.91 ± 134.99	Mild variance in SMT packing
$\mathrm{No} \mathrm{Hetero} (\beta$ OFF)	96.80% ± 0.96%	8842.62 ± 1532.90	Severe Failure
$\mathrm{No} \mathrm{NUMA} (\gamma$ OFF)	33.77% ± 8.29%	980.92 ± 105.97	Loss of data locality bounds
Basic SIMD (All OFF)	97.49% ± 0.50%	10,303.59 ± 1602.04	Blind vectorized routing
$\beta$ Scale 0.5× (10)	43.11% ± 8.26%	1097.65 ± 192.24	Robust degradation
$\beta$ Scale 1.5× (30)	26.34% ± 7.40%	1026.77 ± 136.35	Robust thresholding
$\gamma$ Scale 0.5×	34.17% ± 8.08%	1012.82 ± 119.70	Stable locality routing
$\gamma$ Scale 1.5×	32.23% ± 9.26%	1006.74 ± 123.64	Stable locality routing

Demonstrated in the ablation group, the heterogeneity penalty matrix ($\mathit{\beta }$) is the absolute cornerstone of the system. When $\beta$ is disabled, the system regresses to “Basic SIMD” routing—it rapidly assigns GPU-bound tasks to standard CPU cores simply because their temporal queues appear shorter. This triggers head-of-line blocking, causing the DMR to spike drastically to 96.80% and the makespan to increase by 8.6×. This unequivocally proves that SIMD vectorization alone is insufficient for HMCS; the biological “receptor matching” logic modeled by the P System is required to prevent hardware mismatch anomalies.

A common critique of heuristic architectures is their reliance on hyper-parameter tuning. However, the TPSTA parameters ($\alpha ,\beta ,\gamma$) are designed as biological “repulsive potentials” (threshold filters) rather than precise scalar weights. To prove this, we scaled the heterogeneity ($\mathsf{\beta }$) and locality ($\mathsf{\gamma }$) multipliers by $\pm 50\%$. As shown in Table 6, a 50% misconfiguration does not trigger the >$90\%$ failures seen in the ablation tests. The DMR remains structurally stable (fluctuating within expected heavy-load variances). This confirms that TPSTA is robust: If the fundamental physical hierarchy (e.g., a GPU is an order of magnitude faster for matrix tasks than a CPU) is reflected in the penalty matrices, the vectorized engine will mathematically guarantee safe spatial bin-packing.

5.7. Physical Hardware Micro-Benchmark: Validating Sub-Microsecond Latency

While high-level simulations demonstrate the routing quality of TPSTA, Python-based evaluation intrinsically abstracts away critical microarchitectural realities, such as instruction decoding overheads, branch prediction penalties, and L1/L2 cache latencies. To rigorously prove the practical OS-level feasibility of TPSTA and validate the simulated $\mathrm{O}\left(\mathrm{M}/\mathrm{W}\right)$ complexity, we developed a pure C++ physical micro-benchmark. We implemented the core spatial routing logic—specifically the evaluation of the heterogeneous penalty matrices ($\alpha ,\beta ,\gamma$) and the bin-packing assignment—using native AVX-512 intrinsics (e.g., _mm512_add_ps, _mm512_cmp_ps_mask). To test the absolute limits of the architecture, we benchmarked a massive simulated topology of 4096 heterogeneous cores. The vectorized TPSTA engine was evaluated against a standard scalar for-loop implementation, which represents the traditional $\mathrm{O}\left(\mathrm{M}\right)$ linear scan utilized by heterogeneity-aware EDF and Linux GTS variants. To ensure architectural robustness, the micro-benchmark was executed on two distinct physical processor generations:

AMD Zen 4 (Ryzen 7 7840HS): This architecture implements AVX-512 via double-pumped 256-bit ALUs.

AMD Zen 5 (Ryzen AI H 465): This architecture features a true, full-width 512-bit physical data path. The physical execution latencies (averaged over 100,000 iterations to eliminate cold-start cache anomalies) are presented in Table 7.

Table 7. Speedup vs. SIMD Width ($\mathrm{M}=4096$ Cores).

Architecture	Scalar Baseline (O(M))	Vectorized TPSTA (O(M/W))	Hardware Speedup
AMD Zen 4	14.77 μs	0.69 μs	21.52×
AMD Zen 5	13.96 μs	0.62 μs	22.36×

As shown in the hardware telemetry, the scalar baseline requires approximately $14\mathsf{\mu }\mathrm{s}$ to complete a single decision pass. In modern microsecond-scale cloud environments, dedicating $14\mathsf{\mu }\mathrm{s}$ purely to scheduling computation is prohibitively expensive and fundamentally violates the strict latency budgets of real-time OS operations.

Conversely, the vectorized TPSTA engine compresses this exact same spatial bin-packing logic into sub-microsecond latency. On the latest Zen 5 architecture, the decision for 4096 cores executes in merely 0.62 $\mathsf{\mu }\mathrm{s}$. This physical telemetry confirms two critical points:

Bypassing Scalar Overheads: The spatial vectorization of Tissue P Systems effectively eliminates scalar loop-control hazards and branch mispredictions, translating mathematical matrices into silicon data paths.

Practical Feasibility: While the development of a complete eBPF production kernel module remains as our immediate future work, a $0.62\mathsf{\mu }\mathrm{s}$ algorithmic overhead is negligible compared to standard OS context-switch latencies. Recent empirical profiling of the Linux sched_ext framework [45] demonstrates that the BPF user-space transition overheads are minimal; in fact, tailored dispatch logic can reduce total task wakeup latency by up to 45% compared to the default in-kernel CFS. By mathematically guaranteeing that our spatial routing engine executes in sub-microsecond time bounds on physical hardware, we have proven that TPSTA will not become a computational bottleneck. This establishes TPSTA as a highly viable, hardware-validated candidate for future integration into modern BPF-based OS scheduling ecosystems.

6. Conclusions and Future Perspectives

In this work, we explored the natural isomorphism between graph-based Tissue P Systems and heterogeneous multi-core systems (HMCSs). By mapping cells to heterogeneous cores and intercellular communication to Network-on-Chip (NoC) interconnects, we designed TPSTA, a vectorized, bio-inspired scheduling framework. To strictly isolate and validate this architecture, we focused on the scheduling of independent, non-preemptive (Run-to-Completion) tasks, bridging the gap between theoretical membrane computing and physical hardware constraints.

To address the fundamental trade-offs of heterogeneous scheduling, TPSTA employs a rigorous spatio-temporal decoupling strategy. It leverages an EDF-based gradient for optimal temporal injection while utilizing vectorized penalty matrices ($\mathsf{\alpha },\mathsf{\beta },\mathsf{\gamma }$) as a fast, hardware-aware spatial bin-packing engine. Unlike “blind” heuristics (e.g., Linux GTS, Kubernetes) that sacrifice correctness for speed, or “heavyweight” optimizations (e.g., Genetic Algorithms) that suffer from prohibitive convergence latency (>700 ms) and black-box opacity, TPSTA offers deterministic explainability and sub-microsecond responsiveness. Our experiments demonstrated its robustness, mathematically matching the near-optimal routing reliability of a fully heterogeneity-aware oracle and achieving a 0.00% Deadline Miss Ratio under normal loads.

We successfully translated the symport/antiport rules of P systems into $\mathrm{O}\left(\mathrm{M}/\mathrm{W}\right)$ matrix operations executable on modern CPUs via native AVX-512 intrinsics. Physical micro-benchmarks confirm that this approach achieves extreme scalability on many-core clusters (up to 4096 cores), delivering a 22.3× hardware speedup over scalar baselines and compressing decision latency to merely 0.62 μs. This proves TPSTA’s potential for modern user-space ecosystems like Linux sched_ext.

Acknowledging that TPSTA realizes a form of bounded parallelism rather than the maximal parallelism defined in theoretical P Systems, this deviation is necessitated by two critical factors:

Hardware Constraints: The parallelism of current von Neumann architectures is bounded by the physical width of SIMD units ($\mathrm{W}$), whereas theoretical membranes possess infinite parallel execution capacity.

Determinism vs. Non-Determinism: While P Systems are inherently stochastic, industrial real-time scheduling requires strict determinism. TPSTA deliberately sacrifices non-deterministic evolution for predictable, urgency-driven decision-making.

Our future work will focus on expanding membrane synaptic rules to support DAG topological dependencies via inter-membrane tokens, and modeling object expulsion for preemptive execution. Consequently, the realization of a fully biologically isomorphic or even bio-implemented scheduler based on P Systems—one that fully exploits maximal parallelism and non-deterministic evolution—awaits the maturation of non-von Neumann architectures, such as membrane hardware accelerators, in-memory computing substrates, or neuromorphic chips [46].