Synthesis of FPGA-Based Moore FSMs with Two Cores of Partial Functions

Abstract

A new architecture of FPGA-based Moore finite state machine (FSM) is proposed, as well as the corresponding method of synthesis. The proposed architecture of FSM circuit includes two cores of partial Boolean functions. The first core is based on functional decomposition, the second core is based on structural decomposition. Under certain conditions, the proposed method improves both spatial and temporal characteristics of FSM circuits. The FSM states have two codes. The first of them is a maximum binary code (MBC) having minimum possible number of bits. The second code is a partial state code representing a state as the element of some class of compatibility. The method can be applied if Moore FSM circuits are implemented using look-up table (LUT) elements of field-programmable gate arrays. To improve characteristics of resulting FSM circuits, the classes of pseudoequivalent states are used. This allows diminishing the numbers of literals in sum-of-products representing partial input memory functions. The first core is multi-level. For the second core, all partial functions are generated by single-LUT circuits. These cores form the first level of FSM circuit. The LUTs of the second level generate bits of MBCs. These codes are used by the third circuit level for generating both FSM outputs and partial state codes. An example of synthesis is shown. The experiments are conducted using a known library of benchmark Moore FSMs. The experiments show that the proposed approach can be used for complex FSMs where the total number of FSM inputs and state variables is at least twice the number of inputs of the base LUT. The results of experiments show that the proposed method allows improving both the spatial and temporal characteristics for complex FSMs compared with their counterparts based on other known design methods.

1. Introduction

It is known that the majority of modern digital systems includes a lot of various sequential blocks [1,2]. These sequential blocks can be used as (1) control units of computers [3,4,5,6,7]; (2) controllers of various protocols used in embedded systems [8]; (3) blocks of hyper-tangent and exponential functions [9]; (4) different blocks for integral stochastic computing [10]; (5) activation functions of deep neural networks [11,12]; (6) different stages of cascaded digital processing systems [13,14]. A lot of other examples could be added [15,16,17,18,19,20,21,22,23]. This wide range of applications explains continuous interest in optimizing characteristics of sequential blocks. This requires working out new design methods of these blocks. Very often, the sequential blocks are represented using the model of Moore finite state machine (FSM) [24,25]. This paper is devoted to optimizing spatial characteristics of Moore FSMs implemented with field-programmable gate arrays (FPGAs) [26,27,28].

Various FPGA chips are applied for implementing the digital systems [29,30]. Due to this, we choose these chips as a base for implementing circuits of Moore FSMs. Leading experts are sure that FPGAs will be used for at least three next decades [31]. In this article, we discuss a case when logic circuits of Moore FSMs are implemented with look-up table (LUT) elements, programmable flip-flops, dedicated multiplexers, programmable interconnections, and a synchronization tree.

A LUT is a single-output logic block having $S_L$ inputs [26,28]. If some Boolean function depends on up to $S_L$ arguments, then it could be generated by a single LUT [32,33]. But the number of LUT inputs is very small: it does not exceed six [26,28,30]. Very often, this peculiarity is the cause of using the methods of functional decomposition (FD). These methods turn systems of Boolean functions (SBFs) representing logic circuits of Moore FSMs [33,34] into compositions of partial functions. This approach produces rather Moore FSM circuits having a lot of logic levels and a very complicating system of interconnections [35].

To improve the main characteristics of LUT-based FSM circuits, it is necessary to reduce the numbers of LUTs used and simplify the system of interconnections. The problem of reducing the values of LUT counts is known as a problem of improving the spatial characteristics [36,37]. As a rule, optimizing the values of LUT counts reduces the chip area occupied by an FSM circuit. In turn, it reduces the value of power consumption [38]. It is very important to improve the spatial characteristics in such a way that this does not deteriorate tremendously the temporal characteristics of resulting circuits. In this article, we propose a method which allows optimizing spatial characteristics without increasing either the cycle time or the power consumption of produced Moore FSM circuit.

The spatial characteristics of a LUT-based FSM circuit is determined mostly by the value of LUT count and the system of inter-LUT interconnections. The best way for reducing the area required by a circuit is the reducing the value of LUT count for a given circuit. But optimizing the system of interconnections is very important, too. Two factors determine this importance. The first factor: in modern chips, interconnection delay dominates logic delay [32,39]. The second factor: around 70% of power is consumed by the system of interconnections [40]. So, the optimization of the interconnect system is necessary to diminish the power consumption and increase the value of maximum operating frequency of a particular FSM circuit [2].

Results of research [29] prove that value S_L = 6 allows obtaining the optimal trade-off for such characteristics of LUTs as the occupied chip area, performance, and consumed energy. Therefore, we cannot expect the growth for the number of LUT inputs. But the complexity of FPGA-based projects is constantly growing [19,41]. So, it is necessary to develop efficient methods of technology mapping for improving the basic characteristics of LUT-based circuits.

In this paper, we propose a novel design method whose purpose is improving the spatial characteristics of LUT-based Moore FSMs. The method uses some specifics of the model of Moore FSM discussed further. The main idea of the proposed method is reduced to adding an SD-based core of partial Boolean functions (PBFs) to FD-based Moore FSM architecture. The proposed method leads to double-core FSM architectures whose circuits have less values of LUT counts than their single-core FD-based counterparts.

The paper includes five more sections. They contain the following information. Section 2 includes basic information about the FSM model used and logic elements. Section 3 discusses the state of the art in the LUT-based design of sequential devices. Section 4 represents the essence of the proposed method. Section 5 includes a synthesis example. Section 6 is devoted to analysis of results of conducted experiments. A brief conclusion sums up the results obtained in the paper.

2. Background Information

As a rule, modern FPGAs include different configurable logic blocks (CLBs) and a matrix of programmable interconnections [26,27,28]. Our current paper is devoted to the case when CLBs include LUTs, dedicated multiplexers and programmable flip-flops. Inside each CLB, the LUT output and a flip-flop input are directly connected (without using programmable multiplexers). The flip-flops can be used as a state memory of sequential blocks [24].

The main specific of LUT is a very limited number of inputs, $S_L$. In modern FPGAs, the value of $S_L$ does not exceed six [28,42]. This leads to the necessity of functional decomposition of Boolean functions depending on at least 1+$S_L$ arguments [33]. As a rule, the FD-based FSM circuits are multi-level. Moreover, they posses the irregular systems of interconnections. As it is mentioned in [2], the functional decomposition leads to FSM circuits with “spaghetti-type” interconnections.

A Moore FSM is defined as a six-component vector $S = <A, X, Y, \delta , \lambda , a_1>$ [24], where $A=\{a_1, \dots , a_M\}$ is a finite set of states, $X=\{x_1, \dots , x_L\}$ is a finite set of inputs, $Y=\{y_1, \dots , y_N\}$ is a finite set of outputs, $\delta$ is a transition function, $\lambda$ is an output function, and $a_1\in A$ is an initial state. A Moore FSM can be represented using various approaches. In this paper, we use state transition graphs (STGs) and state transition tables (STTs) of Moore FSMs [1,24].

An STG has M nodes. Each node corresponds to a single state $a_m\in A$. Near each node, the collections of outputs $Y_q\subseteq Y$ are written where $q\in \{1, \dots , Q\}$. The interstate transitions are represented by arcs directed from current states into states of transitions. If an FSM has H transitions, then its STG has H arcs. Above the $h-th$ arc, the input signal $X_h$ is written. This signal determines the transition from a current state into the next state. The signal $X_h$ is a conjunction of inputs (or their compliments) determining a particular transition.

An STT can be viewed as a tabular representation of a corresponding STG. Each line of STT corresponds to a unique arc of STG. The STT has the columns [24]: $a_m$ (the current state), $a_s$ (the state of transition), $X_h$, h. The collection of outputs generated in the state $a_m\in A$ is shown in the column $a_m$. This allows to implement the output function of Moore FSMs where outputs do not depend on FSM inputs. There is the transparent connection between these two forms of FSM representation.

Three operations should be executed to construct SBFs representing a Moore FSM circuit [24]. First of all, it is necessary to execute a state assignment [43,44,45]. During this step, each state $a_m\in A$ is represented by a binary code $K\left(a_m\right)$. In the case of maximum binary state assignment, this code consists of R bits (state variables). The minimum possible number of state code bits, R, is determined as

$$R=\lceil lo{g}_{2}M\rceil .$$

(1)

Let us point out that maximum binary codes (MBCs) are used, for example, in well-known academic systems SIS [46] and ABC [47] of Berkeley, as well as in industrial CAD tools Vivado [48] and Quartus [49].

The second step is a constructing the sets of state variables $T=\{T_1, \dots , T_R\}$ and input memory functions (IMFs) $D=\{D_1, \dots , D_R\}$. The IMFs are used for generating the code of the state of transition; they allow to implement the transition function of Moore FSM. The third step is reduced to transformation of initial STT into a direct structure table (DST). Compared to STT, an equivalent DST has three additional columns: $K\left(a_m\right)$, $K\left(a_s\right)$, $D_h$. The column $D_h$ includes IMFs corresponding to state variables $T_r=1$ in a code $K\left(a_s\right)$ written in the $h-th$ line of DST.

State codes should be unchangeable during a cycle of operation. To provide this property, a special register (RG) is used. This block includes R flip-flops. Its operation is controlled by inputs of synchronization (Clock) and reset (Start). As a rule, D flip-flops are used in LUT-based FSMs [43]. Input memory functions $D_r\in D$ can change the RG content (of course, the content may stay the same if the relation $K\left(a_m\right)=K\left(a_s\right)$ takes place for a given transition).

A direct structure table is a base for creating two systems of functions. These systems are the following:

$$D=D(T,X);$$

(2)

$$Y=Y\left(T\right).$$

(3)

The SBFs (2) and (3) are the base for designing a logic circuit of Moore FSM $U_1$ (Figure 1) [50]. In the paper, we use the symbol $LUTer$ to show that a particular block’s circuit includes only LUT-based CLBs. If some block $LUTer$ generates IMFs, then outputs of corresponding flip-flops are treated as registered outputs of this block.

Figure 1. Structural diagram of LUT-based Moore FSM $U_1$.

In Moore finite state machine $U_1$, the block $LUTerT$ generates IMFs represented by (2), the block $LUTerY$ generates outputs represented by SBF (3). If a function $D_r$ is generated by some LUT, then the corresponding flip-flop’s output is used to enter other CLBs of an FSM circuit. The flip-flops represent the block RG which is hidden inside the block $LUTerT$. Because of it, the pulses Start and Clock enter the $LUTerT$. Obviously, the state register RG is hidden. Due to this, the RG is not shown as a separate block of FSM $U_1$.

As shown in [51], using two specifics leads to optimizing the spatial characteristics of Moore FSM circuits. The first specific is an existence of classes of pseudoequivalent states (PES). The second specific is a dependence of FSM outputs $y_n\in Y$ only on state variables $T_r\in T$. Using the first specific, it is possible to minimize the number of arguments in sum-of-products (SOP) of functions included into SBF (2). Using the second specific allows reducing the number of arguments in SOPs of functions $y_n\in Y$. We propose to use these specifics in LUT-based design. This may result in reducing the numbers of LUTs and their levels in circuits of blocks $LUTerT$ (using the first specific) and $LUTerY$ (using the second specific). We discuss these issues in the following sections.

3. State of the Art

The process of technology mapping has been always associated with solution of some optimization problems [43]. As a rule, three classical optimization problems arise in the process of designing FPGA-based FSMs [2]. These problems are: (1) the improving the spatial characteristics, (2) the increase in performance, and (3) the reduction in power consumption. The current paper is aimed at the improving the spatial characteristics. In LUT-based circuits, the spatial characteristics are mostly determined by the numbers of LUT (LUT count) used and inter-CLB interconnections [2].

Of course, some other problems are connected with designing FSM circuits. For example, the testability of FPGA-based circuit should be improved [52,53,54,55]. Also, the circuits should require defense against various malicious attacks [56,57]. In many practical cases, it is necessary to increase the reliability of FSM circuits [58]. To provide the required qualities for an FSM circuit, some additional internal chip resources must be used [58]. This additional blocks consume LUTs, interconnections, and power. We do not discuss these problems because each of them requires a separate paper devoted exclusively to a particular problem.

Let us denote as $NL\left(f_i\right)$ the number of literals [1] in SOP of a function $f_i\in D\cup Y$. As shown in [2], the number of logic levels in the resulting circuit implementing the function $f_i\in D\cup Y$ depends significantly on the condition

$$NL\left(f_i\right)\le S_L.$$

(4)

The violation of Condition (4) leads to producing multi-level FSM circuits. In this case, the problem of hardware reduction arises. For multi-level circuits, it is quite possible that the same inputs $x_l\in X$ and state variables $T_r\in T$ appear on more than a single logic level. It leads to circuits with the spaghetti-type interconnections. The results of experiments conducted by the authors of [59] proved that the regularization of interconnections leads to decreasing the power consumption compared with equivalent circuits having irregular interconnections.

To improve the spatial characteristics LUT-based FSM circuits, three main approaches can be used:

1.

The functional decomposition of SBFs (2) and (3) [3,33,60,61];

2.

The optimal encoding of internal FSM states [1,2,62];

3.

The transformation of FSM circuit (the structural decomposition) [2,59,63,64].

The essence of FD is the following. If Condition (4) is violated, then a function $f_i\in D\cup Y$ is broken down into smaller and smaller components. These components are partial Boolean functions (PBFs). This process is terminated when any PBF depends on no more than $S_L$ arguments. The FD-based solutions are used very often in the process of FPGA-based technology mapping [61,65].

Using the methods of FD leads to appearing $N1$ partial Boolean functions. These partial functions are much simpler than the initial functions included in Systems (2) and (3). If Condition (4) takes place, then there are only $R+N$ LUTs in the logic circuit of Moore FSM $U_1$. Otherwise, the circuit includes $R+N+N1$ elements. The program tools for executing FD are integral parts of both academic [46,47] and industrial [66,67,68] CAD systems.

It is known that for the same FSM, different outcomes of state assignment result in the FSM circuit with different amount of hardware [69]. The optimal state assignment is a process allowing maximum possible minimization of SBFs (2) and (3). This task could be solved using, for example, the algorithm JEDI [46]. We think that JEDI is a part of the system ABC developed by Berkely [47].

Let us point out that each literal of SOP corresponds to a wire in the FSM circuit. So, to reduce the number of interconnections, it is necessary to reduce the numbers of literals in functions $f_i\in D\cup Y$. Therefore, the optimal state assignment must be performed regardless of holding Condition (4).

Various state assignment strategies can be found in modern industrial CAD tools. For example, the design tool Vivado [48,67] of AMD Xilinx uses: the automatic state assignment; One-hot (R = M); compact; Gray codes; Johnson codes; speed encoding; sequential encoding.

In the case of Moore FSM, the area reduction can be achieved via taking into account the existence of pseudoequivalent states [50]. The states $a_m, a_s\in A$ are pseudoequivalent if $\delta$($a_m,X_h$) = $\delta$($a_s,X_h$). Using this definition, it is possible to find a partition ${\Pi }_A=\{B_1, \dots , B_I\}$ of the set A by classes of PES. If $I<M$, then the optimal state assignment is reduced to finding state codes such that each class $B_i\in {\Pi }_A$ is represented by a minimum possible number of generalized intervals of R-dimensional Boolean space [50]. Such state assignment can be executed using, for example, the methods in [70].

The main idea of SD-based methods [50] is reduced to elimination of a direct dependency of functions $f_i\in D\cup Y$ on inputs $x_l\in X.$ To eliminate direct dependence, a set $\Psi$ of some additional functions is constructed. These functions are divided by systems. Each system of new functions determines a separate block $LUTer$ with its unique sets of input and output variables. The classical SD methods use additional variables instead of FSM inputs and maximum binary codes instead of FSM outputs [24]. These methods are thoroughly discussed, for example, in [2].

As shown in [2], the structural decomposition leads to reduced number of literals in SOPs of functions $f_i\in D\cup Y$ as compared to Functions (2) and (3). In turn, this leads to reducing the values of LUT counts in circuits of FSMs $U_1$ as compared to their counterparts based on functional decomposition.

Let the transitions from the state $a_m\in A$ depend on $L\left(a_m\right)$ FSM inputs. Let for some Moore FSM Condition (4) be violated, whereas the following condition holds:

$$L\left(a_m\right)+R\le S_L.$$

(5)

In this case, reducing hardware in LUT-based Moore FSMs is possible due to using the method of twofold state assignment [50].

The term “twofold state assignment” means that each state $a_m\in A$ has two codes: the maximum binary code $K\left(a_m\right)$ and a partial state code $PC\left(a_m\right)$. To create partial state codes, the additional variables ${\tau }_r\in \tau$ are used. This method can be applied if for each state $a_m\in A$ the following condition takes place:

$$L\left(a_m\right)<S_L.$$

(6)

Let us explain this approach. The method is based on finding a partition ${\Pi }_{AT}=\{A^1, \dots A^K\}$ of the set A by classes of compatible states. A class $A^k\in {\Pi }_{AT}$ includes $M_k$ states. Each state is encoded by two codes (MBC $K\left(a_m\right)$ and $PC\left(a_m\right)$). The code $PC\left(a_m\right)$ requires $R_k$ state variables, where

$$R_k=\lceil {\log }_2(M_k+1)\rceil .$$

(7)

To create partial codes of states $a_m\in A^k$, the variables ${\tau }_r\in {\tau }^k=\{{\tau }_1, \dots , {\tau }_{Rk}\}$ are used.

The variables ${\tau }_r\in {\tau }^k$ are combined into a single set $\tau$ having $R_{TF}$ elements:

$$R_{TF}=R_1+R_2+\dots +R_K.$$

(8)

The elements ${\tau }_r\in \tau$ create extended state codes (ESC) $EC\left(a_m\right)$.

Each class $A^k\in {\Pi }_{AT}$ corresponds to some block $LUTerk$. This block generates the following partial functions:

$$D^k=D^k({\tau }^k,X^k).$$

(9)

In (9), the symbol $D^k$ stands for a set of IMFs generating during the transitions from the states $a_m\in A^k$, the symbol $X^k$ stands for a set of FSM inputs causing transitions from the states $a_m\in A^k$. These K blocks create the first level of FSM circuit.

A block $LUTerT$ (the functional assembler) generates the final values of IMFs:

$$D=D(D^1, \dots , D^K).$$

(10)

This block creates the second logic level.

The third logic level includes two blocks, $LUTerY$ and $LUTer\tau$. The block $LUTerY$ generates functions from SBF (3). The block $LUTer\tau$ generates the extended state codes. Due to this, the block $LUTer\tau$ implements SBF:

$$\tau =\tau \left(T\right).$$

(11)

The architecture of Moore FSM $U_2$ is shown in Figure 2.

Figure 2. Structural diagram of LUT-based Moore FSM $U_2$.

The block $LUTerT$ includes R primary–secondary flip-flops combined into state register. The register is hidden inside CLBs of $LUTerT$. Pulses Start and Clock control the operation of RG.

The states of each class are compatible. This means [50] that the states $a_m\in A^k$ satisfy the condition

$$R_k+L_k\le S_L.$$

(12)

The symbol $L_k$ in (12) stands for the number of elements in the set $X^k$.

As shown in [2], this approach improves spatial characteristics of LUT-based FSM circuits compared with the characteristics of FD-based equivalents. But the model $U_2$ cannot be applied if the following condition takes place for at least a single state $a_m\in A$:

$$L\left(a_m\right)\ge S_L.$$

(13)

Obviously, if (13) holds, then it is impossible to place such a state into any class $A^k\in {\Pi }_{AT}$. In this case, the model $U_1$ should be used. This means that methods of FD should be applied to implement the logic circuit of this particular Moore FSM.

In the current paper, we propose a design method which allows using twofold state assignment only for some part of FSM circuit. In this case, the FSM architecture includes two cores of PBFs. One core is based of FD. Another core is based on twofold state assignment.

4. Background of Proposed Method

Let some Moore FSM S be represented by its STG. Let us encode FSM states by MBCs having minimum number of bits determined as (1). Let us construct the DST of Moore FSM S. Now, we know the numbers of FSM states, inputs, and code bits, R. Knowing this, we can divide the set of states A by two disjoint sets, $A_{FD}$ and $A_{SD}$ ($A_{FD}\cup A_{SD}=A;$ $|A_{SD}\cap A_{FD}|=0$). For the states $a_m\in A_{FD}$, Condition (13) holds. Obviously, for the states $a_m\in A_{SD}$, Condition (13) is violated. The set $A_{FD}$ determines a set $X^0$ including FSM inputs which cause transitions from states $a_m\in A_{FD}$. There are $M_{FD}$ elements in the set $A_{FD}$. The set $A_{SD}$ determines a set $X^{SD}$ including FSM inputs which cause transitions from states $a_m\in A_{SD}$. The set $A_{SD}$ contains $M_{SD}$ states.

Let us encode states $a_m\in A_{FD}$ by partial codes $PC\left(a_m\right)$ having $R_{FD}$ variables, where

$$R_{FD}=\lceil lo{g}_2{M}_{FD}\rceil .$$

(14)

To create these codes, we use variables from a set $V=\{v_1,,,v_{RFD}\}$. Using DST, we can find the set of partial input memory functions $D^0\subseteq D$. This set includes IMFs generating during transitions from states $a_m\in A_{FD}$. Using the part of DST with current states $a_m\in A_{FD}$, the following SBF can be created:

$$D^0=D^0(V,X^0).$$

(15)

Next, we propose to apply the procedure of twofold state assignment for the states $a_m\in A_{SD}$. Let us find the partition ${\Pi }_{ASD}=\{A^1, \dots , A^K\}$ of the set $A_{SD}$ by K classes of compatible states. This can be achieved using the greedy algorithm discussed in [50]. The states $a_m\in A^k$ are encoded by partial codes $PC\left(a_m\right)$ using elements of the set ${\tau }^k\in \tau ={\tau }^1\cup {\tau }^2\cup \dots \cup {\tau }^K$.

After executing the partial state assignment, we create the DST for states $a_m\in A_{SD}$. This allows finding SBFs (9). The final values of input memory functions could be generated using the following SBF:

$$D=D(D^0, D^1, \dots , D^K).$$

(16)

Finally, we should find an SBF representing dependences of variables $v_r\in V$ and ${\tau }_r\in \tau$ on the state variables $T_r\in T$. The SBF (11) gives this dependence for variables ${\tau }_r\in \tau$. The second dependence is represented as

$$V=V\left(T\right).$$

(17)

Systems (9), (11), (15)–(17) determine an architecture of Moore FSM $U_3$ with two cores of partial Boolean functions. The generalized architecture of FSM $U_3$ is shown in Figure 3.

Figure 3. Generalized architecture of FSM $U_3$.

The generalized architecture (Figure 3) consists of three levels of logic blocks. The first level includes two cores of PBFs. The $CoreFD$ includes LUTs generating functions from SBF (15). This core’s circuit is multi-level. The implementation of the LUT-based circuit of the $CoreFD$ is connected with applications of various methods of FD [61]. This core is responsible for reducing the value of maximum operating frequency of resulting FSM circuit.

The $CoreSD$ includes LUTs generating functions from SBF (9). The core’s circuit is single-level. The implementation of corresponding LUT-based circuit is straightforward.

The second logic level is a functional assembler. The final values of IMFs (16) are generated by LUTs of this block. The function $D_r\in D$ is represented by $NF\left(D_r\right)$ partial functions. It is possible that the block includes only a single level of LUTs. This is possible if the following condition takes place for all input memory functions:

$$NF\left(D_r\right)\le S_L.$$

(18)

If (18) is violated, then this circuit includes at least two levels of LUTs. The block includes a distributed register RG controlled by signals Start and Clock.

The code transformer represents the third logic level of FSM $U_3$. Its LUTs generate partial state Variables (11) and (17) together with FSM outputs (3). This block is single-level if the following condition holds:

$$R\le S_L.$$

(19)

Each block (Figure 3) is represented by some blocks of LUTs. The resulting architecture of FSM $U_3$ is shown in Figure 4.

Figure 4. LUT-based architecture of Moore FSM $U_3$.

There is a transparent connection between architectures shown in Figure 3 and Figure 4. The block $CoreFD$ is represented by the block $LUTerFD$ (Figure 4). The block CoreSD is represented by K blocks $LUTerk$. The functional assembler is represented by the block $LUTerT.$ Finally, two blocks of LUTs represent the code transformer (Figure 3). The block $LUTerY$ generates FSM outputs. The block $LUTer\tau V$ generates variables used for creating partial state codes.

In this paper, we propose a synthesis method for Moore FSM $U_3$. We assume that an FSM is represented by either STT or STG. In the latter case, the initial STG should be transformed into the equivalent STT. There are the following steps in the proposed synthesis method:

1.

Dividing the set of states by sets $A_{FD}$ and $A_{SD}$.

2.

Encoding of states $a_m\in A_{FD}$ by partial state codes $PC\left(a_m\right)$.

3.

Splitting the set $A_{SD}$ by K classes of compatible states.

4.

Encoding of states $a_m\in A^k$ by partial state codes $PC\left(a_m\right)$.

5.

Encoding of states $a_m\in A$ in the way minimizing SBF (3).

6.

Deriving Functions (15) from the table of block $LUTerFD$.

7.

Deriving Functions (9) from tables of blocks $LUTerk$.

8.

Deriving Functions (16) from the table of functional assembler.

9.

Deriving Functions (17) from the table of block $LUTer\tau V$.

10.

Executing the technology mapping for resulting Moore FSM circuit.

5. Example of Synthesis

In this section, the procedure for synthesizing a Moore FSM circuit according to the proposed method is illustrated. The implementation assumes LUT elements with five inputs. As a demonstration example, we consider the FSM $S_1$, which is described by the state transition table (STT) presented in Table 1 and by the corresponding state transition graph (STG) shown in Figure 5.

Table 1. State transition table of Moore FSM S1.

${\mathit{a}}_{\mathit{m}}$	${\mathit{a}}_{\mathit{s}}$	${\mathit{X}}_{\mathit{h}}$	h
$a_1$ (—)	$a_2$	$x_1{x}_2{x}_3$	1
	$a_4$	$x_1{x}_2\overline{x_3}$	2
	$a_5$	$x_1\overline{x_2}$	3
	$a_3$	$\overline{x_1}{x}_4$	4
	$a_6$	$\overline{x_1}\overline{x_4}{x}_5$	5
	$a_7$	$\overline{x_1}\overline{x_4}\overline{x_5}$	6
$a_2$ ($y_1$)	$a_8$	$x_6{x}_7$	7
	$a_9$	$x_6\overline{x_7}$	8
	$a_4$	$\overline{x_6}$	9
$a_3$ ($y_5{y}_8$)	$a_{10}$	$x_4{x}_5$	10
	$a_{11}$	$x_4\overline{x_5}$	11
	$a_5$	$\overline{x_4}$	12
$a_4$ ($y_5{y}_6$)	$a_8$	$x_6{x}_7$	13
	$a_9$	$x_6\overline{x_7}$	14
	$a_4$	$\overline{x_6}$	15
$a_5$ ($y_2{y}_3{y}_8$)	$a_8$	$x_6{x}_7$	16
	$a_9$	$x_6\overline{x_7}$	17
	$a_4$	$\overline{x_6}$	18
$a_6$ ($y_1{y}_2{y}_3$)	$a_{10}$	$x_4{x}_5$	19
	$a_{11}$	$x_4\overline{x_5}$	20
	$a_5$	$\overline{x_4}$	21
$a_7$ ($y_4{y}_9$)	$a_{10}$	$x_4{x}_5$	22
	$a_{11}$	$x_4\overline{x_5}$	23
	$a_5$	$\overline{x_4}$	24
$a_8$ ($y_3$)	$a_2$	$x_6$	25
	$a_1$	$\overline{x_6}$	26
$a_9$ ($y_6$)	$a_2$	$x_6$	27
	$a_1$	$\overline{x_6}$	28
$a_{10}$ ($y_1{y}_4$)	$a_6$	$x_5$	29
	$a_1$	$\overline{x_5}$	30
$a_{11}$ ($y_7$)	$a_6$	$x_5$	31
	$a_1$	$\overline{x_5}$	32

Figure 5. State transition graph representing the Moore FSM S1.

As follows from Table 1, Moore FSM S1 is characterized by the following sets: $A=\{a_1, \dots , a_{11}\}$, $X=\{x_1, \dots , x_7\}$, and $Y=\{y_1, \dots , y_9\}$. This gives the following: M = 11, L = 7, and N = 9. Table 1 consists of H = 32 rows corresponding to interstate transitions. Using Condition (1) gives R = 4. This determines the sets of state variables $T=\{T_1, \dots , T_4\}$ and IMFs $D=\{D_1, \dots , D_4\}$. Using Table 1 and the value of $S_L=5$, we can divide set A by two disjoint sets.

Step 1. The set $A_{FD}$ exists if an STT includes states satisfying (6). In our example, Condition (6) is transformed into the following: $L\left(a_m\right)\ge 5.$ The analysis of Table 1 allows finding the values of parameters $L\left(a_m\right)$ for states $a_m\in A.$ Only state $a_1$ satisfies Condition (6). This gives the following sets: $A_{FD}=\left\{a_1\right\}$, and $A_{SD}=\{a_2, \dots , a_{11}\}$.

Step 2. The outcome of Step 1 shows that $M_{FD}=1.$ Using (14) gives the number of partial state variables $R_{FD}=1.$ In turn, this determines the set $V=\left\{v_1\right\}$. Let the partial code $PC\left(a_1\right)=1$ be assigned for the state $a_1$.

Step 3. To determine the partition ${\Pi }_{ASD}$, the greedy algorithm described in [50] is applied. This procedure iteratively constructs each class by attempting to incorporate the largest possible number of states. The main condition for including a state into a particular class $A^k$ is the following: the including should minimally increase the number of elements in the set $X^k$.

As follows from [50], the pseudoequivalent states determine the classes of a partition ${\Pi }_A=\{B_1, \dots , B_I\}$ of the set of states. The same inputs cause the same transitions from all states $a_m\in B_i.$ Due to this, in the case of Moore FSMs, all pseudoequivalent states $a_m\in B_i$ are automatically placed into the same class $A^k\in {\Pi }_{ASD}$ (if it is possible, of course).

In the discussed example, there are the following classes of PES: $B_1=\left\{a_1\right\}$, $B_2=\{a_2, a_4, a_5\}$, $B_3=\{a_3, a_6, a_7\}$, $B_4=\{a_8, a_9\}$ and $B_5=\{a_{10}, a_{11}\}$. So, there is I = 5. Using greedy algorithm [50] gives the following partition of the set $A_{SD}$: ${\Pi }_{ASD}=\{A^1, A^2\}$ with K = 2. This partition includes the classes $A^1=\{a_2, a_4, a_5, a_8, a_9\}$ and $A^2=\{a_3, a_6, a_7, a_{10}, a_{11}\}$. Analysis of these classes shows that the first class includes PES from $B_2, B_4$, the second class includes PES from $B_3, B_5$.

Step 4. In the discussed case, there is $M_1=M_2=5$. Using (7) gives the numbers of bits in partial state codes: $R_1=R_2=3.$ These values determine the sets ${\tau }^1=\{{\tau }_1, {\tau }_2, {\tau }_3\}$, ${\tau }^2=\{{\tau }_4, {\tau }_5, {\tau }_6\}$ and $\tau =\{{\tau }_1, \dots , {\tau }_6\}$. The variables from the set ${\tau }^1$ create partial state codes $PC\left(a_m\right)$, where $a_m\in A^1.$ The variables from the set ${\tau }^2$ create partial state codes $PC\left(a_m\right)$ for states $a_m\in A^2.$

To eliminate some state variables from SOPs of Functions (9), we propose to place codes $PC\left(a_m\right)$, where $a_m\in B_i$ and $a_m\in A^k$, into the same generalized interval of $R_k$-dimensional Boolean space. This can be achieved using, for example, the approach discussed in [70]. Using this approach, we can create the partial state codes shown in Karnaugh maps (Figure 6 and Figure 7). In these maps, the symbol «∉» shows that code 000 encodes the relation $a_m\notin A^k$. So, code 000 represents all states which do not belong to the particular class of compatible states.

Figure 6. Partial state codes for $LUTer1$.

Figure 7. Partial state codes for $LUTer2$.

As follows from Figure 6 and Figure 7, each class of PES is represented by a single generalized interval. For example, the states $a_m\in B^1$ are represented by the interval *1* (the symbol «*» means that the corresponding state variable is “don’t care”).

Step 5. To reduce the size of the SOP expressions of SBF (3), each FSM state should be encoded so that it can be covered by the smallest possible number of generalized intervals in the R-dimensional Boolean space [50]. This can be achieved using, for example, the method from [70]. One of the outcomes of such encoding is shown in Figure 8.

Figure 8. Outcome of state assignment for Moore FSM S1.

Using Table 1, we can find the dependence between states and FSM outputs. For example, the output $y_1$ is generated in the states from the set $\{a_2, a_6, a_{10}\}$. So, the output $y_1$ is represented as $y_1=A_2\vee A_6\vee A_{10}$. The symbols $A_m$ stand for the conjunction of state variables corresponding to codes $K\left(a_m\right)$. As follows from Figure 8, the corresponding codes belong to interval 01**. So, the formula for $y_1$ should include only literals $\overline{T_1}$ and $T_2$: $y_1={\overline{T}}_1\wedge T_2$. Acting in the same way, we can create the following SBF:

$$\begin{array}{c}{y}_1=A_2\vee A_6\vee A_{10}=\overline{T_1}{T}_2;\hfill \\ y_2=A_5\vee A_6=\overline{T_1}\overline{T_3}{T}_4;\hfill \\ y_3=A_5\vee A_6\vee A_8=\overline{T_3}{T}_4;\hfill \\ y_4=A_7\vee A_{10}=T_3{T}_4;\hfill \\ y_5=A_3\vee A_4=T_3\overline{T_4},\hfill \\ y_6=A_4\vee A_9=T_1\overline{T_2}\overline{T_4};\hfill \\ y_7=A_{11}=T_1{T}_2;\hfill \\ y_8=A_3\vee A_5=\overline{T_1}\overline{T_2}{T}_4\vee \overline{T_1}\overline{T_2}\overline{T_3};\hfill \\ y_9=A_7=T_1{T}_3{T}_4.\hfill \end{array}$$

(20)

Analysis of SBF (20) shows that its SOPs include 23 literals. Each literal corresponds to a single wire connecting a LUT input with a source of a particular state variable. Clearly, the fewer literals there are, the fewer interconnects the FSM circuit includes. The fewer interconnects, the less power is consumed and the less chip area is occupied by FSM circuit [40].

In the worst case, the SBF (3) includes $RN$ literals. In the discussed case, there is RN = 36. So, the proposed style of state encoding allows eliminating 13 literals (36% of literals).

System (20) represents the circuit of $LUTerY$. Having maximum binary and partial state codes, we can create tables for all other blocks of LUT-based circuit of Moore FSM S1.

Step 6. Table of $LUTerFD$ has the following columns: $a_m$ (the current state belonging to the set $A_{FD}$), $PC\left(a_m\right)$, $a_s$ (state of transition), $K\left(a_s\right)$, $X_h$, $D_h$, h. Because System (3) is already obtained, there is no information about FSM outputs in the first column of this table.

In the discussed case, the table is constructed using information from Rows 1–6 of STT (Table 1). The block $LUTerFD$ is represented by Table 2.

Table 2. Table of $LUTerFD$.

${\mathit{a}}_{\mathit{m}}$	$\mathit{PC}\left({\mathit{a}}_{\mathit{m}}\right)$	${\mathit{a}}_{\mathit{s}}$	$\mathit{K}\left({\mathit{a}}_{\mathit{s}}\right)$	${\mathit{X}}_{\mathit{h}}$	${\mathit{D}}_{\mathit{h}}$	h
$a_1$	1	$a_2$	0100	$x_1{x}_2{x}_3$	$D_2$	1
		$a_4$	1010	$x_1{x}_2\overline{x_3}$	$D_1{D}_3$	2
		$a_5$	0001	$x_1\overline{x_2}$	$D_4$	3
		$a_3$	0010	$\overline{x_1}{x}_4$	$D_3$	4
		$a_6$	0101	$\overline{x_1}\overline{x_4}{x}_5$	$D_2{D}_4$	5
		$a_7$	1011	$\overline{x_1}\overline{x_4}\overline{x_5}$	$D_1{D}_3{D}_4$	6

Of course, partial IMFs shown in column $D_h$ should have the superscript “0”. We do not show this superscript to simplify the table. The same is applied to all other tables. The table of $LUTerFD$ is a base for constructing SBF (15). Using Table 1, we can derive, for example, the following sum of products of the partial IMF $D_1^0$:

$$D_1^0=F_2\vee F_6=v_1{x}_1{x}_2\overline{x_3}\vee v_1\overline{x_1}\overline{x_4}\overline{x_5}$$

(21)

There are six literals in (21). So, the corresponding LUT-based circuit should be designed using the methods of functional decomposition.

Step 7. Tables of blocks $LUTer1-LUTer2$ have the same columns as Table 2. But for $LUTerk$, the following relation holds for all states from the column $a_m$: $a_m\in A^k (k\in \{1, 2\})$.

To construct the table of $LUTer1$ (Table 3), the following rows of Table 1 are used: 7–9, 13–18, 25–28. The partial state codes are taken from Figure 6.

Table 3. Table of $LUTer1$.

${\mathit{a}}_{\mathit{m}}$	$\mathit{PC}\left({\mathit{a}}_{\mathit{m}}\right)$	${\mathit{a}}_{\mathit{s}}$	$\mathit{K}\left({\mathit{a}}_{\mathit{s}}\right)$	${\mathit{X}}_{\mathit{h}}$	${\mathit{D}}_{\mathit{h}}$	h
$a_2$	010	$a_8$	1001	$x_6{x}_7$	$D_1{D}_4$	1
		$a_9$	1000	$x_6\overline{x_7}$	$D_1$	2
		$a_4$	1010	$\overline{x_6}$	$D_1{D}_3$	3
$a_4$	110	$a_8$	1001	$x_6{x}_7$	$D_1{D}_4$	4
		$a_9$	1000	$x_6\overline{x_7}$	$D_1$	5
		$a_4$	1010	$\overline{x_6}$	$D_1{D}_3$	6
$a_5$	011	$a_8$	1001	$x_6{x}_7$	$D_1{D}_4$	7
		$a_9$	1000	$x_6\overline{x_7}$	$D_1$	8
		$a_4$	1010	$\overline{x_6}$	$D_1{D}_3$	9
$a_8$	100	$a_2$	0100	$x_6$	$D_2$	10
		$a_1$	0000	$\overline{x_6}$	–	11
$a_9$	101	$a_2$	0100	$x_6$	$D_2$	12
		$a_1$	0000	$\overline{x_6}$	–	13

To construct the table of $LUTer2$ (Table 4), the following rows of Table 1 are used: 10–12, 19–24, 29–32. The partial state codes are taken from Figure 7.

Table 4. Table of $LUTer2$.

${\mathit{a}}_{\mathit{m}}$	$\mathit{PC}\left({\mathit{a}}_{\mathit{m}}\right)$	${\mathit{a}}_{\mathit{s}}$	$\mathit{K}\left({\mathit{a}}_{\mathit{s}}\right)$	${\mathit{X}}_{\mathit{h}}$	${\mathit{D}}_{\mathit{h}}$	h
$a_3$	010	$a_{10}$	0111	$x_4{x}_5$	$D_2{D}_3{D}_4$	1
		$a_{11}$	1100	$x_4\overline{x_5}$	$D_1{D}_2$	2
		$a_5$	0001	$\overline{x_4}$	$D_4$	3
$a_6$	110	$a_{10}$	0111	$x_4{x}_5$	$D_2{D}_3{D}_4$	4
		$a_{11}$	1100	$x_4\overline{x_5}$	$D_1{D}_2$	5
		$a_5$	0001	$\overline{x_4}$	$D_4$	6
$a_7$	011	$a_{10}$	0111	$x_4{x}_5$	$D_2{D}_3{D}_4$	7
		$a_{11}$	1100	$x_4\overline{x_5}$	$D_1{D}_2$	8
		$a_5$	0001	$\overline{x_4}$	$D_4$	9
$a_{10}$	100	$a_6$	0101	$x_5$	$D_2{D}_4$	10
		$a_1$	0000	$\overline{x_5}$	–	11
$a_{11}$	101	$a_6$	0101	$x_5$	$D_2{D}_4$	12
		$a_1$	0000	$\overline{x_5}$	–	13

Using Table 3 and generalized intervals from the Karnaugh map (Figure 6), the following SBF is constructed:

$$D_1^1={\tau }_2;D_2^1={\tau }_1\overline{{\tau }_2};D_3^1={\tau }_2\overline{x_6};D_4^1={\tau }_2{x}_6{x}_7.$$

(22)

Using Table 4 and generalized intervals from the Karnaugh map (Figure 7), the following SBF is constructed:

$$\begin{array}{c}{D}_1^2={\tau }_5{x}_4\overline{x_5};\hfill \\ D_2^2={\tau }_5{x}_4\vee {\tau }_4\overline{{\tau }_5}{x}_5;\hfill \\ D_3^2={\tau }_5{x}_4{x}_5;\hfill \\ D_4^2={\tau }_5{x}_4{x}_5\vee {\tau }_4\overline{{\tau }_5}{x}_5.\hfill \end{array}$$

(23)

The SBF (22) is a base for implementing the circuit of block $LUTer1$. As follows from (22), there is no need in LUT to generate the function $D_1^1$. There is $S_L=5.$ Due to this, we can use a single dual-output LUT [36,37] to generate functions $D_2^1$ and $D_3^1$. So, the proposed method of partial state encoding allows using only two LUTs instead of four. This results in 50% economy.

The SBF (23) is a base for constructing the circuit of block $LUTer2$. As follows from (23), we can use double-output LUTs for implementing pairs of partial IMFs. This results in 50% economy.

Step 8. The functional assembler (block $LUTerT$) gets the partial IMFs $D_r^k$ and generates the IMFs $D_r\in D$. In the general case, this block is represented by the table having $K+2$ columns. The first column contains the symbols of IMFs $D_r\in D$, other columns are marked by the numbers 0, 1, 2, …, K. The column 0 corresponds to the block $LUTerFD$. We mark the intersections of rows and columns by either minus or plus. The fact that an IMF $D_r^k\in A^k$ is generated by a LUT of some block is marked by + ($k\in \{0, 1, \dots , K\}$). The opposite situation is marked by -. In the discussed case, the block $LUTerT$ is represented by Table 5.

Table 5. Table of $LUTerT$.

${\mathit{D}}_{\mathit{r}}$	0	1	2
$D_1$	+	+	+
$D_2$	+	+	+
$D_3$	+	+	+
$D_4$	+	+	+

Table 5 is a base for generating final values of IMFs represented by (16). The following SBF is derived from Table 5:

$$\begin{array}{c}{D}_1=D_1^0\vee D_1^1\vee D_1^2;\hfill \\ D_2=D_2^0\vee D_2^1\vee D_2^2;\hfill \\ D_3=D_3^0\vee D_3^1\vee D_3^2;\hfill \\ D_4=D_4^0\vee D_4^1\vee D_4^2.\hfill \end{array}$$

(24)

Step 9. The table of $LUTer\tau V$ shows a law of code transformation. It has the following columns: $a_m, K\left(a_m\right), PC\left(a_m\right), {\tau }_1, \dots , {\tau }_K, v_1, \dots , v_{RFD}$. For the discussed case, Table 6 represents the block $LUTer\tau V$.

Table 6. Table of block $LUTer\tau V$.

${\mathit{a}}_{\mathit{m}}$	$\mathit{K}\left({\mathit{a}}_{\mathit{m}}\right)$	$\mathit{PC}\left({\mathit{a}}_{\mathit{m}}\right)$	${\mathit{\tau }}_1$	${\mathit{\tau }}_2$	${\mathit{\tau }}_3$	${\mathit{\tau }}_4$	${\mathit{\tau }}_5$	${\mathit{\tau }}_6$	${\mathit{v}}_1$
$a_2$	0100	010	0	1	0	0	0	0	0
$a_3$	0010	010	0	0	0	0	1	0	0
$a_4$	1010	110	1	1	0	0	0	0	0
$a_5$	0001	011	0	1	1	0	0	0	0
$a_6$	0101	110	0	0	0	1	1	0	0
$a_7$	1011	011	0	0	0	0	1	1	0
$a_8$	1001	100	1	0	0	0	0	0	0
$a_9$	1000	101	1	0	1	0	0	0	0
$a_{10}$	0111	100	0	0	0	1	0	0	0
$a_{11}$	1100	101	0	0	0	1	0	1	0
$a_1$	0000	1	0	0	0	0	0	0	$v_1$

In this table, the codes $K\left(a_m\right)$ are taken from the Karnaugh map (Figure 8). The partial state codes $PC\left(a_m\right)$ are taken from maps shown in Figure 6 (class $A^1$) and in Figure 7 (class $A^2$). The last seven columns of this table represent extended state codes. For example, from Table 6, we can find the extended codes $EC\left(a_2\right)=0100000$, $EC\left(a_3\right)=0000100$, and so on.

Analysis of SBF (23) shows that there is no need in generating state variables ${\tau }_3$ and ${\tau }_6$. So, using PES for partial state encoding allows eliminating around 30% of LUTs from the block $LUTer\tau V$.

The SOPs of Functions (11) and (17) are similar to SOPs of Functions (3). In the discussed case, the following SBFs are derived from Table 6:

$$\begin{array}{c}{\tau }_1=A_4\vee A_8\vee A_9=T_1\overline{T_2}\overline{T_3}\vee T_1\overline{T_2}\overline{T_4};\hfill \\ {\tau }_2=A_2\vee A_4\vee A_5={\tau }_2(T_1, \dots , T_4);\hfill \\ {\tau }_4=A_6\vee A_{10}\vee A_{11}=T_2{T}_4\vee T_1{T}_2;\hfill \\ {\tau }_5=A_3\vee A_6\vee A_7={\tau }_5(T_1, \dots , T_4).\hfill \end{array}$$

(25)

$$v_1=A_1=\overline{T_1}\overline{T_2}\overline{T_3}\overline{T_4}.$$

(26)

Step 10. To implement an FPGA-based FSM circuit, it is necessary to execute the technology mapping. This requires using some industrial package. In the case of chips produced by AMD Xilinx, we use the CAD tool Vivado [48]. We do not show the outcome of implementation for our example. This is due to the fact that Vivado operates with LUTs having six inputs. Because we use the five-input LUTs in our example, the synthesis of FSM S1 is executed manually. But the implementation of FSMs shown in Section 6 is executed using our software.

6. Experimental Results

In this paper, the effectiveness of the proposed method was evaluated using a set of standard benchmark FSMs taken from the library described in [64]. This collection contains 53 Mealy-type benchmark FSMs originating from practical logic design problems. Although these benchmarks are relatively simple, they are widely used in the literature as a common reference for comparing newly proposed approaches with previously published solutions [45,55,61,69]. The benchmark descriptions are provided in the KISS2 format. For the purposes of this study, the original Mealy FSM specifications were converted into equivalent Moore FSM models. This transformation was performed according to the procedure presented in [71]. The basic parameters of the resulting Moore FSMs are summarized in Table 7. The final column of Table 7 shows the sum of the numbers of FSM inputs and state variables.

Table 7. Characteristics of Moore FSMs.

Benchmark	Number of Inputs	Number of Outputs	Number of States	Number of Transitions	Number of State Variables	Sum
	$\mathit{L}$	$\mathit{N}$	$\mathit{M}$	$\mathit{H}$	$\mathit{R}$	$\mathit{L}+\mathit{R}$
bbara	4	2	12	72	4	8
bbsse	7	7	23	104	5	12
bbtas	2	2	9	36	4	6
beecount	3	4	10	40	4	7
cse	7	7	32	183	5	12
dk14	3	5	26	208	5	8
dk15	3	5	17	136	5	8
dk16	2	3	75	300	7	9
dk17	2	3	16	64	4	6
dk27	1	2	10	20	4	5
dk512	1	3	23	48	5	6
donfile	2	1	25	100	5	7
ex1	9	19	80	637	7	16
ex2	2	2	25	92	5	7
ex3	2	2	14	44	4	6
ex4	6	9	17	28	5	11
ex5	2	2	16	52	4	6
ex6	5	8	13	61	4	9
ex7	2	2	17	56	5	7
keyb	7	2	22	193	5	12
kirkman	12	6	139	3817	8	20
lion	2	1	5	14	3	5
lion9	2	1	11	31	4	6
mark1	5	16	21	29	5	10
mc	3	5	8	20	3	6
modulo12	1	1	13	26	4	5
opus	5	6	10	22	4	9
planet	7	19	103	248	7	14
planet1	7	19	103	248	7	14
pma	8	8	49	132	6	14
s1	8	6	20	107	5	13
s1488	8	19	168	912	8	16
s1494	8	19	168	1030	8	16
s1a	8	6	21	115	5	13
s208	11	2	36	309	6	17
s27	4	1	6	34	3	7
s298	3	6	332	1669	9	12
s386	7	7	23	127	5	12
s420	19	2	36	282	6	25
s510	19	7	73	133	7	26
s8	4	1	6	24	3	7
s820	18	19	70	613	7	25
s832	18	19	70	707	7	25
sand	11	9	88	654	7	18
scf	27	56	138	190	8	35
shiftreg	1	1	16	32	4	5
sse	7	7	23	104	5	12
styr	9	10	57	366	6	15
tav	4	4	27	322	5	9
tbk	6	3	60	2942	6	12
tma	7	6	38	72	6	13
train11	2	1	14	34	4	6
train4	2	1	6	21	3	5

All experiments were carried out under the same controlled design environment. For every benchmark, a structural HDL description of the FSM architecture was processed using an identical synthesis flow, including the same toolchain and implementation parameters. The applied state assignment method (such as One-hot or Gray encoding) was selected through the configuration options available in Vivado. After the synthesis stage, the generated Vivado reports and diagnostic messages were analyzed to verify that the inferred FSM structure and the applied state encoding corresponded to the intended design model, as reported in the synthesis summary. No manual optimizations, architecture-specific directives, or additional tuning techniques were introduced during the design flow. All numerical results presented in this work were obtained from post-implementation reports, which guarantees consistent and directly comparable evaluation conditions for all considered FSM architectures and state encoding schemes.

The benchmark descriptions provided in the KISS2 format were converted into VHDL-based FSM models using our dedicated CAD tool K2F [50]. The synthesis and functional simulation of the FSMs were performed in the Active-HDL design environment. The final hardware implementations were generated using Vivado v2025.1 [48].

As the target device, we selected the AMD Xilinx FPGA Virtex UltraScale+ xcvu29p-fsga2577-2L-e [42,72]. This device is based on configurable logic blocks containing LUT elements with six inputs. Each CLB includes eight such base LUTs.

The internal architecture of the device allows the construction of larger LUT structures by combining base LUTs with dedicated multiplexers. In this way, so-called super-LUTs can be formed with seven, eight, or nine inputs. Specifically, a slice can implement four seven-input LUTs, two eight-input LUTs, or a single nine-input LUT. The creation of these structures relies on the dedicated multiplexers available in the FPGA fabric: F7 MUX for seven-input LUTs, F8 MUX for eight-input LUTs, and F9 MUX for nine-input LUTs.

In the beginning, we compared our approach with three other methods used by Vivado v2025.1 (these methods are Auto, One-hot, and Gray). But for all benchmarks, Auto-based circuits always have the worst characteristics. Due to this, we show experimental results for One-hot-based FSMs (Table 8), Grey-based FSMs (Table 9), FSMs $U_2$ (Table 10), and FSMs $U_3$ (Table 11).

Table 8. Experimental results for One-hot-based FSMs.

Benchmark	LUTs	F7 MUX	F8 MUX	Registers	Delay (ns)	Freq. (MHz)	Power (W)
bbara	17	0	0	12	2.494	400.96	2.723
bbsse	27	0	0	23	2.560	390.63	3.712
bbtas	9	0	0	9	2.531	395.10	2.805
beecount	18	0	0	10	3.554	281.37	3.705
cse	55	0	0	32	2.774	360.49	3.568
dk14	31	0	0	26	3.355	298.06	5.732
dk15	20	0	0	17	2.788	358.68	5.052
dk16	84	0	0	75	3.169	315.56	6.961
dk17	18	0	0	16	2.927	341.65	5.409
dk27	7	0	0	10	3.051	327.76	4.116
dk512	15	0	0	21	3.017	331.46	4.752
donfile	31	0	0	25	2.870	348.43	3.222
ex1	143	0	0	80	4.121	242.66	4.490
ex2	11	1	0	14	2.562	390.32	2.690
ex3	12	1	0	13	2.542	393.39	2.667
ex4	18	0	0	17	2.753	363.24	3.378
ex5	12	0	0	14	2.599	384.76	2.798
ex6	23	0	0	13	3.074	325.31	7.555
ex7	6	0	0	7	2.666	375.09	2.584
keyb	36	0	0	22	3.669	272.55	3.364
kirkman	267	0	0	139	4.777	209.34	5.048
lion	5	0	0	5	2.640	378.79	2.784
lion9	12	0	0	11	3.206	311.92	2.927
mark1	19	0	0	20	3.743	267.17	3.040
mc	10	0	0	8	2.736	365.50	3.735
modulo12	7	0	0	13	2.283	438.02	2.720
opus	16	0	0	10	3.463	288.77	3.900
planet	147	0	0	103	4.037	247.71	13.386
planet1	147	0	0	103	4.037	247.71	13.386
pma	83	0	0	49	3.325	300.75	5.049
s1	42	0	0	20	3.558	281.06	6.741
s1488	232	0	0	168	5.113	195.58	7.025
s1494	232	0	0	168	5.847	171.03	7.043
s1a	36	0	0	21	3.051	327.76	2.868
s208	61	0	0	36	2.873	348.07	3.343
s27	10	0	0	6	2.446	408.83	3.256
s298	1143	14	0	341	9.276	107.81	11.008
s386	29	0	0	23	2.684	372.58	3.661
s420	62	0	0	36	3.920	255.10	3.331
s510	64	0	0	73	4.597	217.53	5.757
s8	11	0	0	6	2.446	408.83	2.787
s820	103	0	0	70	3.665	272.85	4.908
s832	104	0	0	70	3.531	283.21	4.918
sand	136	0	0	88	4.387	227.95	7.000
scf	111	0	0	135	6.787	147.34	4.952
shiftreg	11	0	0	16	2.565	389.86	3.397
sse	27	0	0	23	2.560	390.63	3.712
styr	91	0	0	57	3.629	275.56	4.056
tav	31	0	0	27	3.569	280.19	3.722
tbk	152	0	0	60	3.445	290.28	3.618
tma	59	0	0	38	4.009	249.44	3.482
train11	14	0	0	14	3.196	312.89	2.879
train4	5	0	0	6	2.671	374.39	2.828
Total	4072	16	0	2419	183.148	16,541.89	243.500

Table 9. Experimental results for Gray-based FSMs.

Benchmark	LUTs	F7 MUX	F8 MUX	Registers	Delay (ns)	Freq. (MHz)	Power (W)
bbara	18	0	0	4	2.716	368.19	3.300
bbsse	36	3	0	5	2.636	379.36	7.750
bbtas	6	0	0	4	2.583	387.15	3.600
beecount	12	4	0	4	2.855	350.26	5.899
cse	55	10	0	5	3.059	326.90	5.155
dk14	25	10	5	5	2.854	350.39	9.755
dk15	20	0	0	5	3.453	289.60	8.376
dk16	70	22	0	7	3.758	266.10	7.730
dk17	7	0	0	4	2.537	394.17	6.233
dk27	4	0	0	4	2.725	366.97	3.897
dk512	8	0	0	5	2.612	382.85	4.473
donfile	11	5	0	5	3.077	324.99	3.579
ex1	177	27	0	7	3.526	283.61	18.548
ex2	5	0	0	4	2.720	367.65	2.953
ex3	6	0	0	4	2.517	397.30	4.521
ex4	22	0	0	5	2.687	372.16	5.824
ex5	5	0	0	4	2.823	354.23	4.232
ex6	19	2	0	4	2.664	375.38	12.036
ex7	5	0	0	4	2.823	354.23	3.593
keyb	42	5	1	5	3.221	310.46	4.324
kirkman	377	53	9	8	5.990	166.94	14.522
lion	3	0	0	3	2.638	379.08	2.754
lion9	5	0	0	4	2.549	392.31	2.775
mark1	29	0	0	5	2.845	351.49	8.345
mc	6	0	0	3	2.659	376.08	5.522
modulo12	3	0	0	4	2.362	423.37	2.630
opus	18	0	0	4	2.863	349.28	4.560
planet	129	33	0	7	3.411	293.17	20.657
planet1	129	33	0	7	3.411	293.17	20.657
pma	73	6	0	6	2.874	347.95	12.260
s1	53	7	0	5	3.089	323.73	10.869
s1488	291	33	2	10	5.280	189.39	26.114
s1494	293	31	1	10	5.670	176.37	26.202
s1a	49	9	1	5	3.257	307.03	5.447
s208	45	5	0	6	2.791	358.29	5.388
s27	7	3	0	3	2.456	407.17	3.696
s298	607	198	79	39	4.373	228.68	21.491
s386	36	4	0	5	2.642	378.50	7.201
s420	60	12	3	6	2.972	336.47	4.179
s510	51	4	1	7	4.080	245.10	8.502
s8	7	3	0	3	2.453	407.66	3.594
s820	151	27	7	7	3.662	273.07	10.973
s832	145	24	5	7	4.168	239.92	10.298
sand	125	19	0	7	3.278	305.06	11.072
scf	194	19	1	8	8.929	111.99	25.147
shiftreg	3	0	0	4	2.362	423.37	3.989
sse	36	3	0	5	2.636	379.36	7.750
styr	97	14	1	6	3.026	330.47	10.220
tav	25	5	0	5	3.094	323.21	7.392
tbk	136	14	0	6	3.812	262.33	6.286
tma	53	7	0	6	2.772	360.75	9.646
train11	5	0	0	4	2.584	387.00	2.748
train4	2	0	0	3	2.441	409.67	2.923
Total	3796	654	116	312	171.275	17,539.40	451.587

Table 10. Experimental results for $U_2$-based FSMs.

Benchmark	LUTs	F7 MUX	F8 MUX	Registers	Delay (ns)	Freq. (MHz)	Power (W)
bbara	17	0	0	4	2.716	368.19	2.723
bbsse	27	0	0	5	2.636	379.36	3.712
bbtas	6	0	0	4	2.583	387.15	3.600
beecount	12	4	0	4	2.855	350.26	5.899
cse	55	10	0	5	3.059	326.90	5.155
dk14	25	10	5	5	2.854	350.39	9.755
dk15	20	0	0	5	3.453	289.60	8.376
dk16	70	22	0	7	3.758	266.10	7.730
dk17	7	0	0	4	2.537	394.17	6.233
dk27	4	0	0	4	2.725	366.97	3.897
dk512	8	0	0	5	2.612	382.85	4.473
donfile	11	5	0	5	3.077	324.99	3.579
ex1	130	0	0	7	3.338	299.58	4.939
ex2	5	0	0	4	2.720	367.65	2.953
ex3	6	0	0	4	2.517	397.30	4.521
ex4	22	0	0	5	2.687	372.16	3.378
ex5	5	0	0	4	2.823	354.23	4.232
ex6	19	2	0	4	2.664	375.38	12.036
ex7	5	0	0	4	2.823	354.23	3.593
keyb	36	0	0	5	3.221	310.46	3.090
kirkman	240	4	0	8	3.822	261.64	5.553
lion	3	0	0	3	2.638	379.08	2.754
lion9	5	0	0	4	2.549	392.31	2.775
mark1	19	0	0	5	2.845	351.49	3.040
mc	6	0	0	3	2.659	376.08	5.522
modulo12	3	0	0	4	2.362	423.37	2.630
opus	18	0	0	4	2.863	349.28	3.900
planet	131	7	0	9	3.310	302.11	14.725
planet1	131	7	0	9	3.310	302.11	14.725
pma	75	0	0	6	2.727	366.70	5.554
s1	38	2	0	5	2.882	346.98	7.415
s1488	211	6	0	8	4.090	244.50	7.727
s1494	209	8	0	8	4.678	213.77	7.677
s1a	34	0	0	5	2.471	404.69	3.140
s208	41	3	0	6	2.289	436.87	3.677
s27	7	3	0	3	2.456	407.17	3.696
s298	546	12	12	9	3.585	278.94	12.021
s386	29	0	0	5	2.642	378.50	7.201
s420	60	12	0	6	2.972	336.47	4.179
s510	51	4	0	7	4.080	245.10	8.502
s8	7	3	0	3	2.453	407.66	3.594
s820	103	27	0	7	3.662	273.07	4.908
s832	104	24	0	7	4.168	239.92	4.918
sand	136	19	0	7	3.278	305.06	7.000
scf	111	19	0	8	8.929	118.99	4.952
shiftreg	3	0	0	4	2.362	423.37	3.989
sse	25	0	0	5	2.074	482.16	4.076
styr	83	0	0	6	2.903	344.47	4.461
tav	25	5	0	5	3.094	323.21	7.392
tbk	136	14	0	6	3.812	262.33	6.286
tma	49	3	0	6	2.273	439.95	3.830
train11	5	0	0	4	2.584	387.00	2.748
train4	2	0	0	3	2.441	409.67	2.923
Total	3136	235	17	282	162.921	18,224.98	291.364

Table 11. Experimental results for $U_3$-based FSMs.

Benchmark	LUTs	F7 MUX	F8 MUX	Registers	Delay (ns)	Freq. (MHz)	Power (W)
bbara	17	0	0	4	2.716	368.19	2.723
bbsse	27	0	0	5	2.636	379.36	3.712
bbtas	6	0	0	4	2.583	387.15	3.600
beecount	12	4	0	4	2.855	350.26	5.899
cse	55	10	0	5	3.059	326.90	5.155
dk14	25	10	5	5	2.854	350.39	9.755
dk15	20	0	0	5	3.453	289.60	8.376
dk16	70	22	0	7	3.758	266.10	7.730
dk17	7	0	0	4	2.537	394.17	6.233
dk27	4	0	0	4	2.725	366.97	3.897
dk512	8	0	0	5	2.612	382.85	4.473
donfile	11	5	0	5	3.077	324.99	3.579
ex1	130	0	0	7	3.338	299.58	4.939
ex2	5	0	0	4	2.720	367.65	2.953
ex3	6	0	0	4	2.517	397.30	4.521
ex4	22	0	0	5	2.687	372.16	3.378
ex5	5	0	0	4	2.823	354.23	4.232
ex6	19	2	0	4	2.664	375.38	12.036
ex7	5	0	0	4	2.823	354.23	3.593
keyb	36	0	0	5	3.221	310.46	3.090
kirkman	240	4	0	8	3.822	261.64	5.553
lion	3	0	0	3	2.638	379.08	2.754
lion9	5	0	0	4	2.549	392.31	2.775
mark1	19	0	0	5	2.845	351.49	3.040
mc	6	0	0	3	2.659	376.08	5.522
modulo12	3	0	0	4	2.362	423.37	2.630
opus	18	0	0	4	2.863	349.28	3.900
planet	131	7	0	9	3.310	302.11	14.725
planet1	131	7	0	9	3.310	302.11	14.725
pma	75	0	0	6	2.727	366.70	5.554
s1	38	2	0	5	2.882	346.98	7.415
s1488	211	0	0	8	4.090	244.50	7.727
s1494	209	0	0	8	4.678	213.77	7.677
s1a	34	0	0	5	2.471	404.69	3.140
s208	41	3	0	6	2.289	436.87	3.677
s27	7	3	0	3	2.456	407.17	3.696
s298	546	12	7	9	3.585	278.94	12.021
s386	29	0	0	5	2.642	378.50	7.201
s420	55	7	0	6	2.705	369.69	4.031
s510	47	3	0	7	3.713	269.32	6.851
s8	7	3	0	3	2.453	407.66	3.594
s820	95	14	0	7	2.705	369.69	5.810
s832	96	12	0	7	3.930	254.45	5.852
sand	124	11	0	7	3.108	321.75	8.360
scf	102	10	0	8	8.411	118.89	5.942
shiftreg	3	0	0	4	2.362	423.37	3.989
sse	25	0	0	5	2.074	482.16	4.076
styr	83	0	0	6	2.903	344.47	4.461
tav	25	5	0	5	3.094	323.21	7.392
tbk	136	14	0	6	3.812	262.33	6.286
tma	49	0	0	6	2.273	439.95	3.830
train11	5	0	0	4	2.584	387.00	2.748
train4	2	0	0	3	2.441	409.67	2.923
Total	3090	170	12	282	160.404	18,417.14	293.751

All tables use an identical set of columns describing the obtained implementation results. The column Benchmark contains the name of the analyzed FSM. The column LUTs specifies the number of base LUT elements used in the implementation. The columns F7 MUX and F8 MUX show the numbers of multiplexers required to construct super-LUT structures with seven and eight inputs, respectively. The column Registers indicates the number of D flip-flops used to implement the FSM state register. The column Delay represents the clock cycle time, while Freq. denotes the corresponding maximum operating frequency. Finally, the column Power provides the measured value of the consumed power.

While creating Table 11, we found that inside the library used there are groups of simple, complex, and very complex benchmarks. The simple benchmarks fulfill the following condition: $L+R\le 2S_L$. For complex FSMs, this condition is violated and Condition (5) holds for each IMF. For very complex FSMs, Condition (5) is violated (this means that Condition (6) takes place).

The group of complex FSMs contains 14 benchmarks (ex1, kirkman, planet, planet1, pma, s1, s1488, s1494, s1a, s208, s298, styr, tma). The group of very complex FSMs consists of six benchmarks (s420, s510, s820, s832, sand, scf). Obviously, 33 other benchmarks included in Table 7 are simple.

For simple FSMs, any SOP from SBFs (2) and (3) is represented by a single-LUT circuit. So, there is no need in using any kind of decomposition for implementing LUT-based circuits of simple FSMs. The main goal of our method is to obtain an FSM circuit with a minimum value of LUT count. So, we chose either One-hot or Grey state codes. The choice was reduced to comparison of the values of LUT counts for these models (Table 8 and Table 9). In the case of $U_2$-based complex FSMs, the same choice was made. The $U_3$-based FSMs (both simple and complex) have the same characteristics as their $U_2$-based counterparts. For very complex $U_3$-based FSMs, the results were taken from Vivado reports. Using Table 8, Table 9, Table 10 and Table 11, we created Table 12 and Table 13 to compare two basic characteristics of produced FSM circuits (these characteristics are the LUT count and operating frequency). We did not compare the values of power consumption, because, for various models, these results were obtained using different values of operating frequency.

Table 12. Experimental results (LUT count).

Benchmark	One-Hot	Gray	${\mathit{U}}_2$	${\mathit{U}}_3$
bbara	17	18	17	17
bbsse	27	36	27	27
bbtas	9	6	6	6
beecount	18	12	12	12
cse	55	55	55	55
dk14	31	25	25	25
dk15	20	20	20	20
dk16	84	70	70	70
dk17	18	7	7	7
dk27	7	4	4	4
dk512	15	8	8	8
donfile	31	11	11	11
ex1	143	177	130	130
ex2	11	5	5	5
ex3	12	6	6	6
ex4	18	22	22	22
ex5	12	5	5	5
ex6	23	19	19	19
ex7	6	5	5	5
keyb	36	42	36	36
kirkman	267	377	240	240
lion	5	3	3	3
lion9	12	5	5	5
mark1	19	29	19	19
mc	10	6	6	6
modulo12	7	3	3	3
opus	16	18	18	18
planet	147	129	131	131
planet1	147	129	131	131
pma	83	73	75	75
s1	42	53	38	38
s1488	232	291	211	211
s1494	232	293	209	209
s1a	36	49	34	34
s208	61	45	41	41
s27	10	7	7	7
s298	1143	607	546	546
s386	29	36	29	29
s420	62	60	60	55
s510	64	51	51	47
s8	11	7	7	7
s820	103	151	103	95
s832	104	145	104	96
sand	136	125	136	124
scf	111	194	111	102
shiftreg	11	3	3	3
sse	27	36	25	25
styr	91	97	83	83
tav	31	25	25	25
tbk	152	136	136	136
tma	59	53	49	49
train11	14	5	5	5
train4	5	2	2	2
Total	4072	3796	3136	3090
Percentage, %	131.78	122.85	101.49	100.00

Table 13. Experimental results (maximum operating frequency, MHz).

Benchmark	One-Hot	Gray	${\mathit{U}}_2$	${\mathit{U}}_3$
bbara	400.96	368.19	368.19	368.19
bbsse	390.63	379.36	379.36	379.36
bbtas	395.10	387.15	387.15	387.15
beecount	281.37	350.26	350.26	350.26
cse	360.49	326.90	326.90	326.90
dk14	298.06	350.39	350.39	350.39
dk15	358.68	289.60	289.60	289.60
dk16	315.56	266.10	266.10	266.10
dk17	341.65	394.17	394.17	394.17
dk27	327.76	366.97	366.97	366.97
dk512	331.46	382.85	382.85	382.85
donfile	348.43	324.99	324.99	324.99
ex1	242.66	283.61	299.58	299.58
ex2	390.32	367.65	367.65	367.65
ex3	393.39	397.30	397.30	397.30
ex4	363.24	372.16	372.16	372.16
ex5	384.76	354.23	354.23	354.23
ex6	325.31	375.38	375.38	375.38
ex7	375.09	354.23	354.23	354.23
keyb	272.55	310.46	310.46	310.46
kirkman	209.34	166.94	261.64	261.64
lion	378.79	379.08	379.08	379.08
lion9	311.92	392.31	392.31	392.31
mark1	267.17	351.49	351.49	351.49
mc	365.50	376.08	376.08	376.08
modulo12	438.02	423.37	423.37	423.37
opus	288.77	349.28	349.28	349.28
planet	247.71	293.17	302.11	302.11
planet1	247.71	293.17	302.11	302.11
pma	300.75	347.95	366.70	366.70
s1	281.06	323.73	346.98	346.98
s1488	195.58	189.39	244.50	244.50
s1494	171.03	176.37	213.77	213.77
s1a	327.76	307.03	404.69	404.69
s208	348.07	358.29	436.87	436.87
s27	408.83	407.17	407.17	407.17
s298	107.81	228.68	278.94	278.94
s386	372.58	378.50	378.50	378.50
s420	255.10	336.47	336.47	369.69
s510	217.53	245.10	245.10	269.32
s8	408.83	407.66	407.66	407.66
s820	272.85	273.07	273.07	369.69
s832	283.21	239.92	239.92	254.45
sand	227.95	305.06	305.06	321.75
scf	147.34	111.99	111.99	118.89
shiftreg	389.86	423.37	423.37	423.37
sse	390.63	379.36	482.16	482.16
styr	275.56	330.47	344.47	344.47
tav	280.19	323.21	323.21	323.21
tbk	290.28	262.33	262.33	262.33
tma	249.44	360.75	439.95	439.95
train11	312.89	387.00	387.00	387.00
train4	374.39	409.67	409.67	409.67
Total	16,541.89	17,539.40	18,224.98	18,417.14
Percentage, %	89.82	95.23	98.96	100.00

Table 12 and Table 13 follow an identical layout. In both tables, the rows correspond to the individual benchmark FSMs, whereas the columns represent the considered design methods. The rows labeled “Total” contain the aggregated values obtained by summing the corresponding metrics for all benchmarks. The overall characteristics of FSMs implemented using the U₃ model are treated as the reference point and normalized to 100%. The rows marked “Percentage” present the relative values of the summarized characteristics, expressed as percentages with respect to the results obtained for U₃-based FSM implementations.

As follows from Table 12, U₃-based FSMs are represented by circuits requiring fewer LUTs than other investigated methods. There is the following gain: (1) 31.78% regarding One-hot-based FSMs; (2) 22.85% regarding Grey-based FSMs; and (3) 1.49% regarding $U_2$-based FSMs. The analysis of Table 12 shows that our approach gives better results for FSMs where Condition (6) takes place. So, the gain is obtained for very complex FSMs.

The same is true for the maximum values of operating frequency. As follows from Table 13, the U₃-based FSMs have higher operating frequencies than their counterparts based on other investigated methods. The gain in frequency is the following: (1) 10.18% regarding One-hot-based FSMs; (2) 4.77% regarding Grey-based FSMs; and (3) 1.04% regarding $U_2$-based FSMs. As it is for values of LUT counts, the proposed approach gives better results for FSMs where Condition (6) takes place.

To provide a comprehensive comparison of the characteristics of the designed FSM circuits, Table 14 has been prepared. This table collects and summarizes all aggregated results presented previously in Table 8, Table 9, Table 10, Table 11, Table 12 and Table 13.

Table 14. Total results for all benchmarks.

	One-Hot	Gray	${\mathit{U}}_2$	${\mathit{U}}_3$
Total LUTs	4072	3796	3136	3090
Percentage LUTs, %	131.78	122.85	101.49	100.00
Total Registers	2419	312	282	282
Percentage Registers, %	857.80	110.64	100.00	100.00
Total Frequency	16,541.89	17,539.40	18,224.98	18,417.14
Percentage Frequency, %	89.82	95.23	98.96	100.00
Total Power	243.550	451.587	291.364	293.751
Percentage Power, %	82.91	153.73	99.19	100.00

According to the data presented in Table 14, the proposed approach demonstrates slightly better overall spatial and temporal characteristics. The primary objective of the method is to reduce the number of LUTs required for FSM implementation while avoiding a noticeable degradation of timing performance.

The analysis of Table 12, Table 13 and Table 14 confirms that this goal has been achieved. However, a meaningful evaluation of synthesis results is particularly relevant for FSMs of higher complexity. For this reason, the comparison focused on complex benchmarks is presented separately in Table 15.

Table 15. Total results for very complex FSMs.

	One-Hot	Gray	${\mathit{U}}_2$	${\mathit{U}}_3$
Total LUTs	580	726	565	519
Percentage LUTs, %	111.75	139.88	108.86	100.00
Total Registers	472	42	42	42
Percentage Registers, %	1123.81	100.00	100.00	100.00
Total Frequency	1403.98	1511.63	1511.63	1703.79
Percentage Frequency, %	82.40	88.72	88.72	100.00
Total Power	30.866	70.171	34.459	36.846
Percentage Power, %	83.77	190.44	93.52	100.00

As follows from Table 15, the proposed approach allows producing FSM circuits with better spatial and temporal characteristics than their counterparts used for comparison. Our analysis of Table 15 shows the following gain in the number of LUTs used: (1) 11.75% regarding One-hot-based FSMs; (2) 39.88% regarding Grey-based FSMs; and (3) 8.86% regarding $U_2$-based FSMs. The following gain in frequency could be found from Table 15: (1) 17.6% regarding One-hot-based FSMs; (2) 11.28% regarding Grey-based FSMs; and (3) 11.28% regarding $U_2$-based FSMs. So, our approach allows improving both spatial and temporal characteristics for very complex FSMs. Moreover, only this approach allows using methods of structural decomposition for optimizing circuits of very complex FSMs. For all other models used, the optimization is connected with functional decomposition of SBFs (2) and (3).

Let us analyze the reasons why, for highly complex FSMs, implementations based on the $U_3$ model demonstrate better spatial and temporal characteristics than their $U_2$-based counterparts. The model $U_2$ relies on the concept of twofold state assignment. However, this approach cannot be applied when Condition (13) is violated. In such situations, some states become incompatible with the remaining ones and therefore cannot be included in any compatibility class.

When Condition (13) is not satisfied, the $U_2$ model effectively degenerates into the $U_1$ model. As a consequence, the resulting $U_1$-based circuit contains numerous partial functions associated with the states for which (13) holds. Moreover, such circuits typically require a greater number of logic levels.

In the proposed approach, states that violate Condition (13) are encoded using partial state codes that contain fewer bits than the maximum binary state codes applied in $U_1$. This encoding strategy reduces the number of logic levels required in the circuits generating input memory functions when compared with equivalent $U_1$-based FSM implementations.

Consequently, the $U_3$ architecture achieves higher performance in comparison with the corresponding $U_2$-based FSMs, which in these cases effectively operate according to the $U_1$ model. In addition, the use of partial state codes in selected parts of the $U_3$ FSM structure also decreases the number of required LUTs relative to $U_1$-based implementations. As a result, for highly complex FSMs, circuits derived from the $U_3$ model exhibit improved spatial and temporal characteristics compared with both $U_1$- and $U_2$-based solutions.

It should be emphasized that the reported improvement values were obtained specifically for the benchmark set [73] and for the hardware platform represented by the AMD Virtex™ UltraScale+™ 56G PAM4 VCU129 FPGA Evaluation Kit (Virtex7 Ultrascale+ xcvu29p-fsga2577-2L-e) [42,72].

Nevertheless, the experimental results confirm that the proposed design approach can be effectively applied to improve both spatial and temporal characteristics of circuits implementing very complex Moore FSMs.

Table 16 presents a summary of the computational effort related to the FPGA design flow for the considered FSM implementations. The values reported in the table represent the time required to execute the complete Vivado design process for each benchmark. This process includes both the logic synthesis stage and the subsequent implementation steps, such as optimization, placement, and routing.

Table 16. Synthesis and Vivado flow execution times for the analyzed methods.

Time (HH:MM:SS)	One-Hot	Gray	${\mathit{U}}_2$	${\mathit{U}}_3$
Synthesis per Benchmark (Avg.)	00:00:22	00:00:24	00:00:26	00:00:26
Synthesis (Sum)	00:19:28	00:20:46	00:22:37	00:22:43
Vivado Flow per Benchmark (Avg.)	00:04:36	00:04:36	00:04:41	00:04:43
Vivado Flow (Sum)	04:03:22	04:03:34	04:08:55	04:10:14

To enable a clear comparison between the analyzed solutions, the results are reported in two forms: the average processing time per benchmark and the total accumulated processing time calculated for the entire set of benchmarks.

All measurements were obtained under identical tool settings and hardware conditions to eliminate external variability. The experiments were carried out using Vivado v2025.1 on a workstation equipped with an Intel Core i9-14900K processor and 64 GB RAM. The number of parallel threads was explicitly limited to maintain consistent runtime conditions across all evaluated architectures.

7. Conclusions

One of the key challenges in FPGA-based FSM design is the improvement of spatial characteristics of the resulting circuits. In particular, it is desirable to obtain implementations requiring as few LUT elements as possible while avoiding a noticeable degradation of the maximum operating frequency.

For complex FSMs, the synthesis process typically requires the decomposition of the systems of Boolean functions describing the FSM circuit. In many cases, the implementation of LUT-based FSMs relies exclusively on functional decomposition.

In this work, we introduce a design method that combines functional and structural decomposition techniques [2] in order to improve the characteristics of LUT-based Moore FSM circuits. The proposed approach employs two separate cores generating partial Boolean functions. As a result, functional decomposition is applied only to a selected portion of the FSM circuit.

The experimental results indicate that the proposed design method produces FSM circuits with improved spatial characteristics (expressed by lower LUT counts) as well as better temporal properties (higher maximum operating frequency) when compared with equivalent implementations obtained using either functional or structural decomposition alone.

For comparison, the reference FSM circuits were synthesized using three different state encoding strategies: One-hot, Gray, and twofold state assignment. The structural decomposition (SD-based approach employing twofold state assignment) can be applied only when Condition (5) is satisfied. If this condition is not met, the synthesis process must rely solely on functional decomposition.

The method proposed in this work removes this limitation and enables the effective application of SD-based techniques even in cases where Condition (5) is violated.

As the experiments show, the proposed design method allows increasing both spatial and temporal characteristics of LUT-based FSM circuits. For very complex FSMs, the gain in LUTs is from 11.75% to 39.88% compared with FD-based methods and 8.86% compared to twofold state assignment. At the same time, the temporal characteristics of resulting circuits are even better than for their counterparts. So, the proposed method can be used for designing LUT-based circuits of very complex Moore FSMs.