A Wide Load Range Buck Converter with Dual-Mode Zero-Current Detection Using ZCD-N Acquisition and ZCD-F Tracking

Abstract

This paper presents an adaptive on-time (AOT) buck converter with a dual-mode zero-current detection (DM-ZCD) scheme for high efficiency over a wide load range. NMOS-switch-based ZCD (ZCD-N) determines whether a transition to discontinuous conduction mode (DCM) is required without periodically activating the freewheeling switch during continuous conduction mode (CCM), and rapidly detects the vicinity of the zero-current crossing (ZCC) during the initial transition from CCM to DCM. The ZCD scheme is then transferred to freewheeling switch-based ZCD (ZCD-F) for accurate ZCC tracking and suppression of switching node ringing in steady-state DCM. During the DCM-to-CCM transition, the absence of a ZCD-F event automatically re-enables ZCD-N circuit. The AOT controller provides near-constant frequency operation in CCM and load-dependent frequency operation in DCM. Dynamic biasing and a subthreshold-biased differential stage reduce control-circuit power consumption and short-circuit current in the comparator output buffer, respectively. Designed in a 0.18-μm CMOS process, the converter operates from a 1.8 V input with a 0.8–1.5 V output and a 10 μA to 700 mA load range. Post-layout simulations predict 98.9% peak efficiency at $V_{OUT}$ = 1.5 V and $I_{LOAD}$ = 10 mA. At a 0.9 V output, peak efficiency is 97.1% and efficiency remains above 90% from 30 μA to 300 mA. The proposed event-based handoff between ZCD schemes enables efficient operation across a wide load range without explicit load current sensing.

1. Introduction

The growing use of data-rich sensors in IoT nodes has intensified the demand for energy-efficient near-sensor processing [1]. Edge computing SoC such as parallel ultra-low-power (PULP) SoC, supports these workloads using near-threshold and parallel processing architectures [2,3,4]. Their load current can vary from several tens of microamperes in deep sleep operation to several hundred milliamperes during computation-intensive operation, requiring a power management buck converter to maintain high efficiency in this wide load range. Under light load conditions, a low switching frequency is required to reduce switching losses, whereas a constant switching frequency is preferred under heavy load conditions to facilitate noise filtering. Since these requirements are inherently achieved by conventional PFM and PWM, respectively, adaptive on-time (AOT) PFM control is attractive because it provides load-dependent switching-frequency operation in light load (DCM) and approximately constant-frequency operation in heavy load (CCM) without an additional selection circuit for the modulation method [5,6,7].

The zero-current detection (ZCD) circuit turns off the low-side NMOS switch ($M_L$) when the inductor current ($I_L$) approaches zero under light load conditions, preventing reverse current and inducing DCM. A conventional NMOS switch-based ZCD, referred to as ZCD-N, directly detects the polarity change of the switching-node voltage ($V_{SW}$), providing rapid detection [5,6,7,8,9]. However, its detection accuracy is limited by the small on-resistance ($R_{on}$) of $M_L$ and the small inductor current near the zero-current crossing (ZCC), defined as the instant at which $I_L$ becomes zero. Comparator nonidealities and PVT variations further limit accuracy, and $V_{SW}$ ringing after $M_L$ is turned off degrades the effectiveness of the calibration schemes adopted in [10,11,12,13,14].

A freewheeling switch-based ZCD, referred to as ZCD-F, senses the voltage across the freewheeling switch ($M_F$) after $M_L$ is turned off [15,16]. The larger $R_{on}$ of $M_F$ increases the accuracy of detection, while $M_F$ prevents the switching node from floating and suppresses $V_{SW}$ ringing. However, ZCD-F relies on iterative tracking of the ZCC and may require several switching cycles to converge after a change in the ZCC. In addition, conventional ZCD-F periodically turns on $M_F$ in CCM to determine whether the converter should enter DCM, thereby reducing CCM efficiency, unlike ZCD-N.

To combine these complementary characteristics, this work proposes a dual-mode-ZCD (DM-ZCD) scheme with an event-based handoff between acquisition and tracking. During CCM and the initial CCM-to-DCM transition, ZCD-N rapidly acquires the vicinity of the ZCC without turning on $M_F$. Control is then automatically transferred to the ZCD-F, which is based on an analog self-tracking circuit (ASTC), for accurate ZCD in steady-state DCM. During a DCM-to-CCM transition, the absence of a ZCD-F event between consecutive AOT pulses identifies CCM entry, re-enables ZCD-N, and disables ZCD-F by preventing $M_F$ activation. This sequence coordinates the ZCD-N and ZCD-F schemes without the need for direct sensing of the load current.

The main contributions of this work are threefold: first, the proposed handoff separates rapid ZCD-N acquisition from accurate ZCD-F tracking; second, the mode decision circuit and tracking node adjustment in the ASTC support handoff in the ZCD scheme and avoid periodic $M_F$ activation in CCM; third, dynamic biasing and a subthreshold-biased differential output stage reduce control-circuit power consumption and suppress short-circuit current in the following digital buffer. The ASTC and coarse_en generator (CEG) in ZCD-F are adopted from [16], and the AOT control concept and minimum off-time generator are adopted from [7]. For integration with the proposed mode decision circuit, the digital logic of the ASTC and CEG is modified to support handoff between ZCD-N and ZCD-F. In addition, a set-dominant SR latch is employed in the AOT controller, eliminating the need for an additional start-up circuit for the AOT controller. The contribution of this work lies in the handoff between the two ZCD schemes, the mode decision and tracking node adjustment circuits, and the integration of low-power techniques. Designed in a 0.18-μm CMOS process, the converter achieves a post-layout simulated peak efficiency of 98.9%. At $V_{OUT}$ = 0.9 V. The peak efficiency is 97.1%, and efficiency remains above 90% from 30 μA to 300 mA.

The remainder of this paper is organized as follows: Section 2 reviews the operating principles and tradeoffs of ZCD-N and ZCD-F as well as the importance of accurate ZCD techniques; Section 3 presents the proposed converter architecture, DM-ZCD handoff sequence, and AOT-PFM operation; Section 4 describes the circuit implementation of the key blocks; Section 5 presents the post-layout simulation results; and Section 6 concludes the paper.

2. Overview and Operating Principles of ZCD Schemes

Accurate ZCD is essential for minimizing power loss. As illustrated in Figure 1, late turn-off of $M_L$ causes reverse current, which discharges the output capacitor and subsequently flows through the body diode of $M_H$, resulting in additional power loss. In contrast, early turn-off causes forward current to flow through the body diode of $M_L$, resulting in diode conduction loss.

Figure 1. Mechanism of efficiency degradation due to early or late turn-off of $M_L$ with respect to the ZCC.

Figure 2 shows the schematic and operating waveforms of ZCD-N. ZCD-N detects the ZCC by directly comparing $V_{SW}$ with ground, and turns off $M_L$ when $V_{SW}$ crosses 0 V. Although this approach enables immediate ZCC detection, its accuracy is limited by comparator non-idealities, propagation delay, PVT variations, and the small $R_{\mathrm{on}}$ of $M_L$. Adaptive calibration techniques can compensate for these limitations by observing $V_{SW}$ after $M_L$ is turned off [10,11,12,13,14]. However, LC oscillations at the switching node can introduce detection errors and degrade calibration accuracy.

Figure 2. (a) Schematic and (b) operating waveforms of ZCD-N.

Figure 3 shows the schematic and operating waveforms of ZCD-F. Unlike ZCD-N, which directly detects the ZCC, ZCD-F adaptively tracks the ZCC by evaluating the polarity of the inductor current after $M_L$ is turned off. Specifically, $M_F$ is turned on immediately after $M_L$ is turned off, forming a current path through $M_F$. If $M_L$ is turned off later than the ZCC, reverse current causes $V_{SW}$ to become higher than $V_{OUT}$ and the ZCD output becomes LOW. Conversely, if $M_L$ is turned off earlier than the ZCC, forward current causes $V_{SW}$ to become lower than $V_{OUT}$ and the ZCD output becomes HIGH. Based on this information, ZCD-F adaptively adjusts the turn-off timing of $M_L$ toward the ZCC.

Figure 3. (a) Schematic and (b) operating waveforms of ZCD-F.

Since the $R_{\mathrm{on}}$ of $M_F$ is considerably larger than that of $M_L$, ZCD-F provides higher detection accuracy than ZCD-N. In addition, $M_F$ prevents the switching node from floating after $M_L$ is turned off, thereby suppressing switching-node oscillations. However, the adaptive tracking operation of ZCD-F requires multiple switching cycles to converge to the ZCC after a ZCC transition, resulting in lower conversion efficiency during the initial tracking period. Furthermore, $M_F$ must be periodically activated even under CCM to determine whether the converter should transition to DCM, resulting in additional CCM power loss.

3. Proposed Structure

The overall architecture integrating the DM-ZCD and AOT-PFM schemes is shown in Figure 4, while the architectures of the operation mode decider and ZCD-F are shown in Figure 5a,b, respectively.

Figure 4. The overall architecture integrating the DM-ZCD and AOT-PFM schemes.

Figure 5. The architectures of (a) the operation mode decider and (b) ZCD-F.

3.1. ZCD-F Operation Based on the ASTC and CEG

Figure 6a shows the detailed architectures of the ASTC and the CEG embedded in the ZCD-F block, whereas Figure 6b illustrates the operating waveforms of the converter employing the ASTC-based ZCD-F scheme.

Figure 6. (a) Detailed architectures of the ASTC and the CEG. (b) Operating waveforms of the converter employing the ASTC-based ZCD-F scheme.

The ASTC generates the $ZC{D}_F$ signal when $V_{RAMP}$ (which increases with a constant slope while $M_L$ is turned on) intersects with the tracking node $V_{ZERO}$. Since the comparator in the ASTC only needs to be activated while $V_{RAMP}$ is being generated, $GD\_L$ is employed as its enable signal. The $ZC{D}_F$ signal serves to pull $S{W}_F$ LOW, thereby turning off $M_L$ and turning on $M_F$. Subsequently, as described in Section 2, the current loop formed by $M_F$ establishes the relative magnitudes of $V_{SW}$ and $V_{OUT}$. Meanwhile, the $S{W}_{F\_Pulse}$ signal is generated in response to the falling edge of $S{W}_F$. The $S{W}_{F\_Pulse}$ signal is sequentially applied to the MF comparator and its latch, the CEG, and the ASTC through intentionally introduced delays. The MF comparator compares the voltages across $M_F$.

If $M_L$ is turned off later than the ZCC, $V_{SW}$ becomes higher than $V_{OUT}$, as illustrated in Figure 6b. Upon activation by the $S{W}_{F\_Pulse}$ signal, the MF comparator detects this condition, causing the $CM{P}_{MF}$ output to become LOW. If the converter controlled by ZCD-F is in the steady-state, the discharging fine current source ($I_{S\_F}$) in the ASTC is subsequently activated for the duration (${\tau }_1$) of the $S{W}_{F\_Pulse}$, causing $V_{ZERO}$ to decrease by a certain amount. Consequently, $V_{RAMP}$ intersects with $V_{ZERO}$ earlier than before, resulting in an earlier turn-off of $M_L$. Conversely, if $M_L$ is turned off earlier than the ZCC and the $CM{P}_{MF}$ becomes HIGH, the opposite operation is performed. In this manner, the ASTC technique adaptively adjusts the turn-off timing of $M_L$, thereby tracking ZCC.

In the steady state, the ZCC remains constant; consequently, $V_{ZERO}$ repeatedly increases and decreases around its target value. However, when an unexpected disturbance such as noise or leakage occurs, $V_{ZERO}$ may deviate significantly from its target value, causing the $CM{P}_{MF}$ to remain unchanged for several consecutive switching cycles. For example, if $V_{ZERO}$ is significantly increased by noise, the $CM{P}_{MF}$ remains LOW for several consecutive cycles until $V_{ZERO}$ returns to its target value. Under these conditions, relying solely on $I_{S\_F}$ causes $V_{ZERO}$ to decrease slowly, resulting in a slow recovery. Therefore, a CEG and a coarse current source ($I_{S\_C}$) are introduced.

If the $CM{P}_{MF}$ changes, then the output of the XOR gate in the CEG becomes HIGH. In contrast, when the $CM{P}_{MF}$ remains unchanged, the XOR gate output remains LOW. While the XOR gate output remains LOW, the 3-bit counter is not reset and continues counting switching cycles. Consequently, after eight consecutive switching cycles without a change in the $CM{P}_{MF}$, the output of the 3-bit counter becomes HIGH, indicating that $V_{ZERO}$ has deviated significantly from its target value. The output of the 3-bit counter is then used as the clock signal for a D flip-flop (DFF), causing $Coarse\_en$ to transition HIGH. Subsequently, while $Coarse\_en$ remains HIGH, $I_{S\_C}$ (which provides a larger current than $I_{S\_F}$) is activated during ${\tau }_1$. As a result, $V_{ZERO}$ is restored more rapidly. Once $V_{ZERO}$ returns to its target value, the XOR gate output becomes HIGH, resetting corresponding circuits and driving $Coarse\_en$ LOW.

Since the CEG determines whether to activate $I_{S\_C}$ based on the transition of the $CM{P}_{MF}$, the $S{W}_{F\_Pulse}$ must be applied to the CEG after the MF comparator updates the $CM{P}_{MF}$ state and before the ASTC updates $V_{ZERO}$, as described previously. In addition to the operation described above, $Coarse\_en$ can also be forced HIGH by the set signal $CCM\_ENT$ during DCM-to-CCM and CCM-to-DCM transitions. The operation associated with $CCM\_ENT$ will be described in the following subsection.

The tracking resolution of the ZCC in the ASTC is determined by the minimum $\Delta V_{ZERO}$ produced by the fine current source. In this work, the target tracking resolution is set to be 1 ns. Since the proposed converter is controlled by an AOT controller with a nearly constant switching period around 1 μs in CCM, the maximum duration for which $GD\_L$ remains HIGH is always shorter than 1 μs, even without imposing a minimum duty cycle. Therefore, the maximum value of $GD\_L$-controlled $V_{RAMP}$ is equal to $1000\times \Delta V_{ZERO,min}$, since

$${\displaystyle \frac{V_{RAMP,max}}{1\mathsf{\mu }\mathrm{s}}}={\displaystyle \frac{\Delta V_{ZERO,min}}{1\mathrm{ns}}}.$$

(1)

Considering the 1.8 V supply voltage and the voltage range required to ensure stable current output from the current sources, the maximum value of $V_{RAMP}$ is chosen to be 1 V. Consequently, the outputs of the current sources and the values of $C_1$ and $C_2$ in ASTC are determined to satisfy $\Delta V_{ZERO,min}=1\mathrm{mV}$ and a ramp slope of $V_{RAMP}$ equal to $1\mathrm{V}/1\mu \mathrm{s}$. The corresponding design equations are given by

$$\Delta V_{ZERO,min}=1\mathrm{mV}={\displaystyle \frac{{\tau }_1\times I_{S\_F\_out}}{C_2}},$$

(2)

$$\mathrm{Slope}\mathrm{of}{V}_{RAMP}={\displaystyle \frac{1\mathrm{V}}{1\mu \mathrm{s}}}={\displaystyle \frac{I_{RAMP\_out}}{C_1}},$$

(3)

where $I_{S\_F\_out}$ and $I_{RAMP\_out}$ are the output current of the $I_{S\_F}$ and $I_{RAMP}$, respectively. Based on these equations, ${\tau }_1$, $I_{S\_F\_out}$, $I_{RAMP\_out}$, $C_1$, and $C_2$ are chosen as 20 ns, 0.5 μA, 0.5 μA, 0.5 pF, and 10 pF, respectively. Furthermore, the output current of the $I_{S\_C}$ is chosen to be five times larger than that of the $I_{S\_F}$. To summarize, the design parameters are determined sequentially: the target tracking resolution and switching period first determine $\Delta V_{ZERO,min}$, while the voltage range required to ensure stable current output determines the maximum $V_{RAMP}$. The resulting ramp slope and $\Delta V_{ZERO,min}$ are then used to determine the current-source output currents $C_1$, $C_2$, and ${\tau }_1$ using (2) and (3).

The above design is based on a nominal supply voltage of 1.8 V. When the supply voltage changes within a range where the current sources can maintain stable output currents over the selected $V_{RAMP}$ range, the design parameters do not need to be recalculated; otherwise, the $V_{RAMP}$ range should be reconsidered to ensure stable current-source operation and the subsequent design parameters should be recalculated accordingly.

3.2. Operating Principle of the Proposed DM-ZCD

Figure 7a shows the operating waveforms of the overall architecture presented in Figure 4 during a heavy-to-light load transition from 100 mA to 10 mA with a load-current transition time of 10 ns at $V_{OUT}=0.9$ V. During CCM operation, $V_{ZERO}$ remains at $V_{DD}$; therefore, it does not intersect with $V_{RAMP}$, preventing turn-on of $M_F$ and avoiding CCM efficiency degradation.

Figure 7. (a) Operating waveforms during a heavy-to-light load transition from 100 mA to 10 mA with a load-current transition time of 10 ns at $V_{OUT}=0.9$ V and (b) distortion of the vicinity of ZCC.

When the $I_L$ decreases below zero due to a heavy-to-light load transition, ZCD-N turns off $M_L$ by driving $ZC{D}_N$ HIGH, thereby enabling immediate detection of the ZCC and recognizing the need to transition into DCM. Subsequently, the converter operates in DCM under the control of ZCD-N for several periods. Because $V_{RAMP}$ is controlled by the $GD\_L$ signal, the instant at which $GD\_L$ goes LOW, i.e., the vicinity of ZCC, is captured by $V_{RAMP}$ during these periods.

The rising edge of $ZC{D}_N$ causes the DCM detector in the operation mode decider to drive $DCM\_ENT$ HIGH. Upon this high signal, $V_{ZERO}$, which had previously remained at $V_{DD}$, is gradually discharged by $I_{S\_F}$ and $I_{S\_C}$ whenever $GD\_L$ goes HIGH. As $V_{ZERO}$ intersects with $V_{RAMP}$, $ZC{D}_F$ goes HIGH, thereby driving $DCM\_ENT$ LOW and stopping the gradual discharge of $V_{ZERO}$. Through this operation, the DM-ZCD switches the ZCD mechanism from ZCD-N to ZCD-F.

The number of switching cycles required for this handoff depends on the VCR because the amount by which $V_{ZERO}$ is discharged in each switching cycle is determined by the duration for which $GD\_L$ remains HIGH. Since this duration increases as the VCR decreases, the required handoff duration ranges from 10 to 33 switching cycles over the designed output-voltage range, with 10 cycles at $V_{OUT}=0.8$ V and 33 cycles at $V_{OUT}=1.5$ V.

During the transition from ZCD-N to ZCD-F, $V_{ZERO}$ suppresses the peak of $V_{RAMP}$, causing the vicinity of ZCC previously captured by ZCD-N to be distorted. Consequently, ASTC turns off $M_L$ earlier than the ZCC, inducing a large forward current, as illustrated in Figure 7b. In the worst-case condition, the peak of $V_{RAMP}$ is suppressed by approximately 90 mV, resulting in a forward current of up to approximately 22 mA.

To recover rapidly from this distortion, the signal $CCM\_ENT=\mathrm{HIGH}$ preemptively forces both $CM{P}_{MF}$ and $Coarse\_en$ HIGH through the latch and the CEG, respectively. With this forced-coarse mechanism, the converter recovers from the distortion within 14 switching cycles, corresponding to 65.8 μs when $I_{LOAD}=10$ mA. Without the forced-coarse mechanism, the recovery would require approximately 20–21 switching cycles, as $Coarse\_en$ must wait until $V_{ZERO}$ rises consecutively for eight cycles to become HIGH. The implementation of the forced-coarse mechanism using the latch is described in Section 4, Circuit Implementation.

In ZCD-N-controlled DCM, $CCM\_ENT$ must remain HIGH to force $Coarse\_en$ HIGH, enabling the gradual discharge of $V_{ZERO}$ and rapid recovery from distortion. In contrast, in ZCD-F-controlled DCM, $CCM\_ENT$ must be driven LOW to disable the forced HIGH state of $Coarse\_en$, thereby preserving the intended resolution of $V_{ZERO}$. Therefore, the LOW-to-HIGH transition of $ZC{D}_F$ drives $CCM\_ENT$ LOW in addition to $DCM\_ENT$. Furthermore, since the period during which $CCM\_ENT$ remains HIGH exactly corresponds to the period in which ZCD-N operation is required, $CCM\_ENT$ can be used as the enable signal for ZCD-N, thereby avoiding unnecessary power consumption.

The operating waveforms during a light-to-heavy load transition from 10 mA to 100 mA with a load-current transition time of 10 ns at $V_{OUT}=0.9$ V are shown in Figure 8. During ZCD-F-controlled DCM, one $ZC{D}_F$ event is expected between consecutive rising edges of the AOT controller output D, where each rising edge corresponds to the turn-on of $M_H$. If the next rising edge of D occurs without an intervening $ZC{D}_F$ event, this indicates that the converter has entered CCM, and the CCM detector in the operation mode decider drives $CCM\_ENT$ HIGH. Upon $CCM\_ENT$ going HIGH, $V_{ZERO}$ is charged to $V_{DD}$ by $I_{S\_C}$ to prevent $V_{ZERO}$ from intersecting with $V_{RAMP}$, thereby avoiding the turn-on of $M_F$ during CCM. In addition, ZCD-N is re-enabled to monitor whether the inductor current reaches zero. This event-based decision identifies CCM entry without explicit load current sensing.

Figure 8. Operating waveforms during a light-to-heavy load transition from 10 mA to 100 mA with a load-current transition time of 10 ns at $V_{OUT}=0.9$ V.

In summary, the converter operates in CCM ($CCM\_ENT=\mathrm{HIGH}$, $DCM\_ENT=\mathrm{LOW}$), ZCD-N-controlled DCM ($CCM\_ENT=\mathrm{HIGH}$, $DCM\_ENT=\mathrm{HIGH}$), or ZCD-F-controlled DCM ($CCM\_ENT=\mathrm{LOW}$, $DCM\_ENT=\mathrm{LOW}$). To realize these operating modes, $V_{ZERO}$ is appropriately charged or discharged by the digital control logic in the ASTC, as shown in Figure 9. The corresponding logic is summarized in Table 1.

Figure 9. Characteristics of $V_{ZERO}$ (black) and $V_{RAMP}$ (red): (a) CCM, (b) ZCD-N-controlled DCM, (c) ZCD-F-controlled DCM, and (d) DCM-to-CCM transition.

Table 1. Digital control logic for $V_{ZERO}$ in the DM-ZCD.

Input 1						Output 2				Remarks
$\mathit{DCM}\mathbf{\_}\mathit{ENT}$	$\mathit{GD}\mathbf{\_}\mathit{L}$	$\mathit{CCM}\mathbf{\_}\mathit{ENT}$	${\mathit{SW}}_{\mathbf{F}\mathbf{\_}\mathit{Pulse}}$	$\mathit{Coarse}\_\mathit{en}$	${\mathit{CMP}}_{\mathit{MF}}$	C. Chg.	F. Chg.	C. Dischg.	F. Dischg.
H	L	H	L	x	x	X	X	X	X	DCM by ZCD-N Discharge VZERO according to GD_L
H	H	H	L	x	x	X	X	O	O
L	x	H	L	x	x	O	X	X	X	CCM $V_{ZERO}=V_{DD}$
L	x	L	L	x	x	X	X	X	X	DCM by ZCD-F
L	x	L	H	H	L	X	X	O	O
L	x	L	H	H	H	O	O	X	X
L	x	L	H	L	L	X	X	X	O
L	x	L	H	L	H	X	O	X	X

¹ H = HIGH, L = LOW, and x = don’t care. ² C. = coarse, F. = fine, Chg. = charge current source, Dischg. = discharge current source, O = activated, and X = deactivated.

Consequently, the proposed DM-ZCD employs an event-based handoff between rapid ZCD-N acquisition and accurate ZCD-F tracking. Specifically, during CCM or the initial stage of the CCM-to-DCM transition, ZCD-N enables reverse-current detection without turning on $M_F$ and provides rapid detection of the ZCC. Subsequently, in the steady state of the DCM, ZCD-F provides high accuracy in detecting the ZCC while eliminating switching-node oscillations. As a result, the proposed DM-ZCD enables efficient operation over a wide load range covering both CCM and DCM. Furthermore, because the operating mode can be uniquely identified from the states of $CCM\_ENT$ and $DCM\_ENT$, the proposed DM-ZCD also provides the flexibility to incorporate additional functions based on these mode indicator signals.

As an additional observation, Figure 10 shows the waveforms under a back-to-back load step, where the load returns to a heavy load condition during the handoff from ZCD-N to ZCD-F caused by a heavy-to-light load transition. In this case, although the converter has already returned to CCM, both $CCM\_ENT$ and $DCM\_ENT$ remain HIGH while $V_{ZERO}$ is discharging. Subsequently, $V_{ZERO}$ and $V_{RAMP}$ briefly intersect, after which $V_{ZERO}$ is charged back to $V_{DD}$ and the relevant control signals again indicate CCM operation. Although the turn-on of $M_F$ during the brief intersection of $V_{ZERO}$ and $V_{RAMP}$ causes additional power loss, this condition persists for only a few switching cycles, after which all mode-related signals indicate CCM operation. Therefore, the proposed handoff mechanism can robustly recover from back-to-back load transients without remaining in an incorrect operating state.

Figure 10. Waveforms under back-to-back load steps: 100 mA to 10 mA and 10 mA to 100 mA.

3.3. Operating Principle of the AOT-PFM Control

The structure and operating waveforms of the AOT controller during CCM are shown in Figure 11a,b, respectively. The ON time ($T_{ON}$) is determined by the time required for the $V_{R\_AOT}$ generated by the AOT generator to increase to $V_{O\_REF}$. In contrast, the OFF time ($T_{OFF}$) is determined by the time required for the feedback signal ($V_F$), which is in phase with $I_L$, to decrease to $V_{O\_REF}$. Accordingly, the ON time is adaptively determined by the AOT generator based on $V_{O\_REF}$. Since the comparator in the AOT generator only needs to be activated while the ramp signal of $V_{R\_AOT}$ is being generated, i.e., when $GD\_H$ is LOW, $\overline{GD\_H}$ is employed as its enable signal to reduce unnecessary power consumption.

Figure 11. (a) Structure and (b) operating waveforms of the AOT controller.

The slope of $V_{R\_AOT}$ generated by the resistor and capacitor in the AOT generator is given by $V_{IN}/(R·C)$. In addition, as shown in Figure 4, the DC level of $V_F$ is set to $V_{OUT}/2$ by the voltage divider formed by $R_F$ in the feedback filter. Therefore, the reference voltage satisfies $V_{O\_REF}=V_{OUT}/2$. Accordingly, the $f_{SW}$ in CCM can be derived as

$$T_{ON}={\displaystyle \frac{V_{O\_REF}}{V_{IN}/(R·C)}}={\displaystyle \frac{R·C}{2}}\times {\displaystyle \frac{V_{OUT}}{V_{IN}}}={\displaystyle \frac{R·C}{2}}\times {\displaystyle \frac{T_{ON}}{T_{SW,CCM}}},$$

(4)

$$f_{SW,CCM}={\displaystyle \frac{1}{T_{SW,CCM}}}={\displaystyle \frac{2}{R·C}}.$$

(5)

Since the target $f_{SW}$ in CCM determined by the AOT controller is 1 MHz, R and C in the AOT generator are chosen as $1\mathrm{M}\Omega$ and $2\mathrm{pF}$, respectively. As a result, the $f_{SW}$ in CCM is determined solely by the values of R and C without requiring an additional clock signal. Accordingly, the converter operates similarly to PWM mode with a nearly constant $f_{SW}$ of approximately 1 MHz in CCM while operating in PFM mode with a load-dependent $f_{SW}$ in DCM, without the need for an additional modulation method selection circuit. The relationship between $T_{SW}$ in DCM and the load current can be expressed as follows:

$$T_{SW,DCM}=T_{SW,CCM}+{\displaystyle \frac{C_{OUT}·\Delta V}{I_{LOAD}}}$$

(6)

where $\Delta V$ denotes the difference between $V_{OUT}$ immediately after $M_L$ is turned off and the target $V_{OUT}$. As indicated by (6), $T_{SW,DCM}$ increases as the load current decreases, resulting in a lower switching frequency at light loads. Consequently, the switching loss is reduced at light loads, enabling efficient operation over a wide load range.

The simulated minimum on-time is approximately 36 ns, and is primarily limited by the delay of the comparator employed in the AOT generator; the minimum off-time is approximately 32 ns and is determined by the minimum off-time generator. For the nominal CCM switching period of 1 μs, these values correspond to an achievable duty cycle range of approximately 3.6%–96.8%. In addition, these minimum on- and off-times impose a theoretical upper bound of approximately 14.7 MHz on the switching frequency which is well above the designed CCM switching frequency of approximately 1 MHz.

As shown in Figure 11a, the use of a set-dominant SR latch, which forces the output to the set state under the forbidden input condition, eliminates the need for an additional start-up circuit for the AOT controller, unlike the design in [7]. The operating states of the AOT-PFM converter according to the relative magnitudes of the compared voltages are summarized in Table 2.

Table 2. Operating states of converter employing the proposed AOT controller.

	${\mathit{V}}_{\mathit{R}\_\mathit{AOT}}>{\mathit{V}}_{\mathit{O}\_\mathit{REF}}$ ⇒ OFF = HIGH	${\mathit{V}}_{\mathit{R}\_\mathit{AOT}}<{\mathit{V}}_{\mathit{O}\_\mathit{REF}}$ ⇒ OFF = LOW
${\mathit{V}}_{\mathit{F}}>{\mathit{V}}_{\mathit{O}\_\mathit{REF}}$ ⇒ ON = LOW	$D=$ LOW 1 $V_F\downarrow \mathrm{and}{V}_{R\_AOT}\downarrow$	Hold previous state 2
${\mathit{V}}_{\mathit{F}}<{\mathit{V}}_{\mathit{O}\_\mathit{REF}}$ ⇒ ON = HIGH	$D=$ HIGH 4 $V_F\uparrow \mathrm{and}{V}_{R\_AOT}\uparrow$	$D=$ HIGH 3 $V_F\uparrow \mathrm{and}{V}_{R\_AOT}\uparrow$

¹ State 1, ² State 2, ³ State 3, ⁴ State 4

When the converter enters State 1, the discharge NMOS in the AOT generator immediately discharges $V_{R\_AOT}$ to 0 V, causing the converter to transition to State 2. Subsequently, as $V_F$ continues to decrease, the converter enters State 3. Under normal operation, once State 3 is reached, $V_F$ immediately becomes greater than $V_{O\_REF}$, returning the converter to State 2. Thereafter, as $V_{R\_AOT}$ continues to increase, the converter transitions back to State 1.

However, depending on the initial conditions of the converter, the converter may transition from State 3 to State 4. During the start-up phase, this transition occurs if $V_{R\_AOT}$ exceeds $V_{O\_REF}$ before $V_F$ exceeds $V_{O\_REF}$. In State 4, the set-dominant SR latch forces D to remain HIGH. Consequently, both $V_F$ and $V_{R\_AOT}$ continue to increase until $V_F$ exceeds $V_{O\_REF}$, at which point the condition for State 4 is no longer satisfied and the converter transitions to State 1. The resulting state transitions are illustrated in the state diagram shown in Figure 12. Therefore, regardless of the initial conditions under which the converter starts operating, the converter always converges to the normal operation.

Figure 12. State diagram of converter employing the proposed AOT controller.

4. Circuit Implementation

4.1. Operation Mode Decider and ZCD-N

The detailed implementation of the operation mode decider and ZCD-N is shown in Figure 13a. These circuits generate the operation-mode control signals ($CCM\_ENT$ and $DCM\_ENT$) as well as the signals used to turn off $M_L$ ($ZC{D}_N$ and $S{W}_F$).

Figure 13. (a) Detailed implementation of the operation mode decider and the ZCD-N, (b) operating waveforms of the ZCD-N and the DCM detector, and (c) operating waveforms of the SWF generator.

First, the operating waveforms of the ZCD-N and the DCM detector are shown in Figure 13b. The operating concept of the ZCD-N and the schematic of its internal comparator are adopted from [7]. The comparator in the ZCD-N compares $V_{SW}$ with ground and outputs a HIGH when $V_{SW}$ becomes positive. This output is used as the clock signal for a DFF, causing $ZC{D}_N$ to be driven to $V_{DD}$ (HIGH). The comparator is enabled only when both $CCM\_ENT$ and $GD\_L$ are HIGH. Therefore, once $ZC{D}_N$ becomes HIGH and turns off $M_L$, the comparator is immediately disabled, forcing its output LOW. In this manner, the comparator is activated only when required, thereby reducing unnecessary power consumption. Subsequently, at the beginning of the next switching cycle, $ZC{D}_N$ is reset to LOW by the LOW of $GD\_H$. The DCM detector following the ZCD-N detects the rising edge of $ZC{D}_N$ and drives $DCM\_ENT$ to $V_{DD}$ (HIGH). Afterward, when high $ZC{D}_F$ is detected, $DCM\_ENT$ becomes LOW to switch the ZCD scheme.

Next, the operating waveforms of the SWF Generator are illustrated in Figure 13c. Here, D and $ZC{D}_F$ serve as the set and reset signals, respectively. When D becomes HIGH (that is, when $M_H$ is turned on), $S{W}_F$ is driven to HIGH, turning off $M_F$; conversely, when $ZC{D}_F$ becomes HIGH, $S{W}_F$ is driven LOW, thereby turning on $M_F$ and turning off $M_L$. However, if $ZC{D}_F$ turns off $M_L$ at almost the same time that $M_L$ would normally be turned off without ZCD circuit, then the HIGH of D and $ZC{D}_F$ may occur simultaneously, since D is the signal before the gate driver delay. Since this forbidden input condition of the SR latch is reasonably interpreted as CCM operation, a set-dominant SR latch is adopted.

When $S{W}_F$ is driven to LOW, a falling edge detector generates $S{W}_{F\_Pulse}$. $S{W}_{F\_Pulse}$ is generated from the ${\tau }_2$-delayed $S{W}_F$ to compensate for the RC delay caused by the $R_{on}$ of $M_F$ and the parasitic capacitance at the switching node, which slows the rise of $V_{SW}$ toward the vicinity of the $V_{OUT}$ level after $M_L$ is turned off. Consequently, the ${\tau }_2$ delay allows $V_{SW}$ and $V_{OUT}$ to be compared after their voltage relationship is determined solely by the forward or reverse current, ensuring accurate ZCD-F operation.

The CCM detector is implemented by cascading two DFFs using D as the clock signal and $ZC{D}_F$ as the reset signal. During ZCD-N operation, the $ZC{D}_F$ event drives $CCM\_ENT$ LOW, thereby switching the ZCD scheme to ZCD-F. During ZCD-F operation, one $ZC{D}_F$ event is expected between two consecutive rising edges of D, and $CCM\_ENT$ remains LOW; otherwise, $CCM\_ENT$ is driven to $V_{DD}$ (HIGH), switching the operation mode to CCM. As mentioned previously, in order to interpret the simultaneous HIGH of D and $ZC{D}_F$ as CCM operation, an AND gate combines $\overline{D}$ and $ZC{D}_F$.

4.2. Latch of MF Comparator

In Section 4.1, the simultaneous HIGH of $ZC{D}_F$ and D was addressed. A similar consideration must also be applied to the latch of the MF comparator (hereafter referred to as the MF latch). In addition, to mitigate the distortion shown in Figure 7b, the MF latch is required to output $CM{P}_{MF}=\mathrm{HIGH}$ when $CCM\_ENT$ is HIGH. Accordingly, the MF latch is designed as shown in Figure 14a.

Figure 14. (a) Detailed implementation of the MF latch and (b) the case where $S{W}_{F\_Pulse}$ and $\overline{GD\_H}$ become HIGH simultaneously.

Since $S{W}_{F\_Pulse}$ is generated with a delay of ${\tau }_2$ from the falling edge of $ZC{D}_F$, the HIGH of $S{W}_{F\_Pulse}$ and $\overline{GD\_H}$ may still occur simultaneously despite the solution introduced in Section 4.1. As illustrated in Figure 14b, under this condition, the MF comparator performs the voltage comparison only after $V_{SW}$ has risen to $V_{IN}$ due to the turn-on of $M_H$. Consequently, the MF comparator outputs $CM{P}_{MF}=\mathrm{LOW}$ even though the converter should be operating in CCM, causing $V_{ZERO}$ to decrease and creating a condition in which $M_F$ can be turned on. As shown in Figure 14a the MF latch is designed to prevent this behavior, such that whenever $S{W}_{F\_Pulse}$ and $\overline{GD\_H}$ become HIGH simultaneously, $CM{P}_{MF}$ is driven to HIGH regardless of all other input signals. Likewise, when $CCM\_ENT$ is HIGH, the MF latch forces $CM{P}_{MF}$ HIGH regardless of the other inputs in order to mitigate the distortion shown in Figure 7b.

Even after incorporating the above functions, the circuit must still operate as a latch under normal comparison conditions. The MF comparator, implemented as a StrongARM Latch [17], outputs $(\mathrm{HIGH},\mathrm{HIGH})$ in its idle state. Furthermore, a NAND gate functions as an inverter when its other input remains HIGH. Taking these characteristics into account, $V_{OUT}$ and $V_{SW}$ are applied to the positive and negative inputs of the MF comparator, $V_{in\_p}$ and $V_{in\_n}$, respectively. Its positive and negative outputs, $V_{out\_p}$ and $V_{out\_n}$, respectively, are then connected to the MF latch, as shown in Figure 14a. Consequently, as shown in Table 3, the proposed MF latch performs the intended logic.

Table 3. Operation of the proposed MF latch under normal comparison conditions.

Condition of MF Comparator	${\mathit{V}}_{\mathit{out}\_\mathit{p}}$	${\mathit{V}}_{\mathit{out}\_\mathit{n}}$	R	S	${\mathit{CMP}}_{\mathit{MF}}$
Compare in forward current ($V_{OUT}>V_{SW}$)	H	L	L	H	H
Compare in reverse current ($V_{OUT}<V_{SW}$)	L	H	H	L	L
Idle state	H	H	L	L	Hold

$V_{in\_p}=V_{OUT}$ and $V_{in\_n}=V_{SW}$.

4.3. Comparator

To identify the dominant power-consuming circuits, the power consumption of each block and circuit in the proposed converter must first be examined. Although the ASTC includes several current sources, their output currents are small and they are activated only temporarily. Consequently, as the load current decreases and the switching period becomes longer under PFM control, their contribution to the total power consumption is progressively reduced. The MF comparator is a dynamic comparator that consumes only dynamic power. The comparators employed in the ASTC and the AOT generator are activated only when $M_L$ and $M_H$ are turned on, respectively. Therefore, the power consumption of these three comparators also becomes less significant as the load current decreases. The comparator used in the ZCD-N is not activated during DCM operation controlled by the ZCD-F, and so consumes no power under steady-state DCM operation.

In contrast, the static comparator that compares $V_F$ with $V_{O\_REF}$ in the AOT controller (hereafter referred to as the AOT comparator) must remain continuously active; therefore, minimizing the power consumption of this comparator is of particular importance. Reducing the bias current of the comparator is essential for lowering its power consumption. However, another important issue must also be considered: if the two input voltages of the comparator are very close, the output voltage may remain at an intermediate level for a long time, allowing short-circuit current to flow in the subsequent digital buffer, thereby increasing power consumption. This issue is particularly critical for the AOT comparator, since the difference between $V_F$ and $V_{O\_REF}$ is typically within 20 mV.

A straightforward solution is to employ a differential amplifier as the second stage of the comparator. However, the static bias current required by a conventional differential amplifier can become a significant power overhead under light load conditions. To address this issue, the proposed design adopts a differential amplifier with input transistors that operate in the subthreshold region (hereafter referred to as the diff amp), as shown in Figure 15a.

Figure 15. (a) Schematic of the proposed AOT comparator and (b) its operating waveforms at $V_{OUT}=0.9$ V and $I_{LOAD}$ = 10 mA (DCM).

The first stage latch serves two purposes: it enlarges the input voltage difference of the second stage relative to that of the latch, and it ensures that $M_{sp}$ and $M_{sn}$ operate in the subthreshold-region during DCM. A dynamic bias scheme is adopted for the latch such that the left bias current is enabled only during CCM. Consequently, the bias current of latch is 2 μA in CCM and 0.3 μA in DCM.

Next, consider the second stage, namely, the diff amp. Both $M_{sp}$ and $M_{sn}$ operate in the subthreshold region, while the drain voltage of $M_1$ is pulled close to 0 V by the $V_{GS}$ of $M_{sp}$ and $M_{sn}$, forcing $M_1$ to operate in the deep triode region. As a result, the diff amp consumes only several tens of nanoamperes when the input voltage difference is relatively large and several hundreds of nanoamperes when the two inputs are close to each other. Since this circuit functions as a comparator, its output common-mode voltage should be approximately $V_{DD}/2$. Therefore, $M_2$ and $M_3$ are designed with long channel lengths.

As a result of these design techniques, the operation of the AOT comparator is illustrated in Figure 15b. The diff amp ensures that its output does not exceed 0.5 V unless the voltage difference between two inputs of the AOT comparator is within 0.5 mV, thereby suppressing short-circuit current in the subsequent buffer. In addition, the first inverter in the digital buffer is implemented with a long channel length to reduce the short-circuit current. Consequently, the current consumption of the AOT comparator exhibits a brief peak when the two input voltages become nearly identical, then returns to the bias-current level discussed above. Owing to the characteristics of PFM control, the interval between these current peaks increases as the load current decreases, resulting in a lower average current consumption of the AOT comparator.

The comparators employed in the ASTC and the AOT generator are designed based on the same principle, as shown in Figure 16. However, because these comparators are activated only when an enable signal becomes HIGH, several modifications are introduced. In the first stage, the dynamic bias current range of 0.3–2 μA is changed to 0–2 μA. In the second stage, an additional NMOS transistor controlled by the enable signal is inserted below $M_1$ to provide the enable function. Furthermore, the long channel inverter is replaced with a conventional inverter.

Figure 16. Schematic of the comparators employed in the ASTC and AOT generator, with the modified components highlighted in blue.

Under the same comparison conditions with a conventional comparator having the same bias current, both comparators exhibit a delay of approximately 24 ns, indicating negligible difference in delay. In contrast, the peak short-circuit current is reduced from 94.1 μA for the conventional comparator to 12.4 μA for the proposed comparator, demonstrating a significant suppression in the short-circuit current.

5. Simulation Results

The proposed DC–DC buck converter employing the DM-ZCD, referred to as the DM-ZCD converter, was designed in a 0.18-μm CMOS process. Figure 17a shows the layout of the DM-ZCD converter, which occupies an active area of 0.34 mm², while Figure 17b shows its power breakdown at $V_{OUT}=0.9$ V and $I_{LOAD}=100$μA. All post-layout simulation results were obtained using Cadence Virtuoso with the Spectre simulator. An off-chip 4.7 μH inductor with a DCR of 216 mΩ, an off-chip 4.7 μF output capacitor with an ESR of 6 mΩ and an ESL of 258 pH, and wire-bonding parasitics modeled as 50 mΩ/mm resistance and 1 nH/mm inductance were included in the simulations.

Figure 17. (a) Chip layout and (b) power breakdown at $V_{OUT}=0.9$ V and $I_{LOAD}=100$μA.

Although the post-layout simulations include the modeled parasitic elements, additional losses may occur in actual silicon due to thermal effects, unmodeled PCB traces, and other non-idealities in the measurement environment. Therefore, the measured performance of the proposed converter may be slightly lower than the post-layout simulation results.

Since ZCD-N is inherently susceptible to non-ideal factors such as comparator offset and PVT variations, whereas ZCD-F is expected to be significantly less sensitive to these variations, their robustness is first evaluated. Figure 18a shows the statistical distribution of the ZCD-N comparator offset obtained from 200 Monte Carlo simulations. While the nominal ZCD-N operation results in an average reverse current of approximately 7 mA, the comparator offset can result in a reverse current of up to 41 mA or a forward current of up to 27 mA within the $2\sigma$ range. Therefore, when the ZCC detection error is quantified in terms of the reverse-current magnitude, the maximum error is increased by approximately 5.86 times compared with the nominal case.

Figure 18. Monte Carlo and process temperature variation results: 200-run Monte Carlo simulations of (a) comparator offset, (b) fine current-source output, and (c) pulse width; (d) maximum reverse current of ZCD-N and ZCD-F under process and temperature variations.

In contrast, ZCD-F compares the voltage across $M_F$, for which the $R_{\mathrm{on}}$ is considerably larger than that of the $M_L$ used for ZCD-N; as such, it provides lower sensitivity to comparator offset. Nevertheless, according to (2), mismatch in the current-source output ($I_{S\_F\_out}$) and pulse width (${\tau }_1$) can affect the tracking resolution of ZCD-F. The corresponding Monte Carlo simulation results are shown in Figure 18b and Figure 18c, respectively. Since the tracking resolution is determined by the product of these two parameters, the maximum tracking resolution within the $2\sigma$ range is approximately 1.2 times its nominal value. These results demonstrate that ZCD-F is significantly less sensitive to mismatch than ZCD-N.

As reported in [10], reverse current results in greater power loss than forward current, as it introduces not only diode conduction loss but also capacitor discharging loss. Moreover, the power loss caused by the reverse current is proportional to the cube of the ZCD timing error. Since the magnitude of the reverse current is linearly proportional to the ZCD timing error under the same operating condition, the increase in reverse current can be directly related to the increase in loss induced by the ZCD error. Accordingly, within the $2\sigma$ range, the maximum ZCD error-induced loss can increase by approximately 201 times for ZCD-N, whereas the corresponding increase for ZCD-F is limited to approximately 1.73 times.

The robustness of the two ZCD schemes against process and temperature variations is further evaluated in Figure 18d, which compares their maximum reverse-current magnitudes across the considered process corners and temperatures. Across these conditions, the maximum reverse-current magnitude varies over a range of 1.94 mA for ZCD-N, compared with only 0.92 mA for ZCD-F. These results further demonstrate that ZCD-F is considerably less sensitive to process and temperature variations than ZCD-N.

Figure 19 shows the switching period and the $V_{OUT}$ ripple under steady state for different operating conditions. As shown in Figure 19a, the switching period remains nearly constant even when $V_{OUT}$ varies in CCM ($I_{LOAD}=100$ mA). Figure 19b shows that the switching period increases significantly in DCM ($I_{LOAD}=100$μA) compared with that in CCM, implying a substantial reduction in switching loss. These results demonstrate the effectiveness of the proposed AOT-PFM control scheme.

Figure 19. Switching period and $V_{OUT}$ ripple (a) at $I_{LOAD}=100$ mA and (b) at $V_{OUT}=0.9$ V and $I_{LOAD}=100$μA.

Figure 20a shows the waveforms of $V_{OUT}$ and $V_{SW}$ during a load transition between 100 mA and 100 μA with a load-current transition time of 10 ns at $V_{OUT}=1.2$ V. Compared with the transient condition used in Section 3, this simulation employs a larger load step and a different output voltage. As observed from the $V_{OUT}$ waveform, the $V_{OUT}$ remains properly regulated even under this large load step. The $V_{SW}$ waveform after the heavy-to-light load transition clearly shows the handoff of the ZCD scheme from ZCD-N to ZCD-F.

Figure 20. Load transient waveforms between 100 mA and 100 μA at $V_{OUT}=1.2$ V with load-current transition times of (a) 10 ns and (b) 5 μs.

To further evaluate the handoff behavior under a slower load transition, Figure 20b shows the transient response under the same load step and output voltage conditions, but with the load-current transition time increased from 10 ns to 5 μs. Compared with the 10 ns case, the slower rise of $V_{ZERO}$ increases the recovery time following the light-to-heavy load transition to approximately 30.8 μs. Nevertheless, $V_{OUT}$ is eventually properly regulated, while the response to the heavy-to-light load transition remains consistent with that observed in the 10 ns case. These results demonstrate that the proposed handoff mechanism maintains proper operation even under a significantly slower load transition.

Figure 21 shows the simulated converter efficiency as $V_{OUT}$ and $I_{LOAD}$ vary. The DM-ZCD converter achieves a peak efficiency of 98.9% at a voltage conversion ratio (VCR) of 0.83, corresponding to $V_{OUT}=1.5$ V and $I_{LOAD}=10$ mA. The edge computing SoC application requires the converter to provide a sub-1 V output voltage. Under this operating condition, corresponding to $V_{OUT}=0.9$ V ($VCR=0.5$), a peak efficiency of 97.1% is achieved while maintaining efficiency above 90% over a wide load range from 30 μA to 300 mA.

Figure 21. Simulated converter efficiency versus $I_{LOAD}$.

To further quantify the individual contributions of the circuit-level techniques to the converter efficiency, additional ablation simulations were performed. First, the effect of dynamic biasing was evaluated by continuously maintaining the bias currents of all comparators at 2 μA. At $V_{OUT}=1.2$ V and $I_{LOAD}=100$μA, the conversion efficiency decreases from 96.40% with dynamic biasing to 92.18% under the fixed-bias condition, corresponding to a degradation of 4.22 percentage points. This result demonstrates that dynamic biasing plays an important role in maintaining high efficiency under light load conditions.

In addition, the contribution of the proposed subthreshold-biased comparator was evaluated by replacing the AOT comparator with a conventional comparator under the same bias condition. At $V_{OUT}=0.9$ V and $I_{LOAD}=10$ mA, the conversion efficiency decreases from 97.38% to 96.39%, while the power consumption of the AOT controller increases from 2.052 μW to 29.862 μW. These results quantitatively demonstrate the contribution of the proposed comparator topology to reducing the control-circuit power consumption and improving the overall conversion efficiency.

Based on these simulation results, Table 4 compares the performance of the proposed DM-ZCD converter with that of previously reported buck converters employing DCM operation under light load conditions, including [16], which served as the basis for the proposed improvements. Since the results of the proposed converter are based on post-layout simulations, whereas all previous studies report physical measurement results, the actual measured efficiency of the proposed converter may be slightly lower than the reported simulation results.

Table 4. Performance comparison of buck converters incorporating DCM operation for light load.

Item	TCAS-II’19 [16]	TCAS-I’20 [8]	TPEL’21 [6]	TCAS-I’22 [7]	TCAS-I’25 [10]	JSSC’25 [5]	This Work *
Technology (nm)	180	180	180	180	55	180	180
Die Area (mm2)	0.19	1.10	1.09	0.55	0.53	0.73	0.34
$V_{IN}$ (V)	1.8	2–5	2.1–5.5	2.7–4.7	2.5–4.2	2.4–5.5	1.8
$V_{OUT}$ (V)	1.0–1.5	0.8–3	1.8	1.6	0.8–2.2	1.2–2.5	0.8–1.5
$L/C_{OUT}$ (μH/μF)	4.7/4.7	2.2/4.7	2.2/10	4.7/4.7	6.8/2.2	2.2/10	4.7/4.7
Max. Ripple (mV)	N/A	75	19	50	35	20	12 @ $V_{OUT}=0.9$ V
Support CCM	Yes	Yes	Yes	Yes	No	Yes	Yes
$f_{SW,\mathrm{CCM}}$ (MHz)	1	2.6	1.5	4	N/A	1.4	1
$I_{LOAD}$ Range (mA)	1–300	${10}^{-3}$–50	${10}^{-3}$–300	${10}^{-3}$–100	${10}^{-3}$–300	${10}^{-3}$–1000	${10}^{-2}$–700
Circuit for $I_{LOAD}$ Detection	No	Yes	Yes	Manual	No	No	No
Peak Efficiency (VCR)	94% (0.67)	94.7% (0.83)	95.8% (0.86)	92.1% (0.59)	95.8% (0.69)	97.4% (0.83)	98.9% (0.83)
Efficiency @10 μA (VCR)	N/A	80% (0.50)	84% (0.43)	68% (0.44)	84% (0.52)	90% (0.43)	82% (0.50)
>90% Efficiency Load Range (mA) (VCR)	10–300 (0.67)	0.6–10 (0.50)	0.1–300 (0.43)	None ** (0.44)	None ** (0.52)	0.01–600 (0.43)	0.03–300 (0.50)

* Post-layout simulation results; ** no load-current range with an efficiency above 90% exists at a VCR close to 0.5.

Among the compared converters in Table 4, the DM-ZCD converter achieves the second-widest load current range, with efficiency above 90%; this is surpassed only by JSSC’25 [5]. In addition, the DM-ZCD converter achieves the highest peak efficiency among all compared converters. These results demonstrate that the proposed design techniques, including the DM-ZCD scheme, dynamic biasing, and subthreshold-biased differential output stage, enable the converter to achieve state-of-the-art or near-state-of-the-art efficiency-related performance among converters incorporating DCM operation. Compared with [16], the chip area is increased, as both the ZCD scheme and the modulation method have been modified; however, a significant improvement in efficiency is achieved. In particular, the proposed DM-ZCD converter improves the peak efficiency by 4.9 percentage points compared with [16].

Table 5 shows the additional comparison of the performance between [16] and the DM-ZCD converter. To verify the effectiveness of the proposed design in preventing $M_F$ from turning on in CCM, the CCM efficiency should be compared. Although the load current corresponding to the peak efficiency of [16] is not specified, its efficiency curve indicates that the peak efficiency is achieved at approximately 100 mA in CCM. Therefore, the efficiency of the DM-ZCD converter was also simulated at $VCR=0.67$ and $I_{LOAD}=100$ mA, resulting in a CCM efficiency of 96.7%, which corresponds to an improvement of 2.7 percentage points. These results quantitatively demonstrate the contribution of the proposed DM-ZCD scheme to the conversion efficiency by preventing $M_F$ from periodically turning on in CCM, unlike [16].

Table 5. Comparison of ZCD and CCM performance between [16] and the DM-ZCD converter.

Item	TCAS-II’19 [16]	This Work
tracking resolution	1.3 ns	1 ns
Zero-current self-tracking time (LOAD: 100 mA → 10 mA, $V_{OUT}$ = 1.2 V)	40 μs (40 cycles)	116 μs (25 cycles)
ZCD Power	81 μW	4.4 μW @ 10 mA
CCM Efficiency	94% @ 1.2 V/1.8 V (peak efficiency at approximately 100 mA)	96.7% @ 1.2 V/1.8 V (load current = 100 mA)

The zero-current self-tracking time is longer in the proposed converter due to the longer switching period resulting from the different modulation method. However, this drawback is mitigated by reducing the required number of cycles: ZCD-N captures the vicinity of ZCC and the mode decision circuit allows the ASTC operation to be influenced by ZCD-N, resulting in rapid discharge of $V_{ZERO}$ during handoff. As a result, the proposed converter requires only 25 cycles for zero-current self-tracking, compared with 40 cycles in [16].

In addition, the DM-ZCD converter achieves significantly lower ZCD power. The reduced switching frequency at light loads reduces the activation frequency of the ZCD circuit, including the ASTC, while the use of a 50-nA current reference reduces the bias currents of the current sources in the ZCD circuit. Consequently, the ZCD power is reduced to 4.361 μW at 10 mA, compared with 81 μW in [16].

6. Conclusions

This paper presents an AOT buck converter with a DM-ZCD scheme for high-efficiency operation over a wide load range in edge computing SoC applications. ZCD-N determines whether a transition to DCM is required without periodically activating the $M_F$ during CCM, and rapidly detects the vicinity of the ZCC during the initial CCM-to-DCM transition. The ZCD scheme is then transferred to ZCD-F for accurate ZCC tracking and suppression of switching-node LC oscillations in steady-state DCM. During DCM-to-CCM transition, the absence of a ZCD-F event automatically re-enables the ZCD-N circuit. The AOT controller provides near-constant frequency operation in CCM and load-dependent frequency operation in DCM, reducing switching loss in DCM. Dynamic biasing and a subthreshold-biased differential stage in the AOT comparator reduce control-circuit power consumption and short-circuit current in the comparator output buffer, respectively, while maintaining reliable operation.

Designed in a 0.18-μm CMOS process, the DM-ZCD converter operates from a 1.8 V input with an output voltage range of 0.8-1.5 V and a load current range of 10 μA to 700 mA. Post-layout simulation results predict a peak efficiency of 98.9% at $V_{OUT}=1.5$ V and $I_{LOAD}=10$ mA. At $V_{OUT}=0.9$ V, the converter achieves a peak efficiency of 97.1% and maintains an efficiency above 90% over a load range from 30 μA to 300 mA. The proposed event-based handoff between ZCD schemes enables efficient operation over a wide load range.