Accuracy Optimization and Settling Time Characterization of an N-Bit PWM DAC with a First-Order RC Filter

Abstract

This paper presents a time-domain analysis of an $N$-bit pulse-width-modulated digital-to-analog converter (PWM DAC) employing a first-order passive resistor-capacitor (RC) filter. Exact analytical expressions are derived for the output settling time in both rising and decreasing digital-code transition modes. The worst-case condition is identified, and the settling-time criterion is expressed as a function of the DAC resolution $N$, tolerance $\epsilon$, and normalized filter parameter $k=T/RC$. The derived criterion is compared with a commonly used first-order RC settling approximation. For $N=8$ and $\epsilon =1/4$, the proposed worst-case criterion gives a discrete settling interval of 823 PWM periods, whereas the literature-based estimate gives 355 periods. The analytical results are confirmed by numerical evaluation and LTspice transient simulations and are further supported by experimental measurements obtained using a microcontroller-based PWM generator and a passive RC filter. The results confirm the duty-cycle dependence of the steady-state ripple and demonstrate that the proposed criterion provides a conservative design rule for selecting PWM DAC parameters while balancing accuracy, ripple, and settling speed.

1. Introduction

In modern embedded and mixed-signal systems, it is often necessary to convert a digital signal into an analog equivalent, for example for generating reference voltages, driving actuators, forming control signals, or implementing compact sensor-interface circuits. Although dedicated digital-to-analog converters (DACs) provide well-defined static and dynamic performance, many practical systems rely on simpler and more cost-effective solutions such as the pulse-width-modulated digital-to-analog converter (PWM DAC). In this approach, a digital PWM signal is applied to a low-pass filter, producing an analog output voltage whose average value is proportional to the duty cycle ($D$).

PWM DACs are attractive because PWM generators are available in nearly all microcontrollers, digital signal controllers, and FPGA devices, while the analog filtering stage can be implemented using inexpensive passive components, typically a resistor ($R$) and a capacitor ($C$). Therefore, the PWM DAC architecture is widely used for generating direct-current (DC) and reference voltages [1,2], converting signals into 4–20 mA current-loop outputs for industrial transmitters [3,4], biomedical and sensor applications where PWM DACs are used to form control and measurement voltages [5], and compact mixed-signal architectures such as accelerators based on in-memory computing [6]. Recent works and technical reports also confirm the continued relevance of pulse-based DAC structures, including combined pulse-width and pulse-density digital modulators for analog signal generation [7], MCU-based PWM DAC implementations with RC low-pass filtering [8,9], and PWM-plus-filter blocks used in FPGA mixed-signal architectures [10]. In such applications, the PWM DAC provides an attractive compromise between implementation simplicity, low cost, and acceptable analog-output accuracy.

The main design difficulty of a PWM DAC is the trade-off between output ripple and settling time. A stronger low-pass filter reduces the residual ripple at the PWM frequency and its harmonics, but it also slows down the response after a duty-cycle change. Conversely, increasing the filter bandwidth improves the dynamic response but increases the steady-state ripple. Conventional design procedures usually address this trade-off in the frequency domain by selecting the filter cut-off frequency and estimating the attenuation of the PWM spectral components [1,2,11], or by using simplified first-order resistor-capacitor (RC) step-response approximations. Such approaches are useful for preliminary design, but they do not explicitly describe how the output-voltage extrema evolve within each PWM period, nor do they directly provide a conservative settling-time criterion that accounts for the PWM resolution, the digital-code transition, and the admissible ripple margin.

A time-domain formulation is therefore important when the output voltage must be guaranteed to enter and remain inside a prescribed code-dependent interval. In an $N$-bit PWM DAC, the filtered output is not a single static value, but a periodic waveform with a finite ripple envelope around the desired quantized level. Consequently, it is not sufficient to analyze only the average value of the filtered PWM signal. The maximum and minimum values of the output voltage must also be considered, because these extrema determine whether the output remains inside the admissible range associated with a given digital code. This observation motivates the use of safe and forbidden operating zones as a design tool for connecting steady-state ripple, quantization accuracy, and transient settling behavior.

In contrast to architecture- and implementation-oriented studies, the present work develops an explicit analytical framework for the first-order RC PWM DAC. It links the steady-state ripple envelope, the per-code safe and forbidden operating zones, and the worst-case settling time to the PWM resolution $N$ and the admissible tolerance $\epsilon$, yielding closed-form design rules rather than a specific circuit realization.

A detailed time-domain analysis of a PWM DAC with a first-order passive RC filter was previously reported in [12]. In that work, exact expressions were derived for the maximum and minimum output voltages, the average value and ripple in the steady-state condition, and the estimation of the settling time following a change in duty cycle. However, the explicit dependence of the design criterion on the PWM generator resolution $N$, the admissible tolerance $\epsilon$, and the worst-case digital-code transition was not fully developed. In addition, the operating-zone interpretation, which distinguishes between safe and forbidden steady-state regions, was not introduced as a systematic design metric. These aspects are essential when the PWM DAC is used as a quantized analog-output stage whose ripple must remain safely below the decision boundaries of adjacent digital codes, especially under real operating conditions where component tolerances and noise can affect conversion accuracy.

The objective of this paper is to extend the analysis presented in [12] and to provide a comprehensive and experimentally supported framework for the optimization of $N$-bit PWM DAC structures with a first-order passive RC filter. The main contributions of this work are as follows:

• The dependence of the admissible normalized filter parameter $k=T/\tau$, where $T$ is the PWM period and $\tau =RC$ is the filter time constant, on the PWM resolution $N$ and tolerance $\epsilon$ is derived, providing a direct criterion for selecting the RC time constant with respect to the PWM period. Its minimum admissible value, denoted $k_{\min }$, is the smallest $k$ for which the steady-state output of every code remains within the safe operating zone, and is derived in Section 3.2.
• Safe and forbidden operating zones are introduced to define a conservative steady-state accuracy condition based on the maximum and minimum output-voltage extrema, rather than only on the average value.
• Exact time-domain settling-time expressions are derived for both rising and decreasing digital-code transitions, and the corresponding worst-case conditions are identified.
• The proposed worst-case settling-time criterion is compared with the commonly used first-order RC approximation, and the relationship between the simplified literature estimate and the present time-domain framework is clarified.
• The steady-state harmonic content at the filter output is discussed as a frequency-domain consequence of the same PWM DAC model. This provides a complementary interpretation of the residual ripple in terms of attenuated PWM harmonics.
• The analytical results are validated by numerical evaluation, LTspice transient simulations, and experimental measurements obtained using a microcontroller-based PWM generator and a passive first-order RC filter.

In this way, the paper provides a methodological tool for PWM DAC designers, offering clear insight into the trade-off between response speed and conversion accuracy. The scope of this work is intentionally limited to a first-order passive RC filter, which represents the simplest and most economical PWM DAC implementation and enables closed-form analytical expressions with clear design interpretation. Higher-order passive filters, active low-pass filters, ripple-cancelation structures [13], and generalized multi-stage architectures can further improve the ripple-settling trade-off, but they introduce additional states, component sensitivities, and implementation constraints. These extensions are therefore identified as natural directions for future work, while the first-order case analyzed here provides the reference framework and baseline design criterion.

2. Modeling of PWM DAC

The structure of a PWM-based digital-to-analog converter (DAC) consists of two fundamental parts: a digital PWM generator and a low-pass filter. The PWM generator produces a binary periodic signal, while the filter performs signal averaging and converts it into an analog output voltage. A typical block diagram of the PWM DAC is shown in Figure 1.

Figure 1. Block diagram of the PWM DAC, consisting of a digital $N$-bit PWM generator followed by a low-pass filter that averages the switched waveform into the analog output voltage.

In this paper, a first-order passive RC filter is considered for analytical purposes, as shown in Figure 2. This choice enables the derivation of exact analytical expressions and a straightforward interpretation of the system dynamics. More complex filters of higher order, as well as active structures, are beyond the scope of this study and may be the subject of future research.

Figure 2. PWM DAC structure with a first-order RC filter. The PWM signal, defined by its high-level and low-level durations within the period $T$, drives the RC network, while the output voltage charges and discharges during each period and converges toward the steady-state level determined by the duty cycle.

Figure 2 illustrates the realization of a PWM DAC with the PWM signal characterized by the high-level and low-level durations. The signal is applied to the input of a first-order RC filter whose output voltage oscillates due to the capacitor charging and discharging within each period and gradually converges toward its steady-state value. This illustrates the fundamental principle of converting a PWM signal into an analog voltage.

The PWM signal is defined by the following parameters:

• Signal period $T$—the total duration of one PWM cycle.
• High- and low-level signal durations, $T_{\mathrm{H}}$ and $T_{\mathrm{L}}$, where $T=T_{\mathrm{H}}+T_{\mathrm{L}}$.
• Duty cycle $D={\displaystyle \frac{T_{\mathrm{H}}}{T}}$.
• Voltage levels $V_{\mathrm{H}}$ and $V_{\mathrm{L}}$: typically, $V_{\mathrm{L}}=0$ (logical 0) and $V_{\mathrm{H}}=V_{\mathrm{DD}}$ (supply voltage, logical 1).

The PWM generator is typically implemented using an $N$-bit counter; therefore, the duty cycle can take discrete values:

$$D={\displaystyle \frac{d}{2^N}},d ϵ \left\{0, 1,\dots , 2^N-1\right\},$$

(1)

where $N$ denotes the DAC resolution (number of bits), and $d$ represents the digital code.

For a quantitative description of the output-voltage behavior, we rely on the results of a detailed time-domain analysis of a PWM DAC structure with a first-order RC filter presented in [12]. In that study, general expressions were derived for:

• The maximum and minimum output voltages in the $n$-th period:

$$v_{\max ,n}=V_0{e}^{-k(n-1+D)}+V_{\mathrm{H}}{\displaystyle \frac{1-e^{-kD}}{1-e^{-k}}}\left(1-e^{-kn}\right)+V_{\mathrm{L}}{\displaystyle \frac{e^{-kD}-e^{-k}}{1-e^{-k}}}\left(1-e^{-k(n-1)}\right),$$

(2)

$$\begin{gathered} v_{\min ,n}=V_0{e}^{-k(n-1)}+V_{\mathrm{H}}{\displaystyle \frac{e^{-k(1-D)}-e^{-k}}{1-e^{-k}}}\left(1-e^{-k(n-1)}\right) \\ +V_{\mathrm{L}}{\displaystyle \frac{1-e^{-k(1-D)}}{1-e^{-k}}}\left(1-e^{-k(n-1)}\right), \end{gathered}$$

(3)

where $k=T/\tau$.

• The steady-state (stationary) maximum and minimum values ($n\to \infty$, and digital domain transition $D={\displaystyle \frac{d}{2^N}}$):

$$v_{\max ,\infty }={V_{\mathrm{L}}{\displaystyle \frac{e^{-k\frac{d}{2^N}}-e^{-k}}{1-e^{-k}}}+V}_{\mathrm{H}}{\displaystyle \frac{1-e^{-k\frac{d}{2^N}}}{1-e^{-k}}},$$

(4)

$$v_{\min ,\infty }={V_{\mathrm{L}}{\displaystyle \frac{1-e^{-k(1-\frac{d}{2^N})}}{1-e^{-k}}}+V}_{\mathrm{H}}{\displaystyle \frac{e^{-k(1-\frac{d}{2^N})}-e^{-k}}{1-e^{-k}}}.$$

(5)

These expressions are fundamental for defining the safe and forbidden operating zones of the PWM DAC, as well as for the analytical determination of the settling time.

Steady-State Harmonic Interpretation

The main analysis in this paper is performed in the time domain, because the proposed accuracy and settling-time criteria are based on the maximum and minimum values of the filtered PWM waveform. Nevertheless, the same first-order PWM DAC model can also be used to determine the steady-state harmonic components at the output of the RC filter. This provides a frequency-domain interpretation of the residual ripple and is consistent with conventional PWM DAC design approaches based on the attenuation of PWM spectral components [1,2,11].

In the steady state, the filtered output is a periodic waveform with the PWM period $T$. The duty cycle is denoted by $D$, and for the $N$-bit PWM DAC considered in this paper it is given by Equation (1), $D=d/2^N$. The steady-state extrema of this periodic waveform are given by Equations (4) and (5). Therefore, the following frequency-domain interpretation refers to the same steady-state waveform, but it is used only to describe its harmonic content.

The average, or DC, component of the PWM DAC output is:

$$C_0=V_{\mathrm{DC}}=V_{\mathrm{L}}+(V_{\mathrm{H}}-V_{\mathrm{L}})D.$$

(6)

For the ideal unfiltered PWM waveform with voltage levels $V_{\mathrm{L}}$ and $V_{\mathrm{H}}$, the magnitude of the $m$-th complex Fourier coefficient, is:

$$\left|U_m\right|={\displaystyle \frac{(V_{\mathrm{H}}-V_{\mathrm{L}})\left|\sin (\pi mD)\right|}{\pi m}}, m=1, 2, 3, \dots ,$$

(7)

The $m$-th PWM harmonic occurs at the angular frequency ${\omega }_m=m{\omega }_0$, where ${\omega }_0=2\pi /T$ is the fundamental PWM angular frequency. The magnitude of the first-order RC filter transfer function at this harmonic frequency is:

$$\left|H\left(j{\omega }_m\right)\right|={\displaystyle \frac{1}{\sqrt{1+{(2\pi m/k)}^2}}},$$

(8)

where $\tau =RC$ is the filter time constant and $k=T/\tau =T/RC$ is the dimensionless normalized filter parameter. The limiting value $k_{\min }$, derived later from the safe-zone criterion, represents the admissible boundary value of this parameter.

Consequently, the magnitude of the $m$-th complex Fourier coefficient at the RC filter output is:

$$\left|C_m\right|={\displaystyle \frac{(V_{\mathrm{H}}-V_{\mathrm{L}})\left|\sin (\pi mD)\right|}{\pi m\sqrt{1+{(2\pi m/k)}^2}}}, m=1, 2, 3, \dots ,$$

(9)

This expression has a direct physical interpretation. The first factor represents the $m$-th harmonic component of the ideal unfiltered PWM waveform expressed by Equation (7), while the second factor represents the attenuation introduced by the first-order RC filter at the same harmonic frequency expressed by Equation (8). Therefore, in the ideal first-order passive RC model considered in this paper, the steady-state ripple can be interpreted as the residual contribution of attenuated PWM harmonic components at the filter output.

It should be noted that $C_m$ denotes a complex Fourier coefficient. Therefore, the corresponding one-sided sinusoidal amplitude of the $m$-th harmonic is $2\left|C_m\right|$. The peak-to-peak ripple is obtained from the combined time-domain contribution of all harmonic components with their phases, rather than from a simple summation of magnitudes.

This frequency-domain interpretation is included only as a complementary steady-state view. It is not used as the settling-time criterion. In the following sections, the analysis remains based on the output-voltage extrema and the corresponding safe operating zones.

3. Definition of Operating Zones of PWM DAC

This chapter analyzes the operation of the PWM DAC with a first-order RC filter, with the aim of clearly defining the safe, transitional, and forbidden operating zones. The boundaries of these zones are determined based on the analytical expressions for the maximum and minimum output voltages, as well as the quantized transfer function with the quantization step $∆ ={\displaystyle \frac{V_{\mathrm{H}}-V_{\mathrm{L}}}{2^N}}$.

In this way, a precise criterion is established for distinguishing between stable and unstable operating regimes. The results are graphically illustrated through figures that clearly separate the safe and forbidden regions, as well as the transitional zones where the system cannot reach a stable steady-state condition.

3.1. Discretization and Quantization Models

The discrete duty cycle values defined by Equation (1) form the basis for the quantization model of the PWM DAC. Since the PWM period is divided into $2^N$ subcycles, the duty cycle can assume only discrete values. Theoretically, the duty-cycle range is $D\mathsf{ϵ}\left[0, 1\right];$ however, in practical implementations, the extreme values $D=0$ and $D=1$ are not always simultaneously used, and the operational range depends on the selected quantization convention. In this context, two standard uniform quantization conventions, mid-tread and mid-rise, are considered.

Two standard approaches are typically considered:

• Mid-tread model—the operational range is defined as:

$$D\in \left[0, 1-{\displaystyle \frac{1}{2^N}}\right],$$

(10)

which means that the lower extreme $D=0$ is allowed, while the upper extreme $D=1$ is excluded.

As shown in Figure 3, the mid-tread realization illustrates three consecutive PWM periods corresponding to duty cycles $D=0$, $D=1/2$ and $D=15/16$. This representation highlights that the lower extreme ($D=0$) is available, whereas the upper extreme ($D=1$) is excluded. As a result, a short low-level interval is always present at the top end of the duty-cycle range. Consequently, even the smallest change in the digital input code causes a corresponding change in the PWM duty cycle, which in turn modifies the average value of the signal within one period. Since the RC low-pass filter follows this average component, every minimal variation in the digital code produces a corresponding change in the steady-state output voltage.

Figure 3. PWM signal in the time domain for the mid-tread model ($N=4$) for three representative digital codes $d=0, 8$, and $15$, corresponding to the duty cycles $D=0, 1/2$, and $15/16$. The lower extreme is included, while the upper extreme $D=1$, corresponding formally to $d=2^N$, is excluded; therefore, a finite low-level interval remains even at the highest code. Horizontal axis: time normalized to the PWM period T; vertical axis: PWM output level.

• Mid-rise model—the operational range in this case is defined as:

$$D\in \left[{\displaystyle \frac{1}{2^N}},1\right],$$

(11)

meaning that the upper extreme $D=1$ is available, while the lower extreme $D=0$ is excluded.

As shown in Figure 4, the mid-rise realization illustrates three PWM periods with duty cycles $D=1/16$, $D=1/2$ and $D=1$, demonstrating that the upper extreme ($D=1$) is available, while the lower extreme ($D=0$) is excluded.

Figure 4. PWM signal in the time domain for the mid-rise model ($N=4$) for three representative digital codes $d=1, 8$, and $16$, corresponding to the duty cycles $D=1/16, 1/2$, and $1$. In this model, the upper extreme is included while the lower extreme $D=0$ is excluded, so a finite high-level interval remains at the low end of the range. Horizontal axis: time normalized to the PWM period T; vertical axis: PWM output level.

As a result, at the lower end of the range, each PWM period contains at least a short high-level interval. Consequently, even the smallest change in the digital input code results in a corresponding variation in the PWM duty cycle and, therefore, in the average value of the signal within one period. In this case as well, the RC low-pass filter follows this change in the average component, which leads to a measurable shift in the steady-state output voltage.

Depending on the selected quantization model, either the lower extreme or the upper extreme of the duty-cycle range is excluded. This treatment of extremes is important in practical PWM implementations, because different timer peripherals may define the compare event and the terminal counter value in different ways. As a result, the exact mapping between the digital code and the duty cycle must always be interpreted according to the selected PWM realization.

To enable a direct comparison of the code-to-voltage mapping, Figure 5 shows a 3-bit example of the discrete transfer characteristics of a PWM DAC for both quantization models. In the mid-tread model, the quantization levels lie on the interval boundaries, whereas in the mid-rise model they are centered within the intervals.

Figure 5. Discrete transfer characteristics of a 3-bit PWM DAC: (a) mid-tread model, where the quantization levels lie on the interval boundaries; (b) mid-rise model, where the levels are centered within intervals. Horizontal axis: digital code $d$; vertical axis: normalized steady-state output voltage. The blue and orange stepped lines represent the code-to-voltage mapping for the mid-tread and mid-rise models, respectively.

The discretized transfer function for code $d\mathsf{ϵ}\left[0, 2^N-1\right]$ in the mid-tread model is expressed as:

$$V_{o,q}\left(d\right)=V_{\mathrm{L}}+d∆,$$

(12)

where the quantization step is $∆ ={\displaystyle \frac{V_{\mathrm{H}}-V_{\mathrm{L}}}{2^N}}$.

For the mid-rise model, the discretized transfer function takes the form:

$$V_{o,q}\left(d\right)=V_{\mathrm{L}}+\left(d+{\displaystyle \frac{1}{2}}\right)∆,d\in \left[1,2^N\right].$$

(13)

In this paper, the mid-tread model is adopted for the main analysis because it is directly consistent with the duty-cycle definition introduced in Equation (1), $D=d/2^N$, where the digital code $d$ takes values from 0 to $2^N-1$. Under this convention, the lower extreme $D=0$ is included, while the upper extreme $D=1$ is excluded. This is representative of PWM counter implementations in which the duty cycle is generated by comparing an $N$-bit counter value with a digital compare value, so that the maximum digital code still leaves a finite low-level interval within each PWM period.

The choice of the mid-tread model also simplifies the connection between the digital code, the average output value, and the steady-state extrema derived in Equations (2)–(5). The safe-zone and settling-time criteria developed in the following sections are therefore formulated using this mapping.

For a mid-rise realization, the same analytical procedure can be applied after using the corresponding shifted code-to-duty-cycle relation implied by the mid-rise model. In that case, the interpretation of extremes, code boundaries, and quantization levels are shifted with respect to the mid-tread case.

Because the worst-case settling condition occurs near $D=1/2$, which is an interior duty cycle reachable in both models, the design criterion $k_{\min }$ (the minimum admissible value of the normalized filter parameter $k$, derived in Section 3.2) is identical for the two realizations. The half-quantization-step offset of the mid-rise grid may slightly shift the discrete code index and, consequently, the rounded discrete settling interval, depending on the selected PWM realization. The underlying first-order RC charging and discharging dynamics, and the form of the derived safe-zone and settling-time criteria, remain unchanged.

Consequently, the proposed framework is not limited to a particular timer implementation. When applying the derived expressions in practice, the designer must use the duty-cycle mapping that corresponds to the actual PWM peripheral and quantization convention.

3.2. Operating Zones

For the PWM DAC to function correctly, it is necessary that, for a given digital code $d$, the steady-state analog output voltage remains within the range $V_{\mathrm{L}}+\left(d\pm 1/2\right)∆$. In the ideal case, this condition ensures full coverage of the dynamic range of quantized voltage levels. However, under real operating conditions, due to unavoidable tolerances of the passive components of the RC low-pass filter (resistors and capacitors) and the presence of noise, the above requirement becomes overly relaxed.

Such an approximation may lead to situations, especially near the boundary (extreme) values of the duty cycle, where the results have no physical meaning, as the system cannot reach a stable steady-state condition without additional correction. For this reason, the analog output voltage range can be divided into safe and forbidden zones, as illustrated in Figure 6, where the safe zone for a given digital code $d$ is defined within the range $V_{\mathrm{L}}+\left(d\pm \epsilon \right)∆$, $0\le \epsilon <1/2$. The portion of the range not covered by the safe zones for all possible digital codes represents the forbidden regions of the PWM DAC output voltage in the steady state.

Figure 6. Illustration of safe and forbidden operating zones: (a) operating zones of the PWM DAC for a 3-bit input, where the green bands denote the safe zones satisfying the prescribed tolerance criterion, the orange bands denote the adjacent forbidden regions outside the allowed tolerance band, and the stepped black line represents the DAC transfer characteristic for digital codes from $d=0$ to $d=2^N-1$; (b) detailed zone structure around an arbitrary digital code $d$, showing the safe band $\left[d-\epsilon , d+\epsilon \right]$ in $\mathrm{LSB}$ and the adjacent forbidden margins up to $\pm 1/2 \mathrm{LSB}$.

As shown in Figure 6a, the operating zones of the PWM DAC are illustrated for a 3-bit input. The green areas represent safe zones in which the steady-state output satisfies the prescribed tolerance criterion, while the orange areas denote forbidden regions in which this criterion is not satisfied. The stepped black line represents the DAC transfer characteristic, with quantization levels ranging from $d=0$ to $d=2^N-1$.

Figure 6b shows the local structure of the zones around an arbitrary digital code $d$. This representation illustrates the safe band around the target code and the adjacent forbidden regions, which define the range within which the PWM DAC output must remain in order to satisfy the steady-state accuracy criterion.

In the steady-state condition, as shown in Figure 7, the following conditions must be satisfied for the safe zone:

$$v_{o,\mathrm{m}\mathrm{a}\mathrm{x}}\left[\mathrm{\infty },d\right]\le V_{\mathrm{L}}+\left(d+\epsilon \right){\displaystyle \frac{V_{\mathrm{H}}-V_{\mathrm{L}}}{2^N}},$$

(14)

$$v_{o,\mathrm{m}\mathrm{i}\mathrm{n}}\left[\infty ,d\right]\ge V_{\mathrm{L}}+\left(d-\epsilon \right){\displaystyle \frac{V_{\mathrm{H}}-V_{\mathrm{L}}}{2^N}}.$$

(15)

Figure 7. Illustration of the boundary conditions used to define the safe zone. For a given code $d$, the steady-state maximum output must not exceed the upper safe-zone boundary, and the steady-state minimum output must not fall below the lower safe-zone boundary. These two conditions yield the inequalities from which the admissible normalized filter parameter $k$ is derived.

After substituting (4) and (5) into the expressions for $v_{o,\max }\left[\mathrm{\infty },d\right]$ and $v_{o,\min }\left[\infty ,d\right]$, respectively, the following inequalities are obtained:

$${\displaystyle \frac{1-e^{-kd/2^N}}{1-e^{-k}}}\le {\displaystyle \frac{d+\epsilon }{2^N}},$$

(16)

and

$${\displaystyle \frac{e^{kd/2^N}-1}{e^k-1}}\ge {\displaystyle \frac{d-\epsilon }{2^N}}.$$

(17)

Before proceeding further, note that applying the substitution $d\to 2^N-d$ in Equation (17) yields Equation (16) for $k>0$, meaning that the two inequalities are equivalent and it is sufficient to consider only one of them.

In Equation (16), as the parameter $k$ increases, the denominator decreases faster than the numerator, causing the left-hand side to increase. Thus, inequality provides the following condition:

$$k\le k_{\mathrm{m}\mathrm{i}\mathrm{n}}\left(d\right).$$

(18)

The boundary value of $k_{\mathrm{m}\mathrm{i}\mathrm{n}}\left(d\right)$ is obtained as the solution of the equation

$$f\left(k_{\mathrm{m}\mathrm{i}\mathrm{n}}\left(d\right),d\right)=0,$$

(19)

where the function $f\left(k,d\right)$ is defined as:

$$f\left(k,d\right)=2^N\left(1-e^{-kd/2^N}\right)-\left(d+\epsilon \right)\left(1-e^{-k}\right).$$

(20)

To determine the worst-case operating condition, it is necessary to find the minimum of the function $k_{\min }\left(d\right)$, which represents the lowest value of the parameter $k$ for which the PWM DAC remains within the safe operating zone. Differentiating Equation (20) with respect to $d$ therefore gives:

$${\displaystyle \frac{dk}{dd}}={\displaystyle \frac{1-e^{-k}-k{e}^{-kd/2^N}}{d{e}^{-kd/2^N}-\left(d+\epsilon \right)e^{-k}}}.$$

(21)

The condition for the critical point is ${\displaystyle \frac{dk}{dd}}\left(d_{k,\min }\right)=0$, from which it follows that:

$$d_{k,\min }={\displaystyle \frac{2^N}{k}}\mathrm{l}\mathrm{n}{\displaystyle \frac{k}{1-e^{-k}}},$$

(22)

or equivalently,

$$e^{-k{d}_{k,\min }/2^N}={\displaystyle \frac{1-e^{-k}}{k}}.$$

(23)

By expanding the RHS term of Equation (23) into a Taylor series for small $k$ and substituting it into Equation (22), the expression for $d_{k,\min }$ can be approximated as:

$$d_{k,\min }={\displaystyle \frac{2^N}{k}}\mathrm{l}\mathrm{n}\left(1+{\displaystyle \frac{k}{2}}+{\displaystyle \frac{k^2}{12}}+\dots \right)\approx 2^N\left({\displaystyle \frac{1}{2}}-{\displaystyle \frac{k}{24}}\right)=2^{N-1}-2^{N-3}{\displaystyle \frac{k}{3}}\to 2^{N-1}.$$

(24)

The second derivative of $f\left(k,d\right)$ with respect to $k$, for $d=d_{k,\min }$, is:

$${\left.{\displaystyle \frac{d^{2}k}{d{d}^2}}\right|}_{d=d_{k,\min }}={\displaystyle \frac{\frac{k^2}{2^N}{e}^{-k{d}_{k,\min }/2^N}}{d_{k,\min }{e}^{-k{d}_{k,\min }/2^N}-\left(d_{k,\min }+\epsilon \right)e^{-k}}}\approx {\displaystyle \frac{\frac{k^2}{2^N}}{2^{N-1}-\left(2^{N-1}+\epsilon \right)e^{-k/2}}},$$

(25)

for $d_{k,\min }\approx 2^{N-1}$.

For $k_{\min }\left(d\right)$ to have a minimum at $d_{k,\min }$, the denominator must be positive:

$$2^{N-1}{e}^{-{\displaystyle \frac{k}{2}}}-\left(2^{N-1}+\epsilon \right)e^{-k}>0.$$

(26)

Using the same Taylor-series approximation applied earlier (for small values of $k$), inequality in Equation (26) yields:

$$k>2\mathrm{l}\mathrm{n}\left(1+{\displaystyle \frac{\epsilon }{2^{N-1}}}\right)=2\left({\displaystyle \frac{\epsilon }{2^{N-1}}}-{\displaystyle \frac{{\epsilon }^2}{2^{2N-1}}}+{\displaystyle \frac{{\epsilon }^3}{3}}{\displaystyle \frac{1}{2^{3N-3}}}-\dots \right)\approx {\displaystyle \frac{\epsilon }{2^{N-2}}}.$$

(27)

Since $d$ is a discrete variable, it is important to determine when the local minimum lies closer to $2^{N-1}$ than to $2^{N-1}-1$. This implies that the second term in Equation (24) must be:

$$2^{N-3}{\displaystyle \frac{k}{3}}\le {\displaystyle \frac{1}{2}}.$$

(28)

or equivalently,

$$k\le {\displaystyle \frac{3}{2^{N-2}}}.$$

(29)

The analysis confirms that the worst-case condition for $k_{\min }$ occurs when $d_{k,\min }\approx 2^{N-1}$, under the conditions expressed in Equations (27) and (29).

In the subsequent analysis, these conditions are assumed valid and will later be verified for consistency.

An estimation of $k_{\min }$ can be obtained from Equation (21), for ${d=2}^{N-1}$:

$$f\left(k,2^{N-1}\right)=0,$$

(30)

which gives:

$$2^N\left(1-e^{-k/2}\right)=\left(2^{N-1}+\epsilon \right)\left(1-e^{-k}\right).$$

(31)

With the substitution $e^{-k/2}=t$, the following quadratic equation is obtained:

$${{\displaystyle \frac{2^{N-1}+\epsilon }{2^N}}t}^2-t+1-{\displaystyle \frac{2^{N-1}+\epsilon }{2^N}}=0.$$

(32)

The solutions are:

$$t={\displaystyle \frac{1\pm \left(1-2\left(\frac{2^{N-1}+\epsilon }{2^N}\right)\right)}{2\left(\frac{2^{N-1}+\epsilon }{2^N}\right)}}.$$

(33)

Since the solution $t=1$ (i.e., $k=0$) is not physically meaningful, the valid solution is:

$$t={\displaystyle \frac{\frac{2^{N-1}}{\epsilon }-1}{\frac{2^{N-1}}{\epsilon }+1}}.$$

(34)

From this, it follows that:

$$k_{\mathrm{m}\mathrm{i}\mathrm{n}}=2\mathrm{l}\mathrm{n}{\displaystyle \frac{\frac{2^{N-1}}{\epsilon }+1}{\frac{2^{N-1}}{\epsilon }-1}}=4\mathrm{a}\mathrm{r}\mathrm{c}\mathrm{o}\mathrm{t}\mathrm{h}\left({\displaystyle \frac{2^{N-1}}{\epsilon }}\right)=4\left({\displaystyle \frac{\epsilon }{2^{N-1}}}+{\displaystyle \frac{1}{3}}{\displaystyle \frac{{\epsilon }^3}{2^{3N-3}}}+\dots \right)\approx {\displaystyle \frac{\epsilon }{2^{N-3}}}.$$

(35)

The validity of the conditions given by Equations (27) and (29) can now be verified:

• $k_{\mathrm{m}\mathrm{i}\mathrm{n}}>{\displaystyle \frac{\epsilon }{2^{N-2}}}$: always satisfied.
• $k_{\mathrm{m}\mathrm{i}\mathrm{n}}\le {\displaystyle \frac{3}{2^{N-2}}}:$ satisfied if $\epsilon \le {\displaystyle \frac{3}{2}}$. Since by definition $0\le \epsilon <{\displaystyle \frac{1}{2}}$, the condition is met in all practical cases.

Equation (35) shows that $k_{\min }$ decreases as the DAC resolution $N$ increases. This means that higher-resolution PWM DAC operation requires a smaller normalized filter parameter $k=T/RC$, i.e., stronger low-pass filtering relative to the PWM period. Consequently, the improvement in steady-state accuracy is obtained at the cost of a longer settling interval. The tolerance $\epsilon$ directly influences the width of the safe zone—a larger tolerance increases the allowable range around the target code but relaxes the required settling accuracy.

In addition to the dependence of $k_{\min }$ on $N$ and $\epsilon$, the approximation errors arising from the use of the simplified expression for estimating $k_{\min }$ are also analyzed. The simplified approximation $k_{\mathrm{m}\mathrm{i}\mathrm{n}}^{\mathrm{approx}}\approx {\displaystyle \frac{\epsilon }{2^{N-3}}}$ is compared with the exact analytical value:

$$k_{\mathrm{m}\mathrm{i}\mathrm{n}}^{\mathrm{real}}=2\mathrm{l}\mathrm{n}{\displaystyle \frac{2^{N-1}/\epsilon +1}{2^{N-1}/\epsilon -1}}.$$

(36)

Both the relative and absolute approximation errors are considered.

Figure 8 shows the dependence of the exact analytical value $k_{\min }$ ($k_{\mathrm{m}\mathrm{i}\mathrm{n}}^{\mathrm{real}}$, expressed in Equation (36)) on the number of bits $N$ for several typical tolerance values, $\epsilon =1/3, 1/4,$ and $1/5$. These values are selected because they are below the maximum permissible limit $\epsilon <{\displaystyle \frac{1}{2}}$, ensuring operation within the prescribed safe-zone tolerance.

Figure 8. Exact limiting admissible normalized filter parameter $k_{\min }$ as a function of the number of bits $N$, obtained from Equation (36). The three curves correspond to the tolerance values $\epsilon =1/3, 1/4,$ and $1/5$. Horizontal axis: number of bits $N$; vertical axis: $k_{\min }$, the limiting value of $k=T/\tau =T/RC$ at which the safe-zone criterion is satisfied. The decrease of $k_{\min }$ with $N$ shows that higher-resolution PWM DACs require a smaller normalized filter parameter, i.e., stronger low-pass filtering relative to the PWM period, for the same settling tolerance.

Figure 9 shows the relative approximation error of the parameter $k_{\min }$, defined as:

$$\mathrm{Relative} \mathrm{Error} \left[\%\right]=\left|{\displaystyle \frac{k_{\mathrm{m}\mathrm{i}\mathrm{n}}^{\mathrm{approx}}-k_{\mathrm{m}\mathrm{i}\mathrm{n}}^{\mathrm{real}}}{k_{\mathrm{m}\mathrm{i}\mathrm{n}}^{\mathrm{real}}}}\right|·100\%.$$

(37)

Figure 9. Relative approximation error of the parameter $k_{\min }$, defined as the relative difference between the simplified design rule $k_{\min }\approx {\displaystyle \frac{\epsilon }{2^{N-3}}}$ from Equation (35) and the exact value from Equation (36), expressed in percent. The curves correspond to $\epsilon =1/3, 1/4,$ and $1/5$. Horizontal axis: number of bits $N$; vertical axis: relative error [%]. The error decreases rapidly with increasing $N$, confirming that the simplified rule is highly accurate over the practical resolution range.

Figure 10 illustrates the absolute error:

$$\mathrm{Absolute} \mathrm{Error}=\left|k_{\mathrm{m}\mathrm{i}\mathrm{n}}^{\mathrm{approx}}-k_{\mathrm{m}\mathrm{i}\mathrm{n}}^{\mathrm{real}}\right|.$$

(38)

Figure 10. Absolute approximation error of the parameter $k_{\min }$, defined as the absolute difference between the simplified design rule $k_{\min }\approx {\displaystyle \frac{\epsilon }{2^{N-3}}}$ from Equation (35) and the exact value from Equation (36). The curves correspond to $\epsilon =1/3,1/4,$ and $1/5$. Horizontal axis: number of bits $N$; vertical axis: absolute error in the dimensionless parameter $k$. The error decreases monotonically with increasing resolution.

For both error metrics shown in Figure 9 and Figure 10, the curves are plotted for three typical tolerance values, $\epsilon =1/3,1/4,$ and $1/5$. Both the relative and absolute approximation errors decrease with increasing number of bits $N$, confirming that the simplified expressions become more accurate for higher-resolution DACs.

The validity range of the simplified design rule can also be stated analytically. The approximation $k_{\min }\approx \epsilon /2^{N-3}$ in Equation (35) is obtained by retaining the leading term of the series expansion used to simplify the exact expression. The ratio of the first neglected term to the retained leading term gives the following estimate of the relative approximation error:

$${\displaystyle \frac{∆k_{\min }}{k_{\min }}}\approx {\displaystyle \frac{1}{3}}{\left({\displaystyle \frac{\epsilon }{2^{N-1}}}\right)}^2.$$

(39)

This expression shows that the accuracy of the simplified rule depends only on $N$ and $\epsilon$, and improves rapidly with increasing resolution. In the practical range considered in Figure 9 and Figure 10, $4\le N\le 12,$ and for the general admissible tolerance range $0\le \epsilon <1/2$, the estimated relative error remains below approximately $0.13\%$, reaching this maximum only at the lowest resolution $N=4$ and at the limiting tolerance $\epsilon \to 1/2$. For $N\ge 8$, the estimated relative error falls below $0.001\%$ over the same tolerance range.

Therefore, the simplified expression $k_{\min }\approx \epsilon /2^{N-3}$ can be used as a compact design rule across the considered practical range of resolutions and tolerances, in agreement with the numerical results shown in Figure 9 and Figure 10. If the expression is extrapolated to the extreme theoretical case $N=1$ and $\epsilon \to 1/2$, the estimated relative error remains below approximately $10\%$. However, for such very low-resolution limiting cases, the exact expression in Equation (36) should be used.

It is also important to analyze the position of the critical point $d_{k,\min }$, where the function $k_{\min }\left(d\right)$ reaches its minimum, since this point defines the boundary condition for stable system operation.

Figure 11 shows the deviation error of the critical-point position $d_{k,\min }$, as derived in Equation (24), relative to the assumed value $d=2^{N-1}$, for different values of the bit number $N$.

Figure 11. Deviation of the critical-point position from the central reference code $d=2^{N-1}$ used in the worst-case approximation. The plotted quantity is $d_{k,\min }-2^{N-1}$, expressed in LSB, for $\epsilon =1/3,1/4,$ and $1/5$. Horizontal axis: number of bits $N$; vertical axis: critical-point deviation $d_{k,\min }-2^{N-1}$ [$\mathrm{LSB}$]. The small magnitude of the deviation, which remains well below one $\mathrm{LSB}$ over the considered range, shows that the critical point is close to the central code and supports the approximation used in the subsequent settling-time analysis.

Based on the approximation of the critical point given in Equation (27), the second term in the expression $d_{k,\min }\approx 2^{N-1}-2^{N-3}{\displaystyle \frac{k}{3}}=2^{N-1}-{\displaystyle \frac{\epsilon }{3}}$ represents a correction of the critical-point position that depends on the tolerance $\epsilon$ (since $k\approx {\displaystyle \frac{\epsilon }{2^{N-3}}}$ from Equation (35)). For typical values $0\le \epsilon <1/2$, the contribution of this term is smaller than one quantization step (1 $\mathrm{LSB}$), and can therefore be considered negligible in further calculations, as confirmed by the results in Figure 11.

Consequently, to simplify the expressions, the critical point can be approximated without significant loss of accuracy such as:

$$d_{k_{min}}\approx 2^{N-1},$$

(40)

which confirms the initial assumption that the worst-case condition for $k_{\mathrm{m}\mathrm{i}\mathrm{n}}$ occurs approximately at $d=2^{N-1}$.

After considering the error in the position of the critical point, the next step in analyzing the PWM DAC structure is to examine the margins, i.e., the distance between the maximum and minimum steady-state output voltages and the boundaries of the safe zone for a given code $d$.

The analysis of the maximum margin is performed by defining the function $m_{\max }\left(d\right)$:

$$m_{\mathrm{m}\mathrm{a}\mathrm{x}}\left(d\right)={\displaystyle \frac{V_{\mathrm{L}}+\left(d+\epsilon \right)\frac{V_{\mathrm{H}}-V_{\mathrm{L}}}{2^N}-v_{o,\mathrm{m}\mathrm{a}\mathrm{x}}\left[\infty ,d\right]}{∆}},$$

(41)

where the distance between $v_{o,\mathrm{m}\mathrm{a}\mathrm{x}}\left[\infty ,d\right]$ and the boundary of the safe zone is normalized with respect to the quantization step $∆.$

By substituting the known expression given by Equation (4) for the steady-state output voltage $v_{o,\mathrm{m}\mathrm{a}\mathrm{x}}\left[\infty ,d\right]$, the margin function becomes:

$$m_{\mathrm{m}\mathrm{a}\mathrm{x}}\left(d\right)=d+\epsilon -2^N{\displaystyle \frac{1-e^{-kd/2^N}}{1-e^{-k}}}.$$

(42)

To find the point of minimum of the margin, the first derivative of the function $m_{\max }\left(d\right)$ is calculated:

$$m_{\mathrm{m}\mathrm{a}\mathrm{x}}^{\prime }\left(d\right)=1-k{\displaystyle \frac{e^{-kd/2^N}}{1-e^{-k}}}.$$

(43)

By setting $m_{\mathrm{m}\mathrm{a}\mathrm{x}}^{\prime }\left(d\right)=0$, the critical point $d^{*}$ is obtained:

$$e^{-k{d}^{*}/2^N}={\displaystyle \frac{1-e^{-k}}{k}}\Rightarrow {\displaystyle \frac{d^{*}}{2^N}}={\displaystyle \frac{1}{k}}\mathrm{l}\mathrm{n}{\displaystyle \frac{k}{1-e^{-k}}}.$$

(44)

Hence,

$$d^{*}={\displaystyle \frac{2^N}{k}}\left({\displaystyle \frac{k}{2}}-{\displaystyle \frac{k^2}{24}}+{\displaystyle \frac{k^4}{2880}}+\dots \right)\approx 2^{N-1}.$$

(45)

The second derivative confirms that the point $d^{*}$ corresponds to a minimum:

$$m_{\mathrm{m}\mathrm{a}\mathrm{x}}^{″}\left(d\right)={\displaystyle \frac{1}{2^N}}{\displaystyle \frac{k^2}{1-e^{-k}}}{e}^{-kd/2^N}>0,$$

(46)

for $\forall d$, indicating that the function is convex.

Using relation given by Equation (44) in Equation (42), the analytical expression for the lower bound of the maximum margin is obtained:

$$m_{\mathrm{m}\mathrm{a}\mathrm{x}}\left(d^{*}\right)=2^N{\displaystyle \frac{1}{k}}\mathrm{l}\mathrm{n}{\displaystyle \frac{k}{1-e^{-k}}}-2^N{\displaystyle \frac{k-1+e^{-k}}{k\left(1-e^{-k}\right)}}+\epsilon .$$

(47)

Substituting $\epsilon =2^{N-3}k$ yields:

$$m_{\mathrm{m}\mathrm{a}\mathrm{x}}\left(d^{*}\right)=2^N\left({\displaystyle \frac{1}{k}}\mathrm{l}\mathrm{n}{\displaystyle \frac{k}{1-e^{-k}}}-{\displaystyle \frac{k-1+e^{-k}}{k\left(1-e^{-k}\right)}}+{\displaystyle \frac{k}{8}}\right)\approx {\displaystyle \frac{2^{N-6}}{9}}{k}^3={\displaystyle \frac{8}{9}}{\displaystyle \frac{{\epsilon }^3}{2^{2N}}}>0.$$

(48)

After determining the lower bound of the maximum margin, it is also necessary to examine the behavior of the margin at the boundaries of the digital input range, i.e., for $d=0$ and $d=2^N-1$. These boundary points represent extreme cases, and it is essential to verify that the margin remains within the prescribed tolerance $\epsilon$.

For $d=0$:

$$m_{\mathrm{m}\mathrm{a}\mathrm{x}}\left(0\right)=\epsilon ,$$

(49)

which represents the maximum possible margin value and thus satisfies the condition that the margin does not exceed $\epsilon$.

For $d=2^N-1$:

$$m_{\mathrm{m}\mathrm{a}\mathrm{x}}\left(2^N-1\right)=\epsilon -\left(1-2^N{\displaystyle \frac{e^{k/2^N}-1}{e^k-1}}\right)\lesssim \epsilon ,$$

(50)

confirming that the condition is met.

Figure 12 presents the results of the numerical analysis of the maximum margin function $m_{\mathrm{m}\mathrm{a}\mathrm{x}}\left(d\right)$ for various $N$ and tolerance values $\epsilon$.

Figure 12. Maximum margin function $m_{\mathrm{m}\mathrm{a}\mathrm{x}}\left(d\right)$ across the digital input range, evaluated for the optimal boundary value $k=k_{\min }$. The horizontal axis is the normalized digital code $d/2^N$, and the vertical axis is the normalized maximum margin $m_{\mathrm{m}\mathrm{a}\mathrm{x}}\left(d\right)$, expressed in $\mathrm{LSB}$. For each tolerance level $\epsilon =1/3,1/4,$ and $1/5$ (dashed horizontal lines), a separate group of curves is shown for $N=4, 8,$ and $12$. Within each group, the curves for different $N$ nearly coincide because of the normalized representation, with the green curve ($N=12$), drawn last, appearing dominant in the overlapping regions. In every case the curves reach but do not exceed the corresponding $\epsilon$ line, confirming that the upper-boundary condition $m_{\mathrm{m}\mathrm{a}\mathrm{x}}\left(d\right)\le \epsilon$ is satisfied over the complete code range.

From the presented graph, it can be concluded that the condition $m_{\mathrm{m}\mathrm{a}\mathrm{x}}\left(d\right)\le \epsilon$ is satisfied throughout the entire digital input range $d\in \left[0-\left(2^N-1\right)\right]$.

After examining the maximum margin, the next step is to determine the minimum margin of the output signal, defined as:

$$m_{\mathrm{m}\mathrm{i}\mathrm{n}}\left(d\right)={\displaystyle \frac{v_{o,\mathrm{m}\mathrm{i}\mathrm{n}}\left[\infty ,d\right]-\left(V_{\mathrm{L}}+\left(d-\epsilon \right)\frac{V_{\mathrm{H}}-{\mathrm{V}}_{\mathrm{L}}}{2^N}\right)}{∆}}=2^N{\displaystyle \frac{e^{-k\left(1-d/2^N\right)}-e^{-k}}{1-e^{-k}}}-\left(d-\epsilon \right).$$

(51)

Differentiating Equation (51) gives:

$$m_{\min }^{\prime }\left(d\right)=k{\displaystyle \frac{e^{-k\left(1-d/2^N\right)}}{1-e^{-k}}}-1.$$

(52)

Setting $m_{\min }^{\prime }\left(d\right)=0$, yields the critical point $d^{**}$:

$$e^{-k\left(1-d^{**}/2^N\right)}={\displaystyle \frac{1-e^{-k}}{k}}\Rightarrow {\displaystyle \frac{d^{**}}{2^N}}=1-{\displaystyle \frac{1}{k}}\mathrm{l}\mathrm{n}{\displaystyle \frac{k}{1-e^{-k}}},$$

(53)

which leads to:

$$d^{**}\to 2^{N-1},$$

(54)

i.e., the same critical point as in the maximum margin case ($d^{**}=d^{*}$).

The second derivative of Equation (51) is:

$$m_{\min }^{″}\left(d\right)={\displaystyle \frac{1}{2^N}}{\displaystyle \frac{k^2}{1-e^{-k}}}{e}^{-k\left(1-d/2^N\right)}>0,$$

(55)

confirming that the function is convex and that $d^{**}$ is indeed a minimum point.

Substituting relation expressed in Equation (53) into Equation (51) yields the analytical expression for the lower bound of the minimum margin:

$$m_{\mathrm{m}\mathrm{i}\mathrm{n}}\left(d^{**}\right)=2^N{\displaystyle \frac{1}{k}}\mathrm{l}\mathrm{n}{\displaystyle \frac{k}{1-e^{-k}}}-2^N{\displaystyle \frac{k-1+e^{-k}}{k\left(1-e^{-k}\right)}}+\epsilon ,$$

(56)

confirming that the margin is identical to that in Equation (47) and remains above zero and within the permissible tolerance $\epsilon$.

After determining the minimum point $d^{**}$, as in the case of the maximum margin, it is necessary to verify the boundary cases for $d=0$ and $d=2^N-1$.

Verification at $d=0$:

$$m_{\mathrm{m}\mathrm{i}\mathrm{n}}\left(0\right)=\epsilon ,$$

(57)

which corresponds to the largest possible margin value and confirms that it does not exceed the allowed tolerance.

Verification at $d=2^N-1$:

$$m_{\mathrm{m}\mathrm{i}\mathrm{n}}\left(2^N-1\right)=\epsilon -\left(2^N{\displaystyle \frac{1-e^{-k/2^N}}{1-e^{-k}}}-1\right)<\epsilon .$$

(58)

This result verifies that even at the upper limit of the digital range, the minimum margin remains within the specified tolerance band.

Figure 13 shows the results of the numerical analysis of the minimum margin function $m_{\mathrm{m}\mathrm{i}\mathrm{n}}\left(d\right)$ for different values of $N$ and tolerance $\epsilon$.

Figure 13. Minimum margin function $m_{\mathrm{m}\mathrm{i}\mathrm{n}}\left(d\right)$ across the digital input range, evaluated for the optimal boundary value $k=k_{\min }$. The horizontal axis is the normalized digital code $d/2^N$, and the vertical axis is the normalized minimum margin $m_{\mathrm{m}\mathrm{i}\mathrm{n}}\left(d\right)$, expressed in $\mathrm{LSB}$. The curves are shown for $N=4, 8, 12$, while the dashed horizontal lines indicate the tolerance levels $\epsilon =1/3,1/4,$ and $1/5$. The plot confirms that the lower-boundary condition is satisfied over the complete code range. For each tolerance level $\epsilon =1/3,1/4,$ and $1/5$ (dashed horizontal lines), a separate group of curves is shown for $N=4, 8,$ and $12$. Within each group, the curves for different $N$ nearly coincide because of the normalized representation, with the green curve ($N=12$), drawn last, appearing dominant in the overlapping regions. In every case the curves reach but do not exceed the corresponding $\epsilon$ line, confirming that the lower-boundary condition $m_{\mathrm{m}\mathrm{i}\mathrm{n}}\left(d\right)\le \epsilon$ is satisfied over the complete code range.

Based on the presented analyses of the maximum and minimum margin functions, it can be concluded that for the optimal value of $k$, the maximum output voltage always lies within the range $V_{\mathrm{L}}+d∆ \le v_{o,\max }\le V_{\mathrm{L}}+\left(d+\epsilon \right)∆$, while the minimum output voltage remains within $V_{\mathrm{L}}+\left(d-\epsilon \right)∆ \le v_{o,\min }\le V_{\mathrm{L}}+d∆$, as illustrated in Figure 14.

Figure 14. Visual representation of the maximum and minimum steady-state output margins with respect to the safe-zone boundaries, for the optimal boundary value $k=k_{\min }$. The steady-state maximum output remains below the upper safe-zone boundary, and the steady-state minimum output remains above the lower safe-zone boundary; therefore, the complete ripple envelope lies within the safe band of width $2\epsilon$ around the target code $d$.

The conclusions regarding margin behavior provide important confirmation of the robustness of the digital-to-analog conversion in PWM DAC systems. Observation of the steady-state output signal shows that the margin never exceeds the permissible interval defined by the tolerance $\epsilon$, even at the boundary points of the digital input. This analysis enables the designer to confidently dimension system parameters, ensuring both accuracy and stability of conversion across the entire digital input range.

Based on the analysis of the safe operating zones and the maximum/minimum output margins, a framework has been established for further investigation of the system’s dynamic characteristics, primarily the settling time, which is examined in the following section.

4. Settling Time of the PWM DAC Output

The settling time $T_S=nT$ is a key parameter that defines the dynamic performance of a PWM DAC system. In the context of a digitally controlled RC filter, it represents the minimum number of PWM periods $n$ required for the output signal to enter and remain within the specified tolerance band $\epsilon$ around the target value, following a change in the digital input code $d$.

The goal of this chapter is, for a given RC filter configuration and digital code transition, to analytically establish the relationship between the required number of periods $n$ (i.e., the settling time $T_S$) and the system parameters: the number of bits $N$, the tolerance $\epsilon$, and the parameter $k$.

In the settling-time analysis, the target entry boundary is defined by the conventional code-decision interval of $\pm 1/2 \mathrm{LSB}$ around the target code, while the parameter $\epsilon$ is used to define the steady-state safe-zone margin and to select the admissible value of $k$.

As reference (extreme) transitions, the cases $0\to 2^N-1$ and $2^N-1\to 0$ are analyzed. However, the derived expressions are general and valid for any transition between digital codes.

Throughout this analysis, we adopt the following notation: $d_1$ denotes the initial code, and $d_2$ denotes the target code. Two complementary situations are considered: the rising mode ($d_1<d_2$) and the decreasing mode ($d_1>d_2$).

4.1. Settling Time for the Rising Code Transition

In this case, as previously stated, the input digital code changes from $d_1$ to a higher value $d_2$, which results in an increase in the output-voltage level.

As illustrated in Figure 15, the output signal oscillates due to the PWM excitation and the RC filter response but gradually converges toward the new steady-state value $V_{\mathrm{L}}+d_2∆$.

Figure 15. Time-domain response of the PWM DAC output with the RC filter for a rising code transition $d_1\to d_2$, where $d_1<d_2$. The output oscillates due to the PWM excitation and converges toward the new steady state. The green band denotes the safe zone of code $d_2$, the orange band denotes the adjacent forbidden zone, and the dashed lines mark the target level and zone boundaries. The annotated instant marks the end of the settling interval, when the output minimum first enters and remains within the safe zone. Horizontal axis: time $t/T$ [PWM periods].

To determine the settling time for the rising output transition, the output signal must enter and remain within the zone corresponding to the new digital code $d_2$, if the value of the parameter $k$ is appropriately selected. In this case, the minimum value of the output voltage must exceed the lower boundary of the target zone, defined as $V_{\mathrm{L}}+\left(d_2-1/2\right){\displaystyle \frac{V_{\mathrm{H}}-V_{\mathrm{L}}}{2^N}}$.

The settling condition is therefore expressed as:

$$v_{ o,\min }\left[\left(n+1\right),d_2\right]\ge V_{\mathrm{L}}+\left(d_2-{\displaystyle \frac{1}{2}}\right){\displaystyle \frac{V_{\mathrm{H}}-V_{\mathrm{L}}}{2^N}}.$$

(59)

In this mode, the settling condition is evaluated with respect to $v_{o,\min }\left[\left(n+1\right),d_2\right]$, which represents the first minimum of the output signal that is fully determined by the new input code $d_2$.

Based on the expression for the minimum of the output voltage expressed in Equation (3), for the ($n+1$) period, the analytical form can be written as:

$$\begin{gathered} v_{o,\mathrm{m}\mathrm{i}\mathrm{n}}\left[\left(n+1\right),d_2\right] \\ \hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}=V_0{e}^{-kn}+V_{\mathrm{H}}{\displaystyle \frac{e^{-k\left(1-d_2/2^N\right)}-e^{-k}}{1-e^{-k}}}\left(1-e^{-kn}\right) \\ \hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}+V_{\mathrm{L}}{\displaystyle \frac{1-e^{-k\left(1-d_2/2^N\right)}}{1-e^{-k}}}\left(1-e^{-kn}\right). \end{gathered}$$

(60)

From this, the minimum number of periods $n$ required to satisfy the settling condition is obtained as:

$$n\ge {\displaystyle \frac{1}{k}}\mathrm{l}\mathrm{n}\left({\displaystyle \frac{V_{\mathrm{H}}\frac{e^{-k\left(1-\frac{d_2}{2^N}\right)}-e^{-k}}{1-e^{-k}}+V_{\mathrm{L}}\frac{1-e^{-k\left(1-\frac{d_2}{2^N}\right)}}{1-e^{-k}}-V_0}{V_{\mathrm{H}}\frac{e^{-k\left(1-\frac{d_2}{2^N}\right)}-e^{-k}}{1-e^{-k}}+V_{\mathrm{L}}\frac{1-e^{-k\left(1-\frac{d_2}{2^N}\right)}}{1-e^{-k}}-V_{\mathrm{L}}-\left(d_2-\frac{1}{2}\right)\frac{V_{\mathrm{H}}-V_{\mathrm{L}}}{2^N}}}\right).$$

(61)

Here, $V_0$ represents the initial output voltage of the PWM DAC at the moment of code transition from $d_1$ to $d_2$, given by:

$$V_0=v_{o,\mathrm{m}\mathrm{i}\mathrm{n}}\left[\infty ,d_1\right]=V_{\mathrm{H}}{\displaystyle \frac{e^{-k\left(1-d_1/2^N\right)}-e^{-k}}{1-e^{-k}}}+V_{\mathrm{L}}{\displaystyle \frac{1-e^{-k\left(1-d_1/2^N\right)}}{1-e^{-k}}}.$$

(62)

By substituting Equation (62) into Equation (61), a general formula for the number of periods required for the output to settle is obtained:

$$n\left(d_1,d_2\right)\ge {\displaystyle \frac{1}{k}}\mathrm{l}\mathrm{n}\left({\displaystyle \frac{e^{k{d}_2/2^N}-e^{k{d}_1/2^N}}{\left(e^{k{d}_2/2^N}-1\right)-\left(e^k-1\right)\left(d_2-\frac{1}{2}\right)\frac{1}{2^N}}}\right).$$

(63)

This relation provides an exact analytical expression for the settling time $T_S=nT$ in the case of a rising digital code transition, taking into account the initial state, the target code, and the exponential response of the RC filter.

To illustrate the analytical expression for the settling time, Figure 16 shows the number of periods required for the output signal to enter the safe zone for various combinations of input codes, in the case where $d_1<d_2$. For the simulation’s purpose, the following parameters were used: $d_1\in [0, 2^N-2]$, $d_2\in [d_1+1, 2^N-1]$, $N=8$, $\epsilon =1/4$. Each curve corresponds to a fixed $d_1$, while $d_2$ varies along the horizontal axis.

Figure 16. Settling interval $n\left(d_1,d_2\right)$ for rising transitions $d_1<d_2$, evaluated for $N=8$ and $\epsilon =1/4$. Each curve corresponds to a fixed initial code $d_1$, indicated by the viridis color bar, while the target code $d_2$ varies. Horizontal axis: target code $d_2$; vertical axis: settling interval $n\left(d_1,d_2\right)$ [PWM periods]. The maximum settling interval occurs at an interior target code rather than at the largest possible code.

Interestingly, the maximum number of periods required to determine the settling time does not correspond to the upper boundary $d_2=2^N-1$, as might be intuitively expected, but rather occurs for a slightly smaller value of $d_2$. To confirm this observation, a formal analysis of Equation (63) is carried out.

For a fixed value of $d_2$, and a variable $d_1$, the derivative of the function $n\left(d_1, d_2\right)$ with respect to $d_1$ is given by:

$${\displaystyle \frac{\mathrm{d}n\left(d_1,d_2\right)}{\mathrm{d}{d}_1}}={\displaystyle \frac{1}{k}}{\displaystyle \frac{\mathrm{d}}{\mathrm{d}{d}_1}}\ln \left(e^{k{d}_2/2^N}-e^{k{d}_1/2^N}\right)=-{\displaystyle \frac{1}{2^N}}{\displaystyle \frac{e^{k{d}_1/2^N}}{e^{k{d}_2/2^N}-e^{k{d}_1/2^N}}}.$$

(64)

Since $d_2>d_1$ and $\mathrm{d}n\left(d_1,d_2\right)/\mathrm{d}{d}_1<0$, the maximum is achieved for $d_1=0$.

For this case, i.e., for the worst-case condition when the initial digital code has its minimum value $d_1=0$, the number of periods required for settling can be analytically expressed as:

$$\begin{gathered} n\left(d_1=0,d_2\right)\ge {\displaystyle \frac{1}{k}}\mathrm{l}\mathrm{n}{\displaystyle \frac{e^{k{d}_2/2^N}-1}{\left(e^{k{d}_2/2^N}-1\right)-\left(e^k-1\right)\left(d_2-\frac{1}{2}\right)2^{-N}}} \\ \hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}=-{\displaystyle \frac{1}{k}}\mathrm{l}\mathrm{n}\left(1-{\displaystyle \frac{d_2-\frac{1}{2}}{2^N}}{\displaystyle \frac{e^k-1}{e^{k{d}_2/2^N}-1}}\right). \end{gathered}$$

(65)

To determine the value of $d_2$ that yields the maximum settling time, the condition for the extremum of the function is used—that is, the first derivative of $n\left(d_1=0, d_2\right)$ with respect to $d_2$ must be zero:

$${\displaystyle \frac{\mathrm{d}n\left(d_1=0,{ d}_2\right)}{\mathrm{d}{d}_2}}=0\Rightarrow 1-e^{-k{d}_2/2^N}={\displaystyle \frac{k}{2^N}}(d_2-{\displaystyle \frac{1}{2}}).$$

(66)

The general solution of this equation cannot be obtained in a simple closed form, so approximation is employed by expanding the exponential term into a Taylor series for small values of $k/2^N$:

$$e^{-k{d}_2/2^N}\approx 1-{\displaystyle \frac{k}{2^N}}{d}_2+{\displaystyle \frac{1}{2}}{\left({\displaystyle \frac{k}{2^N}}\right)}^2{d_2}^2.$$

(67)

By substituting this approximation into Equation (66) and solving, we obtain an expression for the position of the maximum:

$$d_{2,\mathrm{m}\mathrm{a}\mathrm{x}1}=\sqrt{{\displaystyle \frac{2^N}{k}}}\approx \sqrt{{\displaystyle \frac{2^N}{\epsilon /2^{N-3}}}}={\displaystyle \frac{2^{N-1}}{\sqrt{2\epsilon }}}.$$

(68)

Substituting $d_2=d_{2,\max 1}$ into Equation (65) and using the substitution for parameter $k$ from Equation (35), we obtain the maximum number of periods required for settling in this case:

$$n\left(d_1=0,d_2=d_{2,\mathrm{m}\mathrm{a}\mathrm{x}1}\right)=-{\displaystyle \frac{2^{N-3}}{\epsilon }}\mathrm{l}\mathrm{n}\left(1-{\displaystyle \frac{1}{2}}\left({\displaystyle \frac{1}{\sqrt{2\epsilon }}}-{\displaystyle \frac{1}{2^N}}\right){\displaystyle \frac{e^{\frac{\epsilon }{2^{N-3}}}-1}{e^{\frac{\sqrt{2\epsilon }}{2^{N-1}}}-1}}\right).$$

(69)

To further illustrate and validate the expression for the maximum number of periods required for settling time in the case where $d_1=0$ and $d_2=d_{2,\mathrm{m}\mathrm{a}\mathrm{x}1}$, Figure 17 shows the dependence of the number of periods $n$ on the number of bits $N$, for three different tolerance values $\epsilon =1/3, 1/4, 1/5$.

Figure 17. Worst-case rising-mode settling interval as a function of the number of bits $N$, for $\epsilon =1/3,1/4,$ and $1/5$. The transition is from the lowest code $d_1=0$ to the target code $d_2=d_{2,max1}$, where the rising-mode settling interval reaches its maximum. Horizontal axis: number of bits $N$; vertical axis: settling interval [PWM periods]. The required number of periods increases with resolution and with stricter tolerance.

The results confirm the exponential growth of the settling time with increasing PWM DAC resolution. It is also evident that a smaller tolerance $\epsilon$ leads to a significant increase in the number of periods $n$ required to reach a stable steady-state value.

This analysis provides valuable insight into the trade-off between accuracy (smaller tolerance $\epsilon$) and response speed (shorter settling time), which is crucial in the design of digitally controlled analog systems.

Figure 18 quantitatively evaluates the quality of the approximation of the settling-time maximum position by comparing the exact solution (where $d_2$ is obtained from Equation (66)) and the approximate one from Equation (68).

Figure 18. Difference between the exact and approximate positions of the rising-mode settling-time maximum, expressed in $\mathrm{LSB}$, as a function of the number of bits $N$, for $\epsilon =1/3, 1/4,$ and $1/5$. The small difference shows that the closed-form approximation accurately predicts the target-code position at which the rising-mode maximum occurs.

As shown in Figure 18, the difference is small, approximately 0.17 $\mathrm{LSB}$ for lower values of $N$, and it decreases as $N$ increases. Therefore, the approximation $d_{2,\mathrm{m}\mathrm{a}\mathrm{x}1}\approx 2^{N-1}/\sqrt{2\epsilon }$ can be safely applied in practice.

Since the difference in the position of the settling-time maximum is small, it is expected that the error in the estimated settling time will also be small, which is confirmed by Figure 19.

Figure 19. Difference between the approximate and exact continuous, non-rounded rising-mode settling intervals at the maximum, expressed in PWM periods, as a function of the number of bits $N$, for $\epsilon =1/3, 1/4,$ and $1/5$. The very small difference confirms that approximation has negligible influence before integer rounding.

As the PWM DAC operates in the digital domain, the number of periods required for settling is an integer quantity. Given that the difference shown in Figure 19 is negligible, Figure 20 illustrates that after rounding, the resulting discrete values are practically identical. In other words, the number of periods obtained from the exact approach expressed in Equation (65), using Equation (66) for the maximum point, fully coincides with that obtained from the approximation given by Equation (69).

Figure 20. Difference between the rounded integer rising-mode settling counts obtained from the approximate and exact expressions as a function of the number of bits $N$, for $\epsilon =1/3,1/4,$ and $1/5$. The difference is given in PWM periods. After rounding to an integer number of PWM periods, the difference is zero for all three tolerance values, so the curves overlap and only the last-drawn green curve ($\epsilon =1/5$) is visible.

The presented comparison confirms the applicability of the approximate expression given by Equation (69) in the digital implementation of the PWM DAC, as this simplified approach yields the same integer result for the settling-time period count as the exact expression given by Equation (65) in the rising mode of the digital code.

4.2. Settling Time for the Decreasing Code Transition

In this operating mode, where the digital input code decreases, the output voltage correspondingly decreases as well. The settling time is determined based on the moment when the maximum value of the output signal within a PWM period first falls below the upper boundary of the safe zone corresponding to the digital code $d_2$, and remains within that zone—assuming that the value of the parameter $k$ is properly selected. The upper boundary of the zone assigned to code $d_2$ is defined as $V_{\mathrm{L}}+\left(d_2+1/2\right){\displaystyle \frac{V_{\mathrm{H}}-V_{\mathrm{L}}}{2^N}}$. An illustration of the PWM DAC output time response for the case $d_1>d_2$ is shown in Figure 21.

Figure 21. Time-domain response of the PWM DAC output with the RC filter for a decreasing code transition $d_1\to d_2$, where $d_1>d_2$. The output oscillates due to the PWM excitation and converges toward the new steady state. The green band denotes the safe zone of code $d_2$, the orange band denotes the adjacent forbidden zone, and the dashed lines mark the target level and zone boundaries. The annotated instant marks the end of the settling interval, when the output maximum first falls below and remains under the upper safe-zone boundary. Horizontal axis: time $t/T$ [PWM periods].

The maximum output voltage after $n$ periods for code $d_2$ can be expressed using Equation (2) as:

$$\begin{gathered} v_{o,\mathrm{m}\mathrm{a}\mathrm{x}}\left[n,d_2\right]=V_0{e}^{-k\left(n-1+d_2/2^N\right)}+V_{\mathrm{H}}{\displaystyle \frac{1-e^{-k{d}_2/2^N}}{1-e^{-k}}}\left(1-e^{-kn}\right) \\ +V_{\mathrm{L}}{\displaystyle \frac{e^{-k{d}_2/2^N}-e^{-k}}{1-e^{-k}}}\left(1-e^{-k\left(n-1\right)}\right). \end{gathered}$$

(70)

The stability condition now requires that:

$$v_{o,\mathrm{m}\mathrm{a}\mathrm{x}}\left[n,d_2\right]\le V_{\mathrm{L}}+\left(d_2+{\displaystyle \frac{1}{2}}\right){\displaystyle \frac{V_{\mathrm{H}}-V_{\mathrm{L}}}{2^N}}.$$

(71)

The initial voltage for a given code $d_1$ in this mode is the same as in the rising case and is given by Equation (62).

By solving Equation (71) for $n$, we obtain the expression for the number of periods required for settling time:

$$n\ge 1+{\displaystyle \frac{1}{k}}\mathrm{l}\mathrm{n}{\displaystyle \frac{V_0{e}^{-k{d}_2/2^N}-V_{\mathrm{H}}\frac{1-e^{-k{d}_2/2^N}}{1-e^{-k}}{e}^{-k}-V_{\mathrm{L}}\frac{e^{-k{d}_2/2^N}-e^{-k}}{1-e^{-k}}}{V_{\mathrm{L}}+\left(d_2+\frac{1}{2}\right)\frac{V_{\mathrm{H}}-V_{\mathrm{L}}}{2^N}-V_{\mathrm{H}}\frac{1-e^{-k{d}_2/2^N}}{1-e^{-k}}-V_{\mathrm{L}}\frac{e^{-k{d}_2/2^N}-e^{-k}}{1-e^{-k}}}}.$$

(72)

Substituting Equation (62) for $V_0$, the general expression for the number of periods required for settling time becomes:

$$n\left(d_1,d_2\right)\ge {\displaystyle \frac{1}{k}}\mathrm{l}\mathrm{n}{\displaystyle \frac{\left(e^{k{d}_1/2^N}{e}^{-k{d}_2/2^N}-1\right)}{\left(1-e^{-k}\right)\left(d_2+\frac{1}{2}\right)\frac{1}{2^N}-\left(1-e^{-k{d}_2/2^N}\right)}}.$$

(73)

For the given system parameters ($N=8$, $d_1\in [1, 2^N-1]$, $d_2\in [d_1-1, 0]$, $\epsilon =1/4$, $k={\epsilon /2}^{N-3}=1/2^{N-1}$), the maximum settling time again does not occur at the lower boundary of the code range (i.e., for the smallest $d_2$), as might be intuitively expected. This behavior is illustrated in Figure 22.

Figure 22. Settling interval $n\left(d_1,d_2\right)$ for decreasing transitions $d_1>d_2$, evaluated for $N=8$ and $\epsilon =1/4$. Each curve corresponds to a fixed initial code $d_1$, indicated by the viridis color bar, while the target code $d_2$ varies. Horizontal axis: target code $d_2$; vertical axis: settling interval $n\left(d_1,d_2\right)$ [PWM periods]. As in the rising case, the maximum settling interval occurs at an interior target code rather than at the range boundary.

The expression for the derivative of the number of periods required for settling time with respect to $d_1$ in this case is:

$${\displaystyle \frac{\mathrm{d}n\left(d_1,d_2\right)}{\mathrm{d}{d}_1}}={\displaystyle \frac{1}{2^N}}{\displaystyle \frac{e^{k\left(\frac{d_1-d_2}{2^N}\right)}}{e^{k\left(\frac{d_1-d_2}{2^N}\right)}-1}}.$$

(74)

Since $d_1>d_2$, this derivative is positive, meaning that the maximum settling time occurs for $d_1=2^N-1$. In that case, the number of periods required for settling time is analytically expressed as:

$$n\left(d_1=2^N-1,d_2\right)\ge {\displaystyle \frac{1}{k}}\mathrm{l}\mathrm{n}{\displaystyle \frac{\left(e^{k\left(1-1/2^N\right)}{e}^{-k{d}_2/2^N}-1\right)}{\left(1-e^{-k}\right)\left(d_2+\frac{1}{2}\right)2^{-N}-\left(1-e^{-k{d}_2/2^N}\right)}}.$$

(75)

The goal is to determine the critical value of $d_2$ at which the settling time reaches its maximum. To achieve this, the following condition is applied:

$${\displaystyle \frac{\mathrm{d}n\left(d_1=2^N-1,{ d}_2\right)}{\mathrm{d}{d}_2}}=0.$$

(76)

From this condition, the following equation is obtained:

$$e^{-k\left(1-1/2^N-d_2/2^N\right)}={\displaystyle \frac{k}{2^N}}\left(d_2+{\displaystyle \frac{1}{2}}\right)+1-k{\displaystyle \frac{1-e^{-k\left(1-\frac{1}{2^N}\right)}}{1-e^{-k}}}$$

(77)

Using the following approximations:

• $e^{k{d}_2/2^N}\approx 1+{\displaystyle \frac{k}{2^N}}{d}_2+{\displaystyle \frac{1}{2}}{\left({\displaystyle \frac{k}{2^N}}\right)}^2{d_2}^2$,
• $e^{k\left(1-1/2^N\right)}\approx 1+k\left(1-{\displaystyle \frac{1}{2^N}}\right)$,
• ${\displaystyle \frac{k}{1-e^{-k}}}\approx 1+{\displaystyle \frac{k}{2}}$,

• the expression for the position of the maximum becomes:

$$d_{2,\mathrm{m}\mathrm{a}\mathrm{x}2}=2^N-1-\sqrt{{\displaystyle \frac{2^N}{k}}}\approx 2^N-1-2^{N-1}\sqrt{{\displaystyle \frac{1}{2\epsilon }}}.$$

(78)

Finally, the maximum settling time in this regime, when the output signal decreases, is given by:

$$\begin{gathered} n\left(d_1=2^N-1,d_2=d_{2,\mathrm{m}\mathrm{a}\mathrm{x}2}\right)= \\ {\displaystyle \frac{2^{N-3}}{\epsilon }}\mathrm{l}\mathrm{n}{\displaystyle \frac{e^{\frac{\sqrt{2\epsilon }}{2^{N-1}}}-1}{\left(e^{-\frac{\epsilon }{2^{N-3}}\left(1-\frac{1}{2^N}\right)}{e}^{\frac{\sqrt{2\epsilon }}{2^{N-1}}}-1\right)-\left(e^{-\frac{\epsilon }{2^{N-3}}}-1\right)\left(1-\frac{1}{2}\left(\frac{1}{2^N}+\frac{1}{\sqrt{2\epsilon }}\right)\right)}}. \end{gathered}$$

(79)

Figure 23 shows the dependence of the number of periods required for settling time, $n$, on the number of bits $N$, for three different tolerance values $\epsilon =1/3, 1/4, 1/5$, where $d_1=2^N-1$, $d_2=d_{2,\mathrm{m}\mathrm{a}\mathrm{x}2}\approx 2^N-1-2^{N-1}\sqrt{{\displaystyle \frac{1}{2\epsilon }}}$, and $d_1>d_2.$

Figure 23. Worst-case decreasing-mode settling interval as a function of the number of bits $N$, for $\epsilon =1/3,1/4,$ and $1/5$. The transition is from the highest code $d_1=2^N-1$ to the target code $d_2=d_{2,max2}$, where the decreasing-mode settling interval reaches its maximum. Horizontal axis: number of bits $N$; vertical axis: settling interval [PWM periods]. The trend follows the same resolution and tolerance dependence as the rising case.

Analogous to the rising transition case, in the decreasing code transition regime, Figure 24, Figure 25 and Figure 26 graphically illustrate, respectively: the error of the maximum position, the error of the settling time, and the coincidence of discretized results for the number of periods required for the settling time.

Figure 24. Difference between the exact and approximate positions of the decreasing-mode settling-time maximum, expressed in $\mathrm{LSB}$, as a function of the number of bits $N$, for $\epsilon =1/3,1/4,$ and $1/5$. The small difference confirms the accuracy of the closed-form approximation for the decreasing-mode maximum.

Figure 25. Difference between the approximate and exact continuous, non-rounded decreasing-mode settling intervals at the maximum, expressed in PWM periods, as a function of the number of bits $N$, for $\epsilon =1/3,1/4,$ and $1/5$. The very small difference confirms that approximation has negligible influence before integer rounding.

Figure 26. Difference between the rounded integer decreasing-mode settling counts obtained from the approximate and exact expressions as a function of the number of bits $N$, $\epsilon =1/3,1/4,$ and $1/5$. The difference is given in PWM periods. After rounding to an integer number of PWM periods, the difference is zero for all three tolerance values, so the curves overlap and only the last-drawn green curve ($\epsilon =1/5$) is visible.

The presented results for the decreasing regime confirm the validity of using the approximation for the maximum position $d_{2,\mathrm{m}\mathrm{a}\mathrm{x}2}$ from Equation (78), and consequently, the expression given by Equation (79) for the number of periods required for the settling time in the analysis of the PWM DAC system.

Although the approximations for the number of settling periods in the rising and decreasing regimes, given by Equations (69) and (79), are justified for analyzing PWM DAC behavior, the complexity of these expressions makes it difficult to analytically determine in which regime the maximum number of settling periods is greater. For this reason, a simulation-based comparison of the difference between the number of settling periods in the rising and decreasing regimes is performed, as shown in Figure 27. Figure 28 presents the difference after discretization to an integer number of periods.

Figure 27. Difference between the maximum settling intervals in the decreasing and rising modes, $n_{\downarrow }-n_{\uparrow }$, expressed in PWM periods, as a function of the number of bits $N$, for $\epsilon =1/3,1/4,$ and $1/5$. Here, $\uparrow$ denotes the rising mode ($d_1<d_2$) and $\downarrow$ the decreasing mode ($d_1>d_2$). The non-negative difference shows that the decreasing transition is the more restrictive settling regime.

Figure 28. Difference between the maximum settling intervals in the decreasing and rising modes after rounding to an integer number of PWM periods, expressed in PWM periods, as a function of the number of bits $N$, for $\epsilon =1/3,1/4,$ and $1/5$. Here, $\uparrow$ denotes the rising mode ($d_1<d_2$) and $\downarrow$ the decreasing mode ($d_1>d_2$). The rounded decreasing-mode count exceeds the rising-mode count by at most one PWM period, confirming the decreasing regime as the conservative worst case.

Based on the presented results, the worst-case scenario occurs in the decreasing regime ($d_1>d_2$). Therefore, for the analysis of the PWM DAC system, the maximum number of settling periods should be taken as $n\left(d_1=2^N-1,d_2=d_{2,\mathrm{m}\mathrm{a}\mathrm{x}2}\right)$. It should also be noted that the discretized result $⌈n\left(d_1=2^N-1,d_2=d_{2,\mathrm{m}\mathrm{a}\mathrm{x}2}\right)⌉$ in the worst case is exactly one period greater than the corresponding discretized result for the rising regime $⌈n\left(d_1=0,d_2=d_{2,\mathrm{m}\mathrm{a}\mathrm{x}1}\right)⌉$. Since the expression for $n\left(d_1=0,d_2=d_{2,\mathrm{m}\mathrm{a}\mathrm{x}1}\right)$ is more practical for analytical and implementation purposes than that for $n\left(d_1=2^N-1,d_2=d_{2,\mathrm{m}\mathrm{a}\mathrm{x}2}\right)$, the worst-case number of periods required for settling can be finally expressed as:

$$n_S=⌈n\left(d_1=2^N-1,d_2=d_{2,\mathrm{m}\mathrm{a}\mathrm{x}2}\right)⌉=1+⌈n\left(d_1=0,d_2=d_{2,\mathrm{m}\mathrm{a}\mathrm{x}1}\right)⌉,$$

(80)

or equivalently,

$$n_S=⌈1-{\displaystyle \frac{2^{N-3}}{\epsilon }}\mathrm{l}\mathrm{n}\left(1-{\displaystyle \frac{1}{2}}\left({\displaystyle \frac{1}{\sqrt{2\epsilon }}}-{\displaystyle \frac{1}{2^N}}\right){\displaystyle \frac{e^{\epsilon /2^{N-3}}-1}{e^{\sqrt{2\epsilon }/2^{N-1}}-1}}\right)⌉.$$

(81)

Accordingly, the settling time is defined as:

$$T_S=n·T=n_S·T=⌈1-{\displaystyle \frac{2^{N-3}}{\epsilon }}\mathrm{l}\mathrm{n}\left(1-{\displaystyle \frac{1}{2}}\left({\displaystyle \frac{1}{\sqrt{2\epsilon }}}-{\displaystyle \frac{1}{2^N}}\right){\displaystyle \frac{e^{\epsilon /2^{N-3}}-1}{e^{\sqrt{2\epsilon }/2^{N-1}}-1}}\right)⌉·T.$$

(82)

5. Numerical, LTspice, and Experimental Verification

To verify the analytical expressions derived in Section 4, this section presents numerical examples, LTspice transient simulations, experimental measurements, and a Monte Carlo sensitivity analysis of passive-component tolerances.

First, the boundary (extreme) cases of the output settling time are analyzed for both code transition regimes: $d_1<d_2$, corresponding to the rising output transition, and $d_1>d_2$, corresponding to the decreasing output transition. Both regimes are included to numerically confirm the conclusion from the previous section that the discretized settling-time values satisfy the relation

$$⌈n\left(d_1=0,d_2=d_{2,\mathrm{m}\mathrm{a}\mathrm{x}1}\right)⌉\le ⌈n\left(d_1=2^N-1,d_2=d_{2,\mathrm{m}\mathrm{a}\mathrm{x}2}\right)⌉.$$

The numerical analysis was performed for the number of bits $N\in \left\{6, 8, 10, 12\right\}$ and tolerance $\epsilon \in \left\{1/3, 1/4, 1/5\right\}$. For the subsequent LTspice and experimental verification, the case $N=8$ and $\epsilon =1/4$ was selected as a representative practical configuration. For this specific case, the derived worst-case criterion gives a settling interval of 823 PWM periods.

Based on the derived approximations expressed in Equations (69) and (79), Table 1 presents the discretized number of periods corresponding to the maximum settling time for both rising and decreasing output transition regimes.

Table 1. Discretized number of periods corresponding to the maximum settling time in the rising and decreasing output signal regimes, where $n_{\uparrow }$ corresponds to $d_1<d_2$, and $n_{\downarrow }$ corresponds to $d_1>d_2$).

$\mathit{N}$	$\mathit{\epsilon }$	$⌈\mathit{n}\left(0,{\mathit{d}}_{2,\mathbf{max}1}\right)⌉={\mathit{n}}_{\uparrow }$	$⌈\mathit{n}\left(2^{\mathit{N}}-1,{\mathit{d}}_{2,\mathbf{max}2}\right)⌉={\mathit{n}}_{\downarrow }$
6	1/3	129	129
6	1/4	162	162
6	1/5	197	198
8	1/3	648	649
8	1/4	823	823
8	1/5	1010	1010
10	1/3	3125	3125
10	1/4	4001	4001
10	1/5	4927	4927
12	1/3	14,628	14,628
12	1/4	18,840	18,841
12	1/5	23,255	23,255

The results indicate that the decreasing transition regime is equal to or slightly more restrictive than the rising regime in the considered cases. Therefore, the expression derived for the decreasing transition, given by Equation (82), can be used as a conservative worst-case design criterion for the PWM DAC settling time.

In practical PWM DAC design, the ripple-settling trade-off is commonly evaluated using first-order RC average-response approximations, while the general DAC settling-time literature defines settling with respect to an admissible error band [13,14,15]. This approximation can be interpreted as a simplified limiting case of the time-domain framework presented in this paper.

Namely, if the intra-period output-voltage extrema are neglected and only the average component of the filtered PWM output is considered, the response after a duty-cycle change reduces to the classical first-order RC response. In that case, the transient error decays exponentially with the filter time constant $RC$. For a conservative full-scale transition, the initial deviation of the average output is approximated by the full-scale voltage $V_{\mathrm{fs}}$, while the admissible residual error is represented by the selected ripple limit $v_{\mathrm{ripple}}$. In addition, for a first-order RC-filtered PWM signal with small ripple, the maximum steady-state ripple occurs around $D=1/2$, which leads to the usual small-ripple relationship between $v_{\mathrm{ripple}}$, $T_{\mathrm{PWM}}$, $V_{\mathrm{fs}}$, and $RC$. Combining these assumptions gives the literature-based settling-time estimate used for comparison:

$$t_{\mathrm{settle}}=RC\ln {\displaystyle \frac{V_{\mathrm{fs}}}{v_{\mathrm{ripple}}}}\approx {\displaystyle \frac{T_{\mathrm{PWM}}}{4}}{\displaystyle \frac{V_{\mathrm{fs}}}{v_{\mathrm{ripple}}}}\ln {\displaystyle \frac{V_{\mathrm{fs}}}{v_{\mathrm{ripple}}}},$$

(83)

where $T_{\mathrm{PWM}}$ is the period of the PWM signal, $V_{\mathrm{fs}}$ is the full-scale output voltage, and $v_{\mathrm{ripple}}$ is the allowable ripple limit used in the literature-based settling-time estimate. For the $N$-bit comparison performed in this paper, this limit is selected as $v_{\mathrm{ripple}}=V_{\mathrm{fs}}/2^N$, corresponding to one LSB of the PWM DAC.

Therefore, Equation (83) can be interpreted as a simplified limiting case of the same physical model, obtained when the PWM DAC output is approximated by its average value and the intra-period maximum and minimum values are neglected. This also explains the difference between the literature-based approximation and the criterion derived in this paper. Equation (83) estimates the settling time from the average first-order RC response, whereas the proposed criterion, expressed by Equation (82), requires the output-voltage extrema to enter the target safe zone after the worst-case digital-code transition. Consequently, the proposed criterion is more conservative, but it directly guarantees that the complete PWM DAC output waveform, including its ripple, remains within the admissible code-dependent interval.

For this reason, Table 2 presents a comparison between the discretized settling-time results obtained from the proposed criterion and those obtained from the literature-based approximation, using $N\in \left\{6, 8, 10, 12\right\}$, $\epsilon \in \left\{1/3, 1/4, 1/5\right\}$, $T=T_{\mathrm{PWM}}$, and $v_{\mathrm{ripple}}=V_{\mathrm{fs}}/2^N$.

Table 2. Comparative overview of the discretized settling-time values: analytical result from this paper, $T_S$, versus literature-based result, $t_{\mathrm{settle}}$.

$\mathit{N}$	$\mathit{\epsilon }$	${\mathit{T}}_{\mathit{S}}=⌈\mathit{n}⌉\mathit{T}$	${\mathit{t}}_{\mathbf{settle}}=⌈2^{\mathit{N}}/4\mathbf{ln}{2}^{\mathit{N}}⌉\mathit{T}$	${\mathit{T}}_{\mathit{S}}-{\mathit{t}}_{\mathbf{settle}}$
6	1/3	$129 T$	$67 T$	$62 T$
6	1/4	$162 T$	$67 T$	$95 T$
6	1/5	$198 T$	$67 T$	$131 T$
8	1/3	$649 T$	$355 T$	$294 T$
8	1/4	$823 T$	$355 T$	$468 T$
8	1/5	$1010 T$	$355 T$	$655 T$
10	1/3	$3125 T$	$1775 T$	$1350 T$
10	1/4	$4001 T$	$1775 T$	$2226 T$
10	1/5	$4927 T$	$1775 T$	$3152 T$
12	1/3	$\mathrm{14,628} T$	$8518 T$	$6110 T$
12	1/4	$\mathrm{18,841} T$	$8518 T$	$\mathrm{10,323} T$
12	1/5	$\mathrm{23,255} T$	$8518 T$	$\mathrm{14,737} T$

Compared with the literature-based expression, the proposed criterion gives a more conservative settling-time estimate. This is expected because the derived expression accounts for the worst-case code transition and requires the ripple extrema, rather than only the average output value, to enter the target safe zone. Therefore, satisfying the proposed worst-case criterion guarantees that the settling requirement is fulfilled for all less critical code transitions.

More specifically, the difference between the two estimates should not be interpreted as a disagreement with the literature-based approach, but as a consequence of the different design assumptions used in the two criteria. The literature-based expression is useful as a compact average-value first-order RC settling estimate for preliminary design. Its lower settling-time values result from the fact that the filtered PWM output is represented by its average component, the intra-period ripple extrema are neglected, the code-dependent safe-zone boundaries are not explicitly enforced, and the worst-case digital-code transition is not separately imposed. In contrast, the proposed criterion evaluates a stricter requirement: the complete ripple envelope must enter and remain inside the target safe zone. The larger values in Table 2 therefore reflect the difference between an average-value settling estimate and a conservative ripple-envelope settling criterion.

5.1. LTspice Verification

To verify the derived analytical criterion at the circuit level, transient simulations were performed in LTspice (version 26.0.2, Analog Devices) [16] using a first-order passive RC filter driven by an ideal PWM voltage source. The verification was carried out for $N=8$ and $\epsilon =1/4$, for which the analytical worst-case settling-time criterion gives

$$T_S=823 T.$$

The PWM frequency was set to $f_{\mathrm{PWM}}=10 \mathrm{kHz}$, corresponding to $T=100 \mathsf{\mu }\mathrm{s}$. The nominal filter values were selected as $R=12.8 \mathrm{k}\mathsf{\Omega }$ and $C=1 \mathsf{\mu }\mathrm{F}$, resulting in

$$RC=12.8 \mathrm{ms},k=T/RC=1/128.$$

The selected nominal value $k=1/128$ corresponds to the worst-case design point $k_{\min }=\epsilon /2^{N-3}$ for $N=8$ and $\epsilon =1/4$, ensuring that the analytical and simulated conditions are aligned at the boundary of the safe operating zone. The practical experimental implementation uses measured component values close to this nominal design point, as discussed in Section 5.2.

The voltage levels were $V_L=0 \mathrm{V}$ and $V_H=3.3 \mathrm{V}$.

Three steady-state ripple cases were simulated for the digital codes $d=64$, $d=128$, and $d=192$. In addition, two transient code transitions were simulated: the rising worst-case transition $d_1=0\to d_2=181$, and the decreasing worst-case transition $d_1=255\to d_2=74$. These transitions correspond to the analytically identified critical cases for the selected values of $N$ and $\epsilon$.

The simulated steady-state ripple values are shown in Table 3. The maximum ripple occurs for $d=128$, corresponding to a duty cycle of 50%, as expected for a first-order filtered PWM signal. The analytical peak-to-peak ripple values shown in Table 3 are computed as the difference between the steady-state maximum and minimum output voltages given by Equations (4) and (5).

Table 3. LTspice steady-state ripple verification for $N=8$, $\epsilon =1/4$, $f_{\mathrm{PWM}}=10 \mathrm{kHz}$, $R=12.8 \mathrm{k}\mathsf{\Omega }$, and $C=1 \mathsf{\mu }\mathrm{F}$.

Code $\mathit{d}$	Duty Cycle	LTspice ${\mathit{V}}_{\mathbf{min}}$	LTspice ${\mathit{V}}_{\mathbf{max}}$	LTspice Ripple pp	Analytical Ripple pp	Average Value
64	25%	0.82262 V	0.82745 V	4.834 mV	4.834 mV	0.825 V
128	50%	1.64681 V	1.65326 V	6.445 mV	6.445 mV	1.650 V
192	75%	2.47261 V	2.47745 V	4.834 mV	4.834 mV	2.475 V

The LTspice transient simulations reproduce the analytical ripple values within the numerical precision shown in Table 3. As expected for a first-order PWM-filtered output, the ripple amplitude is maximized at $D=1/2$ and is symmetric around this point, taking equal values for $D=1/4$ and $D=3/4$. This symmetry follows directly from the substitution $D\to 1-D$ in the ripple expression, under which the formula is invariant.

These ripple values are also consistent with the complementary steady-state harmonic interpretation introduced in Section Steady-State Harmonic Interpretation. For the parameters used in Table 3, the normalized filter parameter is $k=T/RC=0.0078125$. This value corresponds to the selected design case $N=8$ and $\epsilon =1/4$ used in the ripple verification. For $d=128$, corresponding to $D=1/2$, the even harmonic components vanish because $\sin \left(\pi mD\right)$ is zero for even harmonic orders. The residual ripple is therefore formed by the odd PWM harmonic components attenuated by the RC response.

Using the harmonic expression from Section Steady-State Harmonic Interpretation with $k=0.0078125$, the magnitudes of the first three nonzero complex Fourier coefficients are approximately $\left|C_1\right|=1.306$ mV, $\left|C_3\right|=0.145$ mV, and $\left|C_5\right|=0.052$ mV. Since $C_m$ denotes the complex Fourier coefficient, the corresponding one-sided peak amplitudes are $2\left|C_m\right|$. Together with their phase shifts and the higher odd harmonic components, these terms reconstruct the steady-state filtered PWM waveform whose peak-to-peak ripple is reported in Table 3. This confirms that the time-domain ripple values obtained from the output-voltage extrema and the frequency-domain interpretation based on attenuated PWM harmonic components are mutually consistent.

The LTspice transient simulations also confirmed the analytically predicted settling interval. For the rising transition $d_1=0\to d_2=181$, the output enters the target safe zone within the predicted discrete settling interval around $T_S=823 T$. Similarly, for the decreasing transition $d_1=255\to d_2=74$, the simulated maximum value of the output ripple reaches the upper boundary of the target zone within approximately one PWM period of the analytical prediction. This agreement confirms that the derived expressions provide a valid conservative criterion for the worst-case settling time.

5.2. Experimental Verification

An experimental prototype was implemented in order to validate the predicted behavior using a microcontroller-based PWM generator and a passive RC filter. The PWM signal was generated using an Arch Pro development board (Seeed Studio, Shenzhen, China), an mbed-enabled prototyping board based on the NXP LPC1768 microcontroller [17]. The board was configured to produce an 8-bit PWM signal at $f_{\mathrm{PWM}}=10 \mathrm{kHz}$. The output of the PWM pin was applied to a first-order RC filter, and the filtered voltage was measured using a Siglent SDS1104X-U digital oscilloscope (Siglent Technologies, Shenzhen, China).

The nominal design values used for the analytical and LTspice verification were $R=12.8 \mathrm{k}\mathsf{\Omega }$ and $C=1 \mathsf{\mu }\mathrm{F}$, corresponding to the normalized filter parameter $k=T/RC=0.0078125$.

In the experimental prototype, the measured component values were

$$R=12.97 \mathrm{k}\mathsf{\Omega },C=955 \mathrm{nF},$$

resulting in an experimental time constant

$$RC\approx 12.39 \mathrm{ms}.$$

The corresponding experimental normalized filter parameter is therefore

$$k={\displaystyle \frac{T}{RC}}={\displaystyle \frac{100 \mathsf{\mu }\mathrm{s}}{12.39 \mathrm{ms}}}\approx 0.00807.$$

This value is close to the nominal design value, but it is not identical. Therefore, both the nominal analytical ripple and the analytical ripple recalculated with the measured RC value are shown in Table 4.

Table 4. Experimental steady-state ripple measurements and component-tolerance sensitivity using the Arch Pro PWM generator and the passive RC filter.

Code $\mathit{d}$	Duty Cycle	Analytical Ripple pp, Nominal RC	Analytical Ripple pp, Measured RC	Measured Ripple pp	Measured Mean Voltage
64	25%	4.834 mV	4.995 mV	6.04 mV	0.85 V
128	50%	6.445 mV	6.661 mV	7.88 mV	1.66 V
192	75%	4.834 mV	4.995 mV	5.80 mV	2.49 V

For the ripple measurements, the values were extracted from the steady-state part of the filtered PWM waveform, after the transient response had decayed. The peak-to-peak ripple was evaluated on the low-frequency RC-filtered envelope, while isolated switching spikes and high-frequency disturbances were not treated as representative ripple values, since they are mainly related to practical parasitic effects and are not included in the analytical model of the ideal first-order RC filter.

The steady-state ripple was measured for three digital codes: $d=64$, $d=128$, and $d=192$. The measured mean output voltages were consistent with the expected duty-cycle-dependent average values. The measured ripple amplitudes and mean output voltages are shown in Table 4.

The measured mean output voltages follow the expected duty-cycle-dependent average-value trend of the PWM DAC. The measured peak-to-peak ripple values are systematically larger than the ideal analytical predictions. However, Table 4 shows that the measured component values explain only a small part of this increase. When the measured $R$ and $C$ values are used in the analytical ripple expression, the predicted ripple increases from 4.834 mV to 4.995 mV for $D=1/4$ and $D=3/4$, and from 6.445 mV to 6.661 mV for $D=1/2$.

The remaining difference between the measured ripple and the analytical prediction based on the measured RC value is approximately 1.04 mV for $D=1/4$, 1.22 mV for $D=1/2$, and 0.80 mV for $D=3/4$. This indicates that the increased ripple cannot be attributed only to the measured component tolerances. The additional ripple contribution is mainly associated with practical non-idealities that are not included in the ideal first-order RC model, including finite rise and fall times of the microcontroller PWM output stage, switching transients and ground bounce on the development board, oscilloscope quantization noise and probe loading, and parasitic capacitance and inductance of the breadboard wiring.

Despite these additional contributions, the qualitative duty-cycle dependence of the ripple is preserved: the maximum ripple occurs at $D=1/2$, while the ripple values at $D=1/4$ and $D=3/4$ are smaller and approximately symmetric, in agreement with both the analytical prediction and the LTspice results.

Figure 29 shows the measured steady-state output ripple for the selected PWM codes.

Figure 29. Measured steady-state output ripple of the experimental PWM DAC for the selected codes $d=64$, $d=128$, and $d=192$, with $N=8$. The traces are vertically offset for clarity. Horizontal axis: time [μs]; vertical axis: AC-coupled output voltage [mV, offset]. The peak-to-peak ripple is largest for $d=128$, corresponding to a 50% duty cycle, and smaller and approximately symmetric for $d=64$ and $d=192$, in agreement with the analytical and LTspice results.

The transient response was also measured for the two critical code transitions used in the LTspice verification: $d_1=0\to d_2=181$ and $d_1=255\to d_2=74$. A separate GPIO signal was generated by the microcontroller and used as the oscilloscope trigger, marking the instant at which the PWM duty cycle was changed. The recorded waveforms show the expected exponential charging and discharging behavior of the first-order RC filter.

Figure 30 shows the measured rising transition for $d_1=0\to d_2=181$. The output voltage increases from the initial low-level state toward the target average value corresponding to the new digital code.

Figure 30. Experimental rising transition of the PWM DAC output for the worst-case code change $d_1=0\to d_2=181$. The measured output increases from the initial low-level state toward the new target average value. The trigger signal generated by the microcontroller marks the instant of the PWM duty-cycle change. Horizontal axis: time [ms] relative to the trigger; vertical axis: output voltage [V].

Figure 31 shows the measured decreasing transition for $d_1=255\to d_2=74$. The output voltage decreases from the initial high-level state toward the target average value corresponding to the new digital code.

Figure 31. Experimental decreasing transition of the PWM DAC output for the worst-case code change $d_1=255\to d_2=74$. The measured output decreases from the initial high-level state toward the new target average value. The trigger signal generated by the microcontroller marks the instant of the PWM duty-cycle change. Horizontal axis: time [ms] relative to the trigger; vertical axis: output voltage [V].

The experimental transient waveforms are consistent with the analytical prediction and the LTspice transient simulations. Due to the millivolt-level ripple, measurement noise, switching transients, and practical wiring parasitics, the experimental measurements were used to confirm the transient trend and the practical feasibility of the derived design criterion, while the exact safe-zone crossing was verified by the analytical and LTspice results.

The numerical, LTspice, and experimental results consistently confirm the main conclusions of the analytical derivation. The proposed criterion predicts a conservative worst-case settling interval, while the steady-state ripple behavior follows the expected duty-cycle dependence. The experimental measurements further demonstrate that the derived design rules can be applied to a practical microcontroller-based PWM DAC implementation with a passive first-order RC filter despite component tolerances, measurement noise, switching transients, and wiring parasitics.

5.3. Monte Carlo Sensitivity Analysis

As an additional check of the influence of passive-component tolerances, a simple Monte Carlo sensitivity analysis was performed for the representative design case $N=8$, $\epsilon =1/4$, $f_{\mathrm{PWM}}=10 \mathrm{kHz}$, $T_{\mathrm{PWM}}=1/f_{\mathrm{PWM}}$, $R=12.8 \mathrm{k}\mathsf{\Omega }$, and $C=1 \mathsf{\mu }\mathrm{F}$. The resistance and capacitance were treated as independent, uniformly distributed random variables within $R\pm 5\%$ and $C\pm 20\%$, which are typical tolerances for low-cost passive components.

A total of 1000 random ($R$, $C$) realizations were generated. For each realization, the normalized filter parameter was recalculated as

$$k_i={\displaystyle \frac{T_{\mathrm{PWM}}}{R_i{C}_i}},i=1, 2, \dots , 1000.$$

The corresponding worst-case settling interval and the steady-state peak-to-peak ripple at $D=1/2$ were then evaluated using the analytical expressions derived in the paper. The settling interval was calculated from the rising and decreasing transition expressions (Equations (63) and (73)), and the worst-case value was taken as the larger of the two, rounded up to an integer number of PWM periods. In Table 5, these two contributions are denoted $n_{\mathrm{RIS}}$ and $n_{\mathrm{DEC}}$, respectively, so that $n_S=⌈\max (n_{\mathrm{RIS}}, n_{\mathrm{DEC}})⌉$. The ripple was calculated from the steady-state maximum and minimum output values (Equations (4) and (5)).

Table 5. Monte Carlo sensitivity analysis for $N=8$, $\epsilon =1/4$, $R\pm 5\%$, $C\pm 20\%$, and 1000 random realizations.

Parameter	Nominal/Reference Value	Mean Value	Minimum Value	Maximum Value	Note
$k=T_{\mathrm{PWM}}/\left(RC\right)$	0.0078125	0.0079116	0.0062497	0.0102380	$k_{\min }\approx 1/128=0.0078125$
Worst-case settling interval $n_S$ [PWM periods]	823	825.2	652	1008	$n_S=⌈\max (n_{\mathrm{RIS}}, n_{\mathrm{DEC}})⌉$
Ripple at $D=1/2$ [mV]	6.445	6.527	5.156	8.446	Peak-to-peak steady-state ripple

The tolerance $\epsilon$ was kept fixed at $\epsilon =1/4$, because it represents the selected safe-zone accuracy requirement rather than a random component tolerance. For this value of $\epsilon$ and $N=8$, the corresponding safe-zone boundary value is $k_{min}\approx 1/128=0.0078125$. In each Monte Carlo run, the actual value $k_i=T_{\mathrm{PWM}}/\left(R_i{C}_i\right)$ was compared with this boundary condition.

Table 5 summarizes the obtained results. The statistical spread shows that resistor and capacitor tolerances directly affect the value of the parameter $k$, and therefore both the settling interval and the output ripple.

In the nominal case, the value of parameter $k$ was intentionally selected at the safe-zone boundary ($k_{\min }$), in order to verify the limiting condition derived in the analysis. The Monte Carlo results show that random tolerances of $R$ and $C$ move the actual value $k_i=T_{\mathrm{PWM}}/\left(R_i{C}_i\right)$ both below and above this boundary. This does not change the analytical criterion, but illustrates that practical component tolerances should be considered when selecting the nominal $RC$ value. In practical designs, the nominal value of $k$, or equivalently the nominal $RC$ product, should therefore be chosen with sufficient margin so that the admissible safe-zone condition remains satisfied under the expected worst-case component tolerances.

6. Conclusions

This work extends the time-domain analysis of a PWM DAC structure employing a first-order passive RC filter. Exact analytical expressions have been derived for both digital-code transition modes, the rising mode ($d_1<d_2$) and the decreasing mode ($d_1>d_2$), and it has been demonstrated that the worst-case condition occurs in the decreasing regime. For practical design purposes, the expression derived for this regime directly provides the number of PWM periods required for settling as a function of the resolution $N$, tolerance $\epsilon$, and the parameter $k$.

Numerical and graphical evaluations confirm that the approximations for the positions of the critical points are well aligned with the exact analytical solutions, with small errors that decrease as the number of bits $N$ increases. The comparison with the standard first-order RC settling estimate from the literature shows that the proposed approach, which considers the worst-case code transition and ripple extrema, provides a more conservative and consistent estimation of the settling time.

The proposed criterion was further verified using LTspice simulations and practical measurements. For the representative case $N=8$, $\epsilon =1/4$, and $f_{\mathrm{PWM}}=10 \mathrm{kHz}$, the analytical criterion predicts a settling interval of 823 PWM periods. The LTspice results confirm the safe-zone crossing within approximately one PWM period of the analytical prediction, while the experimental measurements obtained using an Arch Pro PWM generator and a passive RC filter confirm the expected steady-state ripple behavior and transient charging/discharging trends.

In addition, a Monte Carlo sensitivity analysis confirmed that resistor and capacitor tolerances affect the normalized parameter $k=T/\left(RC\right)$, and therefore both the settling interval and the output ripple, which should be considered when selecting nominal $R$ and $C$ values in practical low-cost implementations.

It is important to emphasize that the obtained results are analytically exact within the adopted model. However, the calculated settling time can become very large for high resolutions and tight tolerances. Such values may be impractical in certain applications, indicating the need for alternative architectures or different filtering strategies when a faster response is required, especially in high-resolution or real-time applications. Therefore, this work provides a conservative time-domain worst-case analysis of the PWM DAC settling time, clearly quantifying the trade-off between the number of bits $N$, tolerance $\epsilon$, and dynamic response speed (i.e., parameter $k$).

The analytical framework presented in this paper therefore establishes a foundation for accurate and predictable time-domain design of PWM DAC systems across a wide range of practical applications. It clearly quantifies the trade-off between the number of bits $N$, tolerance $\epsilon$, ripple amplitude, and dynamic response speed, and provides a conservative criterion suitable for robust parameter selection under practical component tolerances and measurement uncertainty.

Future work will be directed toward PWM DAC architectures employing higher-order and/or active filters, as well as alternative ripple-reduction techniques aimed at reducing the settling time while preserving the required accuracy. Additional experimental work may also investigate the influence of non-ideal PWM output stages, probe loading, and parasitic effects in compact embedded implementations.