Thermal Nonuniformity-Aware Reliability Screening for Systolic AI Accelerators

Abstract

AI accelerators increasingly operate under tight power, thermal, voltage, and timing margins, making workload-dependent thermal nonuniformity an important reliability concern. In systolic AI accelerators, localized activity concentration can create spatially uneven thermal stress, but thermal or timing-exposure analysis alone does not determine whether such stress remains benign, becomes numerically masked, or propagates into silent corruption. This paper presents a cross-layer early-stage screening methodology for thermal nonuniformity-aware reliability analysis in systolic arrays. The framework links workload-aware activity extraction, relative power concentration modeling, diffusion-based thermal proxy analysis, an explicit thermal-to-timing stress abstraction, path class-aware corruption modeling, and clean/masked/silent outcome classification. The revised framework is formalized mathematically and evaluated across dense, low-dynamic-range, and sparse GEMM workloads under weight-stationary and output-stationary execution. To strengthen statistical and methodological confidence, the study includes 100-seed corruption reruns with Wilson confidence intervals, thermal scaling across $8\times 8$, $16\times 16$, and $32\times 32$ arrays, calibration sensitivity, path weight sensitivity, component ablations, and preliminary compact thermal reference alignment. The results show that sparse workloads consistently produce the largest thermal spread across tested array sizes, while dense and low-dynamic-range workloads remain more spatially uniform. Under the default calibrated screening regime at $16\times 16$, sparse output-stationary and sparse weight-stationary cases reach 49% and 40% silent corruption rates, respectively, while dense cases remain mostly clean or masked and low-dynamic-range cases remain largely clean. Sensitivity and ablation experiments show that the sparse workload risk is not caused by one isolated modeling component, although the masked/silent split depends on path class weighting and thermal diffusion assumptions. The main contribution is not signoff-accurate silicon failure prediction, but a reproducible screening front end for identifying workload, dataflow, and path class combinations that deserve deeper thermal, timing, RTL-level, and application-level validation.

1. Introduction

AI accelerators are increasingly designed under tight energy, thermal, voltage, and timing constraints. Systolic arrays are central to this trend because they provide dense, regular, and energy-efficient execution of matrix-intensive workloads [1,2,3]. Their repeated processing elements, local communication patterns, and high utilization make them attractive for inference and training. At the same time, these same structural properties can generate spatially concentrated activity and localized thermal stress inside the compute fabric when workload activity becomes uneven [4,5].

Thermal hotspots are commonly discussed in terms of power density, cooling demand, throttling, and timing degradation. However, timing degradation alone does not fully answer the system-level correctness question. A local thermal hotspot may remain benign, may produce an internal perturbation that is numerically masked, or may propagate into silent corruption without an explicit failure indication. The gap between thermal stress, local timing exposure, and end-to-end correctness is therefore central to understanding reliability risk in systolic AI accelerators operating under tight design margins.

This issue becomes especially important in advanced node and low-voltage designs, where thermal stress interacts with supply sensitivity and timing margin more strongly than in older processes. Elevated local temperature can increase circuit delay and worsen effective timing conditions, especially when combined with IR drop or voltage margin sensitivity [6]. Persistent local stress can also interact with aging mechanisms such as NBTI [7]. Yet, many hotspot-aware analyses stop at power, temperature, slack degradation, or violating path exposure. Such metrics are useful, but they do not indicate whether workload-driven thermal nonuniformity becomes a visible correctness problem during execution.

In this work, thermal stress is not modeled as a direct source of bit flips. Rather, it is treated as a local contributor to timing margin reduction. Reduced timing margin then increases the probability that a path class-specific operation produces an erroneous value. This interpretation is important because heat does not directly corrupt numerical values in the proposed model. Instead, the model abstracts the physical pathway from local temperature to stress, from stress to reduced timing margin, and from reduced timing margin to a timing-induced computational perturbation.

This paper presents a cross-layer screening methodology for systolic AI accelerators. The framework begins with workload-aware activity extraction and power proxy generation, uses these maps to construct diffusion-based thermal proxies, then introduces a path class-aware corruption model that distinguishes MAC, accumulator, and forwarding roles. The resulting execution is classified as clean, masked, or silent corruption. The purpose is not to replace implementation-grade thermal signoff, static timing analysis, RTL power estimation, or RTL fault injection. Instead, the goal is to provide an early-stage screening front end that identifies which workload and dataflow conditions are most likely to deserve deeper validation.

The central result is that correctness risk in systolic arrays is shaped not only by local thermal magnitude, but by the interaction of workload-driven spatial nonuniformity, dataflow organization, timing stress thresholding, and path class-sensitive corruption behavior. Sparse workloads produce the strongest thermal spread across the tested array sizes, while dense and low-dynamic-range workloads remain more uniform. Under a calibrated path-aware corruption regime, sparse workloads show substantially higher silent corruption susceptibility than dense or low-dynamic-range workloads. The revised analysis also shows that this trend persists under multiple sensitivity and ablation checks, although the absolute rate and masked/silent split depend on model settings.

The main contributions of this work are:

• A cross-layer screening framework that links workload-driven activity, relative power concentration, thermal nonuniformity, timing margin stress, path class vulnerability, and end-to-end corruption outcomes in systolic arrays.
• A mathematical formulation of the activity, power, thermal, stress, timing margin, and path class corruption stages, enabling a more reproducible early-stage methodology.
• A path class taxonomy for systolic array datapaths that distinguishes MAC, accumulator, forwarding, and control/update roles, with MAC, accumulator, and forwarding paths activated in the current corruption model.
• A statistical corruption analysis using 100 random seeds per condition, with Wilson confidence intervals for silent corruption outcomes.
• A scaling and sensitivity evaluation including $8\times 8$, $16\times 16$, and $32\times 32$ thermal comparisons, calibration sensitivity, path weight sensitivity, component ablations, and preliminary compact thermal reference alignment.
• A design exploration perspective in which hotspot-aware screening serves as a triage layer for identifying workload, dataflow, and path class combinations that should be prioritized for deeper thermal, timing, RTL-level, and application-level validation.

2. Related Work

2.1. Systolic Array-Based AI Acceleration

Systolic arrays are a widely adopted substrate for matrix-intensive AI workloads because they provide dense, regular, and energy-efficient execution. Their architectural importance is well established in both classic and modern accelerator literature, including the original systolic architecture concept [1], TPU-class fabrics [2], dataflow-oriented architectures such as Eyeriss [3], and open accelerator generators such as Gemmini [8]. These works primarily emphasize throughput, reuse efficiency, architectural organization, and system integration. They provide the architectural substrate for this study, but they do not directly address how workload-driven thermal nonuniformity can interact with path-sensitive corruption behavior.

2.2. Thermal Modeling and Hotspot Analysis

Architectural hotspot analysis has long been studied through compact thermal models such as HotSpot and temperature-aware microarchitecture work [4,5,9]. These studies established the importance of spatial temperature concentration for design evaluation. More recent thermal analysis and model order reduction approaches have improved the efficiency and fidelity of hotspot prediction for integrated systems [10,11]. Pre-RTL and RTL-level power and thermal optimization methods also address thermal and power constraints earlier in the design process [12].

These approaches are important references for thermal modeling, but their primary outputs are temperature, power, or thermal management indicators. They do not usually propagate workload-induced hotspot maps into clean, masked, and silent correctness outcomes. The present work therefore uses a lighter thermal proxy for early-stage screening and explicitly positions implementation-grade thermal modeling as a necessary follow-up validation step.

2.3. Reliability Assessment in DNN Accelerators

Recent work has expanded the study of DNN accelerator reliability through systematic surveys, analytical assessment, hierarchical fault injection, and architecture-aware reliability frameworks [13,14,15,16,17]. This literature shows that fault impact depends strongly on where faults occur and how values propagate through the accelerator. However, many such studies treat faults as externally specified events rather than as consequences of workload-dependent spatial thermal stress.

The present work complements DNN accelerator fault injection studies by using workload- and dataflow-dependent thermal maps as the spatial driver for path class-aware corruption injection. The goal is not to replace detailed RTL-level or application-level fault injection, but to help determine which conditions should be prioritized for such validation.

2.4. Runtime Detection and System-Level Protection

Runtime detection and system-level mitigation of hardware-induced corruption are increasingly important in practical DNN systems [18,19,20,21]. These works demonstrate the broader relevance of correctness-aware reliability and silent data corruption. However, runtime protection systems are usually designed for deployed systems and are not primarily intended as early-stage design space screening tools for workload- and dataflow-induced hotspot behavior.

2.5. Comparison with Prior Thermal and Reliability Analysis Approaches

Prior work has addressed several parts of the problem studied in this paper, including systolic array acceleration, compact thermal modeling, DNN accelerator reliability, and runtime protection against silent data corruption. However, these lines of work usually focus on one layer of the problem at a time. Thermal models identify spatial temperature behavior but typically do not determine whether hotspots remain benign, become numerically masked, or propagate into silent corruption. Fault injection and DNN reliability studies evaluate corruption behavior but often do not model workload-driven thermal concentration as the initiating stressor. Runtime detection systems identify or mitigate hardware-induced corruption, but they are generally not intended as early-stage design space screening tools for dataflow- and workload-induced hotspot behavior.

The present work is positioned between these approaches (Table 1). It does not replace implementation-grade thermal analysis, RTL power estimation, STA, or application-level fault injection. Instead, it provides a lightweight screening layer that connects workload structure, dataflow organization, thermal nonuniformity, path class vulnerability, and clean/masked/silent corruption outcomes within one reproducible framework.

Table 1. Comparison to prior thermal, reliability, and protection approaches.

Approach/Representative Work	Primary Focus	Thermal-Aware	Workload/  Dataflow-Aware	Path Class-Aware	End-to-End Outcomes	Role Relative to This Work
Systolic array accelerator studies [2,3,8]	Architecture, throughput, reuse, energy efficiency	Limited	Yes	No	Usually no	Defines accelerator substrate and dataflow context
HotSpot and compact thermal modeling [4,5]	Architecture-level thermal estimation	Yes	Possible through power maps	No	No	Provides thermal reference methodology; this work uses a lighter screening proxy
Temperature-aware microarchitecture [9]	Thermal and performance management	Yes	Sometimes	No	Usually no	Establishes thermal concentration as a design concern
RTL or pre-RTL power/thermal optimization [12]	Power, voltage, thermal design optimization	Yes	Yes	Usually no	Usually no	More implementation-grounded but less focused on silent corruption propagation
DNN accelerator fault-injection studies [14,15,16,17]	Fault impact and DNN robustness	Usually limited	Yes	Sometimes	Yes	Evaluates reliability effects, but typically not driven by workload-induced hotspot maps
System-level SDC protection [18,19,20,21]	Detecting or mitigating hardware-induced corruption	Not central	Application-dependent	Limited	Yes	Protects deployed systems; this work screens design-time hotspot risk conditions
This work	Early-stage hotspot-to-corruption screening	Yes, via proxy thermal map	Yes	Yes	Yes: clean, masked, silent	Bridges workload-driven thermal nonuniformity to path-sensitive correctness risk

The distinction of the proposed framework is therefore not that it provides a more accurate thermal model than HotSpot-class tools, nor that it replaces RTL-level fault injection. Rather, its contribution is the integration of workload-driven thermal nonuniformity with path class-sensitive corruption outcomes at a level suitable for early design exploration. This enables the framework to answer a different question: which workload and dataflow conditions should be prioritized for deeper thermal, timing, and application-level validation?

3. Cross-Layer Screening Methodology

3.1. Overview of the Screening Flow

This work uses a cross-layer framework that connects workload-driven execution behavior to end-to-end corruption outcomes in systolic arrays. The framework has five stages: workload-aware activity extraction, power proxy generation, thermal proxy modeling, path class-aware vulnerability modeling, and corruption evaluation. The goal is not to provide signoff-accurate silicon prediction, but to capture the chain by which localized thermal stress can become masked or silent corruption during computation.

The screening flow (in Figure 1) operates as a computational pipeline rather than as a manual classification procedure. For each workload and dataflow configuration, the framework constructs a spatial activity map over the systolic array, converts this map into a normalized power concentration proxy, applies a compact diffusion-based thermal model, maps local thermal stress to a timing margin proxy, and then converts margin stress into path class-specific corruption probabilities. Corruption events are injected during GEMM execution and classified according to output behavior.

Figure 1. Cross-layer thermal reliability screening flow. Workload structure and dataflow determine spatial activity. Activity is converted into relative power and thermal concentration. Thermal concentration is mapped to timing margin stress and path class-aware corruption probabilities. End-to-end execution is then classified into clean, masked, and silent outcomes.

3.2. Mathematical Formulation of the Screening Framework

Consider an $N\times N$ systolic array indexed by processing element coordinates $(i,j)$, where $1\le i,j\le N$. For workload w and dataflow d, the activity score of processing element $(i,j)$ is modeled as

$$A_{i,j}^{(w,d)}=\alpha C_{i,j}^{(w,d)}+\beta R_{i,j}^{(w,d)}+\gamma F_{i,j}^{(w,d)},$$

(1)

where $C_{i,j}^{(w,d)}$ denotes local computation activity, $R_{i,j}^{(w,d)}$ denotes residency-related activity, and $F_{i,j}^{(w,d)}$ denotes forwarding or relay burden. The coefficients $\alpha$, $\beta$, and $\gamma$ control the relative contribution of arithmetic work, local value retention, and operand movement. In the present screening study, these terms are normalized before combination so that the resulting map reflects relative spatial activity rather than absolute switching power.

The normalized power concentration proxy is defined as

$$P_{i,j}^{(w,d)}={\displaystyle \frac{A_{i,j}^{(w,d)}}{{max}_{m,n}{A}_{m,n}^{(w,d)}+ϵ}},$$

(2)

where $ϵ$ is a small numerical constant used to avoid division by zero. The resulting $P_{i,j}^{(w,d)}$ values lie in the interval $[0,1]$ and should be interpreted as relative power concentration indicators. They are not intended to replace RTL power estimation or signoff power analysis.

The thermal proxy is generated using an iterative steady-state diffusion update. Let $T_{i,j}^{\left(k\right)}$ denote the temperature proxy at tile $(i,j)$ after iteration k. The update rule is

$$T_{i,j}^{(k+1)}=T_{\mathrm{amb}}+\lambda P_{i,j}^{(w,d)}+\eta \left({\displaystyle \frac{1}{|{\mathcal{N}}_{i,j}|}}\sum _{(m,n)\in {\mathcal{N}}_{i,j}}{T}_{m,n}^{\left(k\right)}-T_{\mathrm{amb}}\right),$$

(3)

where $T_{\mathrm{amb}}$ is the ambient baseline temperature, $\lambda$ controls local heat injection from the power proxy, $\eta$ controls lateral thermal diffusion, and ${\mathcal{N}}_{i,j}$ is the set of neighboring tiles. Boundary tiles use the available in-array neighbors only. The iteration is repeated until the maximum temperature change between iterations falls below a fixed convergence threshold or until a maximum number of iterations is reached.

The resulting temperature map is used to compute a local thermal stress term,

$$S_{i,j}=max\left(0,T_{i,j}-T_{\mathrm{ref}}\right),$$

(4)

where $T_{\mathrm{ref}}$ is a reference temperature below which no additional stress-induced timing degradation is assumed.

To make the timing interpretation explicit, the local timing margin proxy is written as

$$M_{i,j}=M_0-\kappa S_{i,j},$$

(5)

where $M_0$ is the nominal timing margin and $\kappa$ is a temperature-to-margin sensitivity coefficient. Corruption probability increases as the effective margin decreases. For path class c, the corruption probability at tile $(i,j)$ is modeled as

$$p_{i,j,c}=p_{max}·w_c·\sigma \left({\displaystyle \frac{S_{i,j}-S_{\mathrm{th}}}{\tau }}\right),$$

(6)

where $p_{max}$ is the maximum base corruption probability under the calibrated screening condition, $w_c$ is the relative vulnerability weight of path class c, $S_{\mathrm{th}}$ is the stress threshold, $\tau$ controls the smoothness of the transition from low-risk to high-risk behavior, and $\sigma (·)$ is the logistic function,

$$\sigma \left(x\right)={\displaystyle \frac{1}{1+exp(-x)}}.$$

(7)

This formulation separates three distinct concepts: the spatial distribution of activity, the resulting thermal nonuniformity, and the path class-dependent probability that reduced timing margin leads to a computational perturbation. The model therefore does not assume that heat directly flips bits. Rather, heat is treated as a local stressor that degrades timing margin, and path class-specific corruption is used as an abstract representation of timing-sensitive computation under reduced margin.

When corruption is injected, the perturbed value is modeled as

$$x^{\prime }=x+{∆}_c,$$

(8)

where x is the unperturbed intermediate value and ${∆}_c$ is a path class-dependent perturbation term.

The parameters in this formulation are not intended to represent final silicon-calibrated failure probabilities. They define a controlled screening regime for comparing workload and dataflow conditions under consistent stress assumptions. The primary goal is therefore not absolute prediction of field failure rates, but relative identification of configurations that generate stronger spatial thermal nonuniformity and greater path-sensitive corruption susceptibility.

3.3. Thermal Stress, Timing Margin, and Corruption Abstraction

The proposed model does not assume that elevated temperature directly flips bits or corrupts numerical values. Instead, temperature is treated as an indirect reliability stressor that affects circuit delay and timing margin. In CMOS logic, increased local temperature can reduce carrier mobility, increase propagation delay, and interact with supply and IR drop sensitivity. Under tight voltage and timing margins, this delay increase can reduce the available slack of timing-sensitive paths. If the effective delay approaches or exceeds the clock period constraint, a value may be captured incorrectly or may arrive too late to be used reliably.

The screening model abstracts this physical pathway as

$$T_{i,j}\to S_{i,j}\to M_{i,j}\to p_{i,j,c}\to {∆}_c.$$

(9)

Here, $T_{i,j}$ is the local thermal proxy, $S_{i,j}$ is the thresholded thermal stress, $M_{i,j}$ is the local timing margin proxy, $p_{i,j,c}$ is the path class-specific probability of a timing-induced perturbation, and ${∆}_c$ is the resulting numerical perturbation applied during systolic execution.

This abstraction is intentionally simplified. It does not replace STA, circuit simulation, or voltage drop-aware timing analysis. Its purpose is to preserve the causal structure needed for early-stage screening: local thermal concentration reduces timing margin, and reduced timing margin increases the probability that a path class-specific operation produces an erroneous value. The corruption event in the model should therefore be interpreted as a timing-induced computational perturbation, not as a direct thermal bit flip.

The path class dependence is important because different datapath roles translate timing errors into computation differently. A MAC-path perturbation affects local arithmetic generation. An accumulator perturbation can persist across repeated partial-sum updates. A forwarding perturbation can propagate an incorrect operand to downstream processing elements. Thus, the same local thermal stress can have different correctness consequences depending on which functional path is exposed.

3.4. Workload-Aware Activity Extraction

The first stage estimates how workload structure and dataflow organization distribute activity across the systolic array. For each workload, tile-level activity is approximated using a combination of computation activity, residency cost, and relay burden. Computation activity reflects the intensity of multiply–accumulate behavior associated with each spatial region. Residency cost captures the tendency of certain dataflows to retain values longer in particular array locations. Relay burden captures the additional spatial overhead caused by operand movement and local reuse.

To avoid unrealistically uniform activity, the activity model is value-aware. Dense, low-dynamic-range, and sparse workloads are treated differently, and sparse execution allows zero-heavy structure to suppress portions of the activity map. This produces workload-dependent nonuniformity rather than a flat average utilization pattern.

Dataflow further modulates the spatial profile. Under output-stationary execution, output accumulation and local reuse create stronger residency concentration in selected regions. Under weight-stationary execution, activity is more distributed, although forwarding burden can still create asymmetric spatial patterns. The result of this stage is a workload- and dataflow-specific activity map that serves as the basis for the power model.

3.5. Power and Thermal Proxy Modeling

The second stage converts activity into a spatial power proxy. The power model combines computation activity, residency-related cost, and relay-related cost using weighted contributions. The objective is to represent relative spatial stress rather than absolute circuit-level power. Accordingly, the generated power maps are normalized and interpreted as workload-driven power concentration patterns.

The third stage converts normalized power maps into thermal proxy maps. A compact steady-state diffusion model is used in place of a full implementation-level thermal signoff flow. Each tile receives a local temperature that depends on both its own power proxy and the influence of neighboring tiles through iterative diffusion. The model therefore produces smooth, spatially coherent thermal patterns rather than isolated single-tile peaks.

The thermal proxy is used to preserve relative spatial stress structure across workloads and dataflows, not to claim final implementation-level temperature prediction. The main object of interest is relative spatial concentration rather than absolute temperature calibration. The resulting thermal maps are therefore intended as structured workload-driven stress fields that support comparative reliability analysis during design exploration.

3.6. Path Classes in the Systolic Tile

To move beyond generic timing exposure, the framework introduces path classes that represent distinct functional roles in the systolic array datapath. The current path taxonomy is defined using a synthesizable processing element and a small two-by-two systolic tile. Four path classes are identified: PC1 MAC datapath, PC2 accumulator update path, PC3 forwarding path, and PC4 control/update logic.

Among these, PC1, PC2, and PC3 are used directly in the current corruption model. PC4 is included in the taxonomy but reserved for future extension because its failure semantics differ from numerical datapath perturbations.

The vulnerability levels in Table 2 are modeling settings rather than measured STA-derived quantities. They encode the hypothesis that accumulator perturbations are more persistent, MAC perturbations directly affect arithmetic generation, and forwarding perturbations can propagate spatially. The experiments therefore include a uniform path weight sensitivity analysis to evaluate how much of the observed behavior depends on these provisional weights.

Table 2. Path class taxonomy and role in the current screening model.

Path Class	Logic Role	Corruption Interpretation	Status in Current Model	Vulnerability Setting
PC1	MAC datapath	Local arithmetic perturbation during product generation	Active	Provisional high
PC2	Accumulator update	Persistent drift across repeated partial-sum updates	Active	Provisional very high
PC3	Forwarding path	Propagation of corrupted operands to downstream PEs	Active	Provisional moderate
PC4	Control/update logic	Stale update, skipped update, or validity/control fault	Defined but inactive	Future work

The control/update class PC4 is defined but not activated in the present corruption experiments. This is because control faults require different semantics from datapath perturbations. A MAC, accumulator, or forwarding perturbation can be represented as a numerical modification of an intermediate value. In contrast, a control/update perturbation may skip an operation, repeat a stale value, corrupt a valid signal, or alter the timing of data movement. Modeling such behavior requires state machine-level or RTL-level injection and is therefore reserved for future extension.

3.7. Corruption Injection and Outcome Classification

During systolic array GEMM execution, multiply–accumulate operations, accumulator updates, and forwarding behavior can each be perturbed according to their class-specific vulnerability and the local thermal stress of the responsible tile. The outcome of each run is classified as clean, masked, or silent corruption.

Clean means that no meaningful output corruption is observed. Masked means that internal perturbations occur, but the final result remains within tolerance of the golden output. Silent corruption means that the final output deviates from the golden output without any explicit failure indication. In addition to the outcome class, the framework records relative output error, maximum absolute error, and path class-specific injection counts.

4. Experimental Setup

The experiments evaluate how workload structure, dataflow organization, thermal nonuniformity, and path class-aware vulnerability interact in systolic array computation. The setup is intentionally positioned as a controlled early-stage screening study rather than as implementation-grade signoff. All workload and corruption conditions are therefore evaluated under the same normalized modeling assumptions so that relative trends across workloads, dataflows, and array sizes can be compared.

4.1. Array Configurations

The study uses square systolic arrays of size $N\times N$, with $N\in \{8,16,32\}$. The $16\times 16$ array is used as the primary corruption evaluation configuration because it provides sufficient spatial structure for hotspot formation while keeping the 100-seed corruption experiments computationally tractable. The $8\times 8$ and $32\times 32$ configurations are used to evaluate whether thermal nonuniformity trends persist across scale.

Each processing element is modeled as a tile containing a MAC datapath, accumulator update logic, forwarding paths for operands, and local control/update logic. The active corruption model uses the MAC, accumulator, and forwarding classes. The control/update class is included in the taxonomy but is not activated in the current injection experiments.

4.2. Workload Definitions

Three GEMM workload classes are evaluated: dense, low dynamic range, and sparse. For each workload, the systolic array computes

$$C=AB,$$

(10)

where A, B, and C are matrix operands compatible with the selected array size and tiling configuration.

For the primary $16\times 16$ experiments, the GEMM dimensions are set to $M=K=L=256$, so that the computation contains enough tiled reuse to expose spatial activity differences. For the $8\times 8$ and $32\times 32$ scale experiments, the matrix dimensions are kept fixed unless otherwise stated, allowing the effect of array organization to be separated from changes in total workload size.

Dense workloads use operands sampled from a zero-mean bounded distribution and contain no explicitly inserted sparsity. Low-dynamic-range workloads use operands sampled from a narrower bounded interval than the dense case. Sparse workloads use the same base operand distribution as the dense case, followed by structured sparsity injection. A fixed sparsity ratio s is applied by setting a fraction s of operand entries to zero. Unless otherwise stated, the main sparse experiments use $s=0.70$.

The sparse workload is not intended to represent a specific compressed sparse accelerator implementation. Instead, it provides a controlled stress case for evaluating how nonuniform activity interacts with thermal concentration and path-sensitive corruption.

4.3. Dataflow Configurations

Two dataflows are evaluated: weight-stationary and output-stationary. In the weight-stationary configuration, weights remain resident in local processing elements for repeated use, while activations and partial sums move through the array. This tends to distribute accumulation behavior more broadly across the fabric, although forwarding burden can still produce asymmetric spatial stress.

In the output-stationary configuration, partial sums remain resident for repeated accumulation. This increases local residency and repeated accumulator activity in selected spatial regions. Because the model explicitly accounts for residency and accumulator behavior, output-stationary execution is expected to produce stronger spatial concentration in some cases. The experiments therefore focus not only on whether this qualitative trend appears, but also on its magnitude, persistence across workloads, and interaction with path class-aware corruption.

4.4. Activity, Power, and Thermal Parameters

For each workload and dataflow condition, the activity map is computed from computation activity, residency cost, and relay burden according to the formulation in Section 1. The default activity weights are

$$\alpha =1.0,\beta =0.5,\gamma =0.25.$$

(11)

The thermal proxy uses the following default parameters:

$$T_{\mathrm{amb}}=75 °\mathrm{C},\lambda =10 °\mathrm{C},\eta =0.35.$$

(12)

Here, $T_{\mathrm{amb}}$ is the baseline ambient or package-level reference temperature, $\lambda$ controls local heat injection from the normalized power proxy, and $\eta$ controls lateral thermal diffusion between neighboring processing elements. Boundary tiles use only their available in-array neighbors. The diffusion update is iterated until convergence or for a fixed maximum of 500 iterations.

The reported thermal metrics are peak temperature, mean temperature, thermal spread, and temperature standard deviation:

$$T_{\mathrm{peak}}=\underset{i,j}{max}{T}_{i,j},$$

(13)

$$T_{\mathrm{mean}}={\displaystyle \frac{1}{N^2}}\sum _{i,j}{T}_{i,j},$$

(14)

$$T_{\mathrm{spread}}=T_{\mathrm{peak}}-T_{\min },$$

(15)

$$T_{\mathrm{std}}=\sqrt{{\displaystyle \frac{1}{N^2}}\sum _{i,j}{\left(T_{i,j}-T_{\mathrm{mean}}\right)}^2}.$$

(16)

The analysis emphasizes thermal spread and spatial nonuniformity rather than peak temperature alone because the main reliability concern is localized stress concentration across the array.

4.5. Thermal-to-Timing Stress Calibration

The thermal stress term is computed relative to a reference temperature,

$$S_{i,j}=max(0,T_{i,j}-T_{\mathrm{ref}}),$$

(17)

with

$$T_{\mathrm{ref}}=80 °\mathrm{C}.$$

(18)

This choice creates a controlled screening regime in which only locally elevated tiles contribute to stress-induced vulnerability.

4.6. Path Class Vulnerability Parameters

The active path classes are PC1 MAC datapath, PC2 accumulator update, and PC3 forwarding path. The default relative vulnerability weights are

$$w_{\mathrm{MAC}}=0.75,w_{\mathrm{ACC}}=1.00,w_{\mathrm{FWD}}=0.50.$$

(19)

Thes weights are provisional and are not claimed to be final STA-derived sensitivities.

The default stress-to-corruption parameters are

$$p_{max}=0.05,S_{\mathrm{th}}=2 °\mathrm{C},\tau =1 °\mathrm{C}.$$

(20)

These values define the calibrated screening condition. They are selected to produce a nontrivial but not saturated corruption regime, allowing clean, masked, and silent outcomes to be distinguished.

4.7. Corruption Injection and Outcome Classification

During systolic GEMM execution, corruption events are sampled according to the local tile stress and path class probability. If an event is triggered, the corresponding intermediate value is perturbed according to Equation (8). The perturbation scale is path class dependent and increases with local stress:

$${∆}_c\sim \mathcal{U}\left(-{\rho }_c\left|x\right|·\varphi \left(S_{i,j}\right),{\rho }_c\left|x\right|·\varphi \left(S_{i,j}\right)\right),$$

(21)

where ${\rho }_c$ is the base perturbation scale for path class c, and $\varphi \left(S_{i,j}\right)$ is a normalized stress multiplier. The default perturbation scales are

$${\rho }_{\mathrm{MAC}}=0.01,{\rho }_{\mathrm{ACC}}=0.02,{\rho }_{\mathrm{FWD}}=0.01.$$

(22)

The output matrix is compared with a golden, unperturbed GEMM result. The default relative output error is

$$E_{\mathrm{rel}}={\displaystyle \frac{\parallel C_{\mathrm{faulty}}-C_{\mathrm{golden}}{\parallel }_F}{\parallel C_{\mathrm{golden}}{\parallel }_F+ ϵ}}.$$

(23)

A run is classified as silent corruption if

$$E_{\mathrm{rel}}>{ϵ}_{\mathrm{out}},$$

(24)

where

$${ϵ}_{\mathrm{out}}={10}^{-3}.$$

(25)

The maximum absolute error is also reported:

$$E_{max}=\underset{i,j}{max}\left|C_{\mathrm{faulty},i,j}-C_{\mathrm{golden},i,j}\right|.$$

(26)

4.8. Random Seeds and Statistical Reporting

Each workload, dataflow, and array size condition is evaluated across multiple random seeds. The primary $16\times 16$ corruption experiments use 100 random seeds per condition. The thermal maps are deterministic for a fixed workload seed, while corruption outcomes vary according to both the workload instance and sampled corruption events.

For each condition, the manuscript reports clean rate, masked fault rate, silent corruption rate, relative error, maximum absolute error, and path class-specific injected fault counts where applicable. For binary outcome rates such as silent corruption, 95% confidence intervals are computed using the Wilson binomial interval.

4.9. Sensitivity, Ablation, and Reference Alignment

To separate model assumptions from emergent behavior, three additional experiment groups are included. First, a calibration sensitivity analysis varies the stress-to-probability parameters. Second, a path weight sensitivity analysis compares default path class weights with uniform path weights. Third, a component ablation study removes or modifies individual components of the screening framework. The ablated variants include the full model, local-only thermal modeling, no relay term, no residency term, and uniform path class weights.

A preliminary compact thermal reference alignment is also included. This alignment does not establish signoff accuracy. It evaluates whether the proposed proxy preserves broad hotspot structure and high-risk tile ranking relative to a compact reference-style thermal model using the same normalized power maps.

4.10. Scope of the Experimental Setup

The experimental setup supports relative screening claims rather than absolute hardware-failure prediction. The thermal model is a compact proxy and does not replace HotSpot-class or implementation-grade thermal analysis. The path class vulnerability weights are provisional and do not replace STA-derived timing sensitivity. The workload set is synthetic and GEMM-centered, rather than a full CNN, Transformer, or recommendation model benchmark suite.

5. Validation, Scaling, and Sensitivity Results

The original screening results were extended with additional experiments designed to test statistical stability, array size dependence, parameter sensitivity, model component dependence, and preliminary thermal reference alignment. These experiments address whether the observed trends depend on a single calibrated setting or whether they persist across model variations.

5.1. Statistical Corruption Outcomes Across 100 Seeds

Each workload/dataflow condition was rerun across 100 random seeds at $16\times 16$. Table 3 reports clean, masked, and silent corruption rates, together with Wilson 95% confidence intervals for silent corruption.

Table 3. Path-aware corruption outcomes at $16\times 16$ across 100 seeds.

Dataflow	Workload	Clean	Masked	Silent	95% CI for Silent
OS	Dense	59%	39%	2%	0.6–7.0%
OS	Low-DR	97%	3%	0%	0–3.7%
OS	Sparse	9%	42%	49%	39.4–58.7%
WS	Dense	64%	35%	1%	0.2–5.4%
WS	Low-DR	98%	2%	0%	0–3.7%
WS	Sparse	14%	46%	40%	30.9–49.8%

The 100-seed rerun (in Figure 2) preserves the main qualitative finding while making it statistically more stable. Dense workloads remain mostly clean or masked, and low-dynamic-range workloads remain largely clean. Sparse workloads are markedly different: sparse output-stationary execution reaches 49% silent corruption, while sparse weight-stationary execution reaches 40% silent corruption. The confidence intervals show that the sparse workload silent corruption rates are clearly separated from the dense and low-dynamic-range cases.

Figure 2. Clean, masked, and silent outcomes at $16\times 16$ across 100 seeds. Dense workloads remain mostly clean or masked, low-dynamic-range workloads remain largely clean, and sparse workloads show substantially higher silent corruption susceptibility.

5.2. Thermal Scaling Across Array Sizes

To test whether the thermal nonuniformity trend is specific to the $16\times 16$ configuration, the thermal stage was repeated for $8\times 8$, $16\times 16$, and $32\times 32$ arrays. Table 4 summarizes mean peak temperature and mean thermal spread.

Table 4. Thermal scaling across array sizes.

Array	Dataflow	Workload	Peak Temp. Mean	Thermal Spread Mean
$8\times 8$	OS	Dense	82.48	2.35
$8\times 8$	OS	Low-DR	82.49	2.26
$8\times 8$	OS	Sparse	81.65	4.40
$8\times 8$	WS	Dense	82.50	2.18
$8\times 8$	WS	Low-DR	82.51	2.07
$8\times 8$	WS	Sparse	81.69	4.40
$16\times 16$	OS	Dense	82.62	3.04
$16\times 16$	OS	Low-DR	82.62	2.90
$16\times 16$	OS	Sparse	82.30	5.26
$16\times 16$	WS	Dense	82.62	2.72
$16\times 16$	WS	Low-DR	82.62	2.56
$16\times 16$	WS	Sparse	82.26	5.13
$32\times 32$	OS	Dense	82.67	3.04
$32\times 32$	OS	Low-DR	82.67	2.92
$32\times 32$	OS	Sparse	82.55	5.61
$32\times 32$	WS	Dense	82.67	2.82
$32\times 32$	WS	Low-DR	82.67	2.67
$32\times 32$	WS	Sparse	82.56	5.51

The scaling experiment shows that the relative thermal ordering trend persists across the tested array sizes. Sparse workloads produce the largest thermal spread at every size, while dense and low-dynamic-range workloads remain more uniform. Output-stationary execution generally produces slightly stronger thermal spread than weight-stationary execution, especially in dense and low-dynamic-range cases.

The dominant effect is spatial nonuniformity rather than peak temperature increase. Peak temperatures remain in a narrow range, while thermal spread varies more strongly across workload classes (Figure 3). Thus, workload structure primarily redistributes thermal stress rather than making the entire array uniformly hotter.

Figure 3. Thermal spread across array sizes. Sparse workloads consistently produce the largest thermal spread across $8\times 8$, $16\times 16$, and $32\times 32$ arrays. Bar height reports spatial spread rather than peak temperature.

5.3. Calibration Sensitivity

The stress-to-corruption mapping was evaluated under weak, default, and strong stress regimes to determine whether the results depend on a single calibrated setting (Table 5).

Table 5. Silent corruption sensitivity to stress calibration.

Regime	OS Dense	OS Low-DR	OS Sparse	WS Dense	WS Low-DR	WS Sparse
Weak	0%	0%	0%	0%	0%	0%
Default	2%	0%	49%	1%	0%	40%
Strong	15%	1%	99%	15%	1%	98%

Absolute silent corruption rates increase as the stress regime becomes stronger, as expected. However, sparse workloads remain the most sensitive class across the sweep. Under the weak regime, the model produces no silent corruption, indicating that the framework is not forced to generate failures. Under the default regime, sparse workloads separate clearly from dense and low-dynamic-range workloads. Under the strong regime, sparse workloads nearly saturate, while dense workloads show moderate silent corruption and low-dynamic-range workloads remain comparatively stable.

This sensitivity analysis clarifies the meaning of the calibrated stress condition. It is not a tuned single point used to force one desired outcome; rather, it is the middle point of a broader stress-response sweep (Figure 4).

Figure 4. Silent corruption sensitivity across weak, default, and strong stress regimes. Sparse workloads remain the most sensitive class across the stress sweep.

5.4. Path Weight Sensitivity

Because the default model assigns the highest provisional vulnerability to accumulator paths, a uniform path weight experiment was added. In this variant, MAC, accumulator, and forwarding paths receive equal vulnerability weights (Table 6).

Table 6. Effect of path class weighting on corruption outcomes.

Model	Dataflow	Workload	Clean	Masked	Silent
Default weights	OS	Dense	59%	39%	2%
Default weights	OS	Sparse	9%	42%	49%
Uniform weights	OS	Dense	42%	54%	4%
Uniform weights	OS	Sparse	2%	27%	71%
Default weights	WS	Dense	64%	35%	1%
Default weights	WS	Sparse	14%	46%	40%
Uniform weights	WS	Dense	48%	51%	1%
Uniform weights	WS	Sparse	8%	30%	62%

Sparse workloads remain substantially more vulnerable than dense workloads even when the accumulator is not given special priority. Therefore, the sparse workload result is not solely an artifact of the accumulator weight assumption. At the same time, changing the path weights changes the masked/silent split and total severity of outcomes, supporting the claim that path class modeling affects the structure of corruption behavior (Figure 5).

Figure 5. Path weight sensitivity. Sparse workloads remain substantially more vulnerable than dense workloads under both default and uniform path class weighting, indicating that the sparse workload trend is not solely an artifact of the accumulator weight assumption.

5.5. Component Ablation Study

A component ablation study was conducted to evaluate how residency, relay burden, lateral diffusion, and path class weighting affect the results (Table 7).

Table 7. Ablation summary for representative sparse and dense cases.

Variant	OS Dense Silent	OS Sparse Silent	WS Dense Silent	WS Sparse Silent	Main Interpretation
Full model	2%	49%	1%	40%	Reference screening flow
Local-only thermal	0%	39%	0%	33%	Removing diffusion reduces stress propagation and lowers silent rates
No relay	2%	50%	1%	41%	Relay term has modest effect in this configuration
No residency	4%	49%	1%	40%	Residency affects spread but does not eliminate sparse-risk trend
Uniform path weights	4%	71%	1%	62%	Path weights alter severity and masked/silent balance

The ablation study supports the interpretation that sparse workload risk is not caused by one isolated modeling component. Sparse workloads remain more vulnerable than dense workloads across all ablated variants. However, the magnitude of the effect changes across variants, showing that the framework is sensitive to model structure. Removing lateral diffusion reduces silent corruption rates, while uniform path weights increase sparse silent corruption rates in this parameterization (Figure 6).

Figure 6. Component ablation study for representative dense and sparse cases. Sparse workloads remain more vulnerable than dense workloads across ablated variants, while the absolute silent corruption rate depends on thermal diffusion and path weight assumptions.

5.6. Preliminary Thermal Reference Alignment

The diffusion-based proxy was compared with a compact reference-style thermal model using the same normalized power maps. This comparison is not intended to establish signoff accuracy. Instead, it evaluates whether the proposed proxy preserves broad hotspot structure and high-risk tile ranking (Table 8).

Table 8. Thermal proxy/reference alignment.

Workload	Dataflow	Map Correlation	Top-10% Hotspot Overlap
Dense	OS	0.91	0.70
Dense	WS	0.90	0.66
Sparse	OS	0.69	0.53
Sparse	WS	0.69	0.52

The alignment is strongest for dense workloads, where the proxy and reference maps show high correlation and substantial top-hotspot overlap. Sparse workloads show weaker alignment, with correlations around 0.69 and top-10% overlap around 0.52–0.53 (Figure 7). This narrows the claim: the proxy is useful for early-stage screening and broad trend identification, while sparse cases require more careful validation with implementation-grade thermal tools.

Figure 7. Preliminary thermal proxy/reference alignment. The proxy shows stronger alignment for dense workloads and weaker alignment for sparse workloads, supporting its use as an early-stage screening front end rather than a substitute for implementation-grade thermal validation.

This preliminary alignment also supports the role of the proposed method as a triage front end rather than a substitute for thermal signoff. The proxy is sufficient to identify broad stress patterns and prioritize higher-risk conditions, but it should be followed by HotSpot-class or implementation-grade validation for final design decisions.

6. Interpretation and Discussion

6.1. Assumption-Driven and Emergent Components of the Results

A useful interpretation of the proposed framework requires separating behavior intentionally encoded in the model from behavior emerging from interactions among model components. Sparse workloads are explicitly modeled as producing spatially uneven activity. Output-stationary execution is explicitly modeled as increasing local residency and repeated accumulation. Accumulator paths are assigned the highest provisional vulnerability because accumulator perturbations can persist across repeated updates.

However, the main contribution of the results is not the isolated observation that sparsity, output-stationary execution, or accumulator sensitivity can increase reliability risk. Rather, the contribution is the quantified interaction among these factors. The model does not directly prescribe the magnitude of thermal spread across workload and dataflow combinations, the clean/masked/silent split, the relative sensitivity of dense versus sparse cases to calibration changes, or the effect of removing residency, relay, diffusion, or path weighting in ablation studies.

The sparse workload results illustrate this distinction. Sparse workloads intentionally create nonuniform activity, but sparse activity does not automatically imply silent corruption. Silent corruption appears when spatial thermal concentration aligns with thresholded timing stress, path class-sensitive perturbation, and output-level tolerance. The 100-seed results, calibration sweep, path weight sensitivity, and ablation study show that sparse workloads remain the dominant high-risk class across several controlled variants.

6.2. Thermal Nonuniformity Rather than Uniform Heating

The thermal results should be interpreted in terms of spatial nonuniformity rather than peak temperature alone. Across the scaling experiments, peak temperatures remain in a relatively narrow interval, while thermal spread changes substantially across workload and dataflow conditions. Sparse workloads consistently produce the largest thermal spread, even though their peak temperatures are not necessarily the highest.

This distinction matters for reliability screening. A similar peak temperature can correspond to different spatial stress patterns. A relatively uniform thermal map exposes many tiles to similar moderate stress, whereas a highly nonuniform map concentrates stress in a smaller subset of tiles. Under a thresholded timing stress model, this localization can be more consequential than the peak value alone because it determines which tiles cross the stress threshold and which path classes are repeatedly exposed.

Therefore, workload-driven thermal concentration should not be described as making the entire fabric hotter. The more precise interpretation is that workload and dataflow structure make the fabric more spatially uneven, thereby increasing localized timing stress exposure.

6.3. Why Sparse Workloads Remain High Risk

Sparse workloads show the strongest thermal spread and the strongest corruption susceptibility because sparsity redistributes activity rather than simply reducing total work uniformly. Some regions become inactive or lightly used, while others continue to carry computation, residency, or relay burden. This creates sharper spatial gradients and concentrates timing stress in fewer processing elements.

Once thermal stress is coupled with path class-aware corruption, sparse workloads are less likely to average out perturbations evenly across the computation. This explains why sparse workloads show a higher silent corruption rate than dense workloads under default stress, remain most sensitive under the calibration sweep, and remain more vulnerable across ablated model variants.

6.4. Role of Path Class Modeling

The path class sensitivity experiments show that the sparse workload trend is not solely caused by assigning the highest vulnerability to accumulator paths. Sparse workloads remain more vulnerable than dense workloads even under uniform path weights. However, the shift in masked and silent outcomes under uniform weighting shows that path class modeling still matters.

This supports the intended role of the path-aware model. It does not merely increase or decrease total fault probability. Rather, it changes how local thermal stress is translated into computational perturbation. MAC perturbations affect arithmetic generation, accumulator perturbations can persist across repeated updates, and forwarding perturbations can propagate corrupted operands downstream. Separating these mechanisms gives a more informative view than a single generic stress-to-fault probability.

6.5. Implications for Design Exploration

The practical value of the framework is design space triage. It is not intended to decide whether a final chip is safe. Instead, it helps determine where expensive validation effort should be focused. A workload/dataflow condition that produces strong spatial thermal nonuniformity, crosses the timing stress threshold in localized regions, and aligns with accumulator or forwarding paths is a stronger candidate for HotSpot-based thermal analysis, STA, RTL fault injection, and application-level robustness testing than a condition that remains thermally uniform and produces only masked perturbations.

This reframes hotspot-aware reliability as more than a thermal management problem. Dataflow selection, operand reuse strategy, and workload placement can influence not only performance and energy efficiency, but also spatial correctness risk. A design that appears acceptable under average thermal assumptions may still exhibit correctness-sensitive hotspot behavior under particular workloads or execution styles.

7. Design Implications for Systolic AI Accelerators

The results suggest that hotspot-aware reliability in systolic arrays should be treated as a design and operation problem rather than only a thermal management problem. Dataflow selection, operand reuse strategy, and workload placement can all change the shape of thermal concentration and therefore the exposure of vulnerable path classes.

The thermal scaling results show that sparse workloads consistently produce larger thermal spread across the tested array sizes. This implies that sparsity-aware scheduling and mapping decisions may be reliability-relevant. Sparse execution is often viewed primarily as an efficiency opportunity because it reduces unnecessary computation. However, if sparsity produces uneven activity, it can create localized stress concentration even when total work is reduced. Reliability-aware sparse scheduling may therefore need to consider not only the amount of work removed but also where the remaining work is concentrated.

The path class results suggest that accumulator and forwarding behavior deserve particular attention in early-stage reliability screening. Accumulator perturbations are potentially important because partial sums persist across repeated updates. Forwarding perturbations are potentially important because operand movement can spread corruption to downstream processing elements. Even when final path weights must eventually be calibrated through STA and RTL-level injection, distinguishing these roles is more informative than treating all local stress as equivalent.

The calibration and ablation results also suggest that early-stage screening should not rely on a single parameter setting. A workload/dataflow condition that appears risky across multiple stress regimes and ablated model variants is more likely to deserve deeper validation. Conversely, a condition that remains clean or masked across such checks may be a lower priority for expensive implementation-grade analysis.

In practical terms, the framework can be used as a front-end triage tool in the design flow. It can identify workload/dataflow combinations that produce strong spatial thermal nonuniformity, highlight the processing elements that repeatedly cross stress thresholds, and indicate whether those regions align with path classes that are likely to affect end-to-end correctness. These conditions can then be passed to HotSpot-class thermal analysis, detailed floorplanning, voltage drop-aware timing analysis, STA, RTL fault injection, and application-level robustness testing.

8. Limitations and Scope

This study should be interpreted as an early-stage cross-layer screening methodology rather than a final signoff-accurate prediction of silicon failure. The framework is designed to identify workload, dataflow, and path class combinations that deserve deeper implementation-grade validation. Several limitations therefore define the intended scope of the present work.

First, the thermal stage uses a compact diffusion-based proxy rather than an implementation-grade thermal solver. The proxy is intended to preserve relative spatial concentration and hotspot ranking across workload and dataflow conditions, not to predict absolute silicon temperature. In particular, the reported temperatures should be interpreted as calibrated screening values rather than package-accurate thermal predictions. Full validation would require HotSpot-class thermal modeling, detailed package assumptions, floorplanning, tile-level power density, and boundary condition calibration.

Second, the path class vulnerability weights are provisional. The MAC, accumulator, and forwarding classes are derived from the functional structure of the systolic tile, but their numerical vulnerability weights are not yet extracted from static timing analysis or RTL-level fault injection. The present model therefore evaluates a structured hypothesis: accumulator perturbations are more persistent, MAC perturbations directly affect arithmetic generation, and forwarding perturbations can propagate spatially. The uniform path weight sensitivity analysis is intended to test how strongly the reported trends depend on these provisional assumptions.

Third, the thermal-to-corruption pathway is simplified. Temperature is not treated as directly flipping bits. Instead, the model represents a causal abstraction in which local thermal stress reduces timing margin and increases the probability of timing-induced computational perturbation. This captures the direction of the physical mechanism but does not replace STA, voltage drop aware timing analysis, transistor-level simulation, or silicon-calibrated delay modeling.

Fourth, the workload set is intentionally controlled and GEMM-centered. Dense, low-dynamic-range, and sparse GEMM workloads are useful for isolating the effects of activity distribution, dataflow, and sparsity, but they do not cover the full diversity of CNN, Transformer, or recommendation model execution. The present conclusions should therefore be read as mechanism-level trends for systolic GEMM-style computation rather than as universal claims about all AI accelerator workloads.

Fifth, the array size evaluation remains limited relative to production-scale accelerators. The revised manuscript includes $8\times 8$, $16\times 16$, and $32\times 32$ comparisons to test whether thermal ordering trends persist beyond a single configuration. However, this is not equivalent to evaluating very large deployed accelerator fabrics. Larger arrays may introduce additional thermal coupling, floorplanning, clocking, and power delivery effects that require implementation-grade modeling.

Sixth, the current corruption model focuses on datapath perturbations. PC4 control/update logic is included in the path taxonomy but is not activated in the present injection model. This is because control faults require different semantics from numerical datapath perturbations. A control/update fault may skip an operation, repeat a stale value, corrupt a valid signal, or alter data movement. Modeling these effects requires state machine-level or RTL-level injection and is reserved for future extension.

Finally, the application-level interpretation is preliminary. The current framework classifies matrix-level outcomes as clean, masked, or silent corruption. A complete application-level study would require full CNN, Transformer, or recommendation model inference benchmarks and task-level metrics such as accuracy, calibration, ranking quality, or loss degradation.

These limitations do not change the central contribution of the work. Rather, they define the role of the proposed method: a reproducible screening front end that narrows the design space and identifies which workload, dataflow, and path class combinations should be prioritized for deeper thermal, timing, and application-level validation.

9. Conclusions

This paper presented a cross-layer screening methodology for studying how workload-driven thermal nonuniformity can contribute to path-sensitive correctness risk in systolic AI accelerators. The framework links workload-aware activity extraction, relative power concentration, diffusion-based thermal proxy modeling, thermal-to-timing stress abstraction, path class-aware vulnerability modeling, and clean/masked/silent corruption outcomes.

The main contribution is not a signoff-accurate prediction of silicon failure. Rather, the contribution is a reproducible early-stage screening flow that identifies workload, dataflow, and path class combinations that are more likely to require deeper validation. This distinction is important because thermal concentration alone does not determine correctness risk. Localized stress becomes reliability-relevant when it overlaps with timing-sensitive and functionally consequential datapath roles such as accumulation, arithmetic generation, or operand forwarding.

The results show that workload and dataflow jointly shape spatial thermal nonuniformity. Sparse workloads consistently produce the strongest thermal spread across the tested array sizes, while dense and low-dynamic-range workloads remain more spatially uniform. Importantly, this effect should be interpreted primarily as increased spatial unevenness rather than as a uniformly hotter array since peak temperature may remain similar while thermal spread changes substantially. Under the proposed path-aware corruption model, dense workloads remain mostly clean or masked, whereas sparse workloads exhibit stronger susceptibility to silent corruption, especially when localized stress aligns with accumulator or forwarding behavior.

The revised framework also clarifies the physical interpretation of the model. Temperature is not treated as a direct source of bit flips. Instead, local thermal stress is modeled as a contributor to reduced timing margin, which increases the probability of timing-induced computational perturbation. This abstraction allows the methodology to connect thermal nonuniformity with correctness outcomes while remaining explicit about the need for later STA, voltage drop aware timing analysis, RTL-level fault injection, and application-level validation.

Overall, the proposed method is best understood as a design space triage tool. It helps identify which workload/dataflow/path class combinations deserve expensive implementation-grade analysis. Future work should therefore focus on calibrating the path class weights with STA and RTL fault injection, aligning the thermal proxy with HotSpot-class or implementation-grade thermal models, extending the workload set to CNN, Transformer, and recommendation model kernels, activating the PC4 control/update path class, and evaluating task-level application metrics such as accuracy, confidence, calibration, or loss degradation.

By connecting workload-induced spatial stress to path-sensitive correctness outcomes, the proposed framework provides an early warning layer for reliability-aware systolic array design under tight thermal, voltage, and timing margins.