A Low-Power 68.4 dB Signal-to-Noise-and-Distortion Ratio Noise-Shaping SAR ADC for Biomedical Applications

Abstract

This paper introduces a novel analog-to-digital converter (ADC) employing a passive noise-shaping (NS) technique combined with a chopper-stabilized comparator, enhancing performance and reducing ripple factor while maintaining low power consumption. The NS architecture is built on a cascade-integrator feedforward (CIFF) structure, using both infinite- and finite-impulse response filters to minimize quantization and kT/C noise. Additionally, it employs a low-power two-stage chopper amplifier to compensate for the offset voltage and enhance system stability. Validated according to the 180 nm CMOS process, the proposed ADC has an effective number of bits of 10.6, a signal-to-noise-and-distortion ratio of 68.4 dB, and a signal-to-noise ratio of 59.33 dB. With a compact area of 0.17 mm² and a power consumption of 650 µW from a 1.8 V supply, the proposal is well suited to biomedical sensor applications requiring strict accuracy and low energy consumption.

1. Introduction

In the era of digital healthcare and wireless utilities, the demand for wearable medical devices for continuous health monitoring is rapidly increasing [1]. In biomedical applications, a high-performance, intelligent wearable sensor node integrates sensing, processing, and communication technologies, with a scalable analog-to-digital converter (ADC) playing a pivotal role in the system architecture, as depicted in Figure 1. These devices demand a high-resolution, low-noise, and energy-efficient ADC to ensure precise processing of bio-signals, including electrocardiogram [2], electroencephalogram, blood pressure, oxygen saturation, and glucose levels. Among various ADC architectures, the successive approximation register (SAR) ADC stands out as a promising solution, thanks to its ability to balance resolution and power efficiency [3]. However, it has several performance-limiting factors, including quantization noise after each conversion step [4,5], offset voltage (V_OS), and comparator input noise. Quantization noise, also referred to as residue voltage (V_R), arises from the discrepancy between the sampled signal and the estimated value remaining in the digital-to-analog converter (DAC) after each conversion cycle. Such noise reduces the ADC and accuracy directly affects the linearity of the digitized signal. To address this problem and enhance the signal-to-noise-and-distortion ratio (SNDR), SAR ADCs can be combined with the noise-shaping (NS) and oversampling-rate (OSR) techniques, leveraging the advantages of both delta–sigma and SAR ADCs [6,7,8,9]. NS improves signal resolution by employing a feedback loop that shapes the quantization noise spectrum, effectively shifting it out of the frequency band of interest. This process enhances the SNDR, allowing for higher precision in ADC conversion. In [10], an infinite-impulse-response (IIR) filter using an operation transconductance amplifier (OTA) acted as an integrator, producing a sharper noise transfer function (NTF) characteristic. Nevertheless, while OTAs provide high gain and fast processing, they consume significant power, reducing overall power efficiency. An alternative approach proposed in [11] used a loop filter that combines dynamic amplifiers and passive switched-capacitor circuits to optimize energy efficiency and minimize noise. However, the dynamic amplifier’s gain is highly sensitive to process–voltage–temperature variations, making scalability challenging. Another method discussed in [12] is the fully passive noise-shaping technique, in which the OTA was replaced with passive capacitor switches to reduce power consumption. This approach has a drawback: signal loss due to charge leakage and internal resistance degrades conversion quality. Furthermore, in [13], adding two capacitors to the integration path helped shift the NTF zero closer to 1 (approximately 0.75). This modification enhances the system’s performance by improving noise-shaping and management. During each conversion cycle, the capacitor responsible for NS is reset, creating a trade-off between amplification, feedback, and input noise. This observation highlights the effectiveness of NS in improving the energy efficiency of SAR ADC. Furthermore, the comparator is a vital part of the ADC, ensuring precise conversion. For example, dynamic latch comparators [14] have become widely used due to their fast operation and low power consumption, but they suffer from limited stability, increased jitter, and poor scalability [15], making them less ideal for processing complex data. To address these challenges, the two-stage chopper amplifier (TSCA) is introduced to enhance performance while keeping power consumption and noise low. However, TSCA is affected by V_OS and output ripple that can degrade accuracy. To mitigate these effects, a chopper comparator with a compensation–cancelation loop is implemented, thereby stabilizing the output and reducing ripple. Moreover, the self-calibrating input stage in TSCA helps minimize the hysteresis slope and improve overall stability by reducing sensitivity to variations in process conditions and common-mode noise. Additionally, the proposed NS structure is based on a cascade of integrator feed-forward (CIFF) structure, simultaneously using IIR and finite impulse response (FIR) filters to reduce the quantization and kT/C noises to achieve high resolution while ensuring signal integrity and power efficiency due to the linear phase characteristic, preserving the signal without distortion when passing through the system. In this study, the residual from the previous passive NS process is addressed by combining a charge pump with the filter to achieve passive gain. This study also uses a modulated comparator with chopping. The input signal is first modulated to make flicker noise negligible. It is then demodulated to restore the original signal, optimizing the chip space and suppressing noise by eliminating offset and input-referred noise.

This paper offers the following new contributions to the knowledge and application of these techniques. (i) Contribution to knowledge: (1) A passive CIFF-based FIR + IIR noise-shaping loop that eliminates operational transconductance amplifiers (OTAs) from the loop filter, demonstrating that first-order noise-shaping can be achieved with zero static power in the filter path. This challenges the conventional assumption that active integrators are necessary for effective noise-shaping in SAR ADCs. (2) A chopper-stabilized two-stage comparator (TSCA) with an RC integrator that achieves a ripple reduction factor of 56.13 dB without requiring a calibration DAC or digital trimming. This provides a new method for offset cancelation that does not increase conversion time or digital complexity. (ii) Contribution to application: (3) A design in 180 nm CMOS that simultaneously achieves 10.6 ENoB, 10 MHz bandwidth, and 170.2 dB FoM, making it suitable for multi-channel time-division multiplexed biosensor arrays and impedance spectroscopy—applications that cannot be served by conventional low-bandwidth biomedical ADCs. The architecture also scales down to 18 μW for low-frequency ECG/EEG acquisition, offering a single, reconfigurable solution for heterogeneous biomedical monitoring.

2. Design

The proposed ADC structure, including the Sample and Hold (S/H), DAC, comparator, filtering operation transconductance amplifier (FOTA), and SAR logic, is shown in Figure 2. The optimized DAC structure also reduces switching power and charge redistribution losses, thereby enhancing overall efficiency. Not only that, but the differential structure of the DAC also offers several advantages over the single-ended structure, including reduced harmonic distortion, a doubled input voltage range, and an improved common-mode-rejection ratio (CMRR).

The DAC operates by charge redistribution, transforming the digital signal into an analog voltage that then serves as the input to the comparator. In addition, the proposed FOTA is placed between the DAC and the comparator to address the V_R. Signals at the comparator’s input nodes are compared in each conversion, in which, whenever V_COMP—V_COMN > 0, the comparator returns “1” and otherwise it returns “0”. The FOTA block, positioned between the DAC and comparator, comprises FIR and IIR filters that work together to reduce residual voltage from the quantization process. Specifically, the FIR and IIR filters function as integrators: the FIR filter amplifies the VR by a factor of k using a charge pump, and the amplified voltage is then integrated into V_INT. The processing of the NS SAR ADC operates in two distinct stages, referred to as the (k − 1)_th stage and the kth stage, as depicted in Figure 3. The loop filter in this architecture plays a crucial role by using both FIR and IIR filters to process residual signals, amplify them, synthesize them, and feed them back into the SAR ADC. In this work, the FIR stage provides a feedforward gain while the IIR stage introduces memory through residue integration, resulting in a loop filter H_L(ω). Thus, the resulting NTF exhibits a high-pass characteristic, effectively suppressing in-band quantization noise (1):

$$NTF(\omega )={\displaystyle \frac{1-(1-AFIRAIIR){\omega }^{-1}}{1+(7AFIRAIIR-1){\omega }^{-1}}}$$

(1)

Furthermore, after the sampling phase and DAC charging, the V_R remains after each SAR operation cycle. To address this, a feedback loop is established between the (k − 1)_th stage and the kth stage, ensuring the integrated residual from the previous cycle is incorporated into the next conversion process. This effectively enhances the accuracy and reliability of each successive conversion, ultimately improving the overall performance of SAR ADC. In practice, manufacturing errors can cause an unwanted offset at the comparator output, resulting in a discrepancy between the estimated and actual values. Typically, the TSCA structure proposed in [16] addresses this issue by minimizing V_OS and flicker noise, thereby improving D_OUT accuracy. To enhance the quantizer’s performance, increasing the V_R is essential. This is achieved by charging the capacitor in the FIR path when the S_I clock is high, enabling charge pumping to achieve the required gain, as illustrated in Figure 4.

Upon completion of the conversion process, V_R is processed using two control signals: sampling residual (S_F) and residual integration (S_I). As shown in Figure 5a, in the sampling and conversion stage, the residual voltages (V_RP and V_RN) occur at the capacitor arrays (V_DACP and V_DACN) and fluctuate around the common-mode voltage (V_CM). Once the conversion is finished, the residual voltages can be observed on both the positive and negative plates of the DACs. Each C_F capacitor holds a voltage of V_CF[k − 1] = V_INT[k − 1]/n, where n represents the number of C_F capacitors. In this work, n = 3 is selected as the most suitable value, allowing for two sampling cycles and an NS cycle to optimize performance. As illustrated in Figure 5b, the NS cycle begins after the previous stage ends. When the S_F clock is “1”, three C_F are connected in parallel with the DAC, holding the residual voltage temporarily. V_R is then transmitted from the DAC through charge redistribution. When S_F is “0”, both residual voltage processing and V_INT integration take place simultaneously as shown in Figure 5c. When the NS cycle is finished, the (k − 1)_th conversion cycle concludes, and the integrated V_INT value is added to the Capacitive DAC (CDAC) at the comparator input. This process enhances signal quality, ensuring greater accuracy for the next conversion cycle.

3. Circuit Implementation

The comparator is a critical component in SAR ADC, responsible for determining the bit decision at each step of the conversion process. The accuracy, energy efficiency, and speed of the comparator directly affect the ADC’s performance. The comparator in the proposal employs a two-stage op-amp and a chopper technique with a chopping frequency of 10 kHz to modulate flicker noise outside the two-stage op-amp’s bandwidth, thereby minimizing both comparator and flicker noise and improving accuracy. As shown in Figure 6, this design addresses offset voltage by incorporating an RC integrator comprising an operational amplifier, resistors (R_int1, R_int2), and capacitors (C_int1, C_int2). This RC integrator performs multiple functions, including filtering, amplification, and V_OS compensation at the virtual ground of G_m1. Additionally, the flicker noise from the RC integrator, along with the TCSA’s input noise floor, is modulated and processed using the chopping technique, aligning with the system’s cut-off frequency. This technique minimizes the V_OS, and the output ripple by switching S_1,2.

The initial stage of the TCSA, referred to as G_m1, utilizes a self-bias inverter-based design, as illustrated in Figure 7a. To improve noise efficiency, a current-reuse technique is employed to increase effective transconductance without increasing bias current. This doubles the transconductance (g_m) by stacking transistors in series. In addition, the outputs V_ON1 and V_OP1 are fed back to the gate bias nodes, forming a negative DC feedback loop that stabilizes the output common-mode across PVT. This self-biasing approach not only enhances stability through dynamic adjustment but also eliminates the need for a dedicated bias generator, thereby reducing power consumption. Furthermore, this design employs a differential architecture in which VIN1 and VIP1 exhibit equal amplitude but opposite phase. As a result, V_A and V_B remain unchanged, effectively functioning as AC ground nodes. Thanks to the balance condition, the differential output generates opposing voltages, which cancel out at each node through transistors M_P3, M_P4, M_N3, and M_N4. By running a Monte Carlo simulation with 200 samples under the process variation and random mismatch consideration, as shown in Figure 7b, the result shows an expectation of G_m1’s open-loop gain of 62.3 dB with a standard deviation of 2.8 dB. As a result, the first stage becomes more stable and effectively suppresses noise. As illustrated in Figure 8a, a common-source amplifier is employed in the second stage (G_m2). Since this is a two-stage amplifier architecture with a complex balancing mechanism, Miller capacitors (C_m1,2) and resistors (R_m1,2) are incorporated into G_m2 to ensure the stability of both the comparator and the common-mode feedback (CMFB) circuit. Moreover, CMFB is used to regulate the DC output voltage, which remains consistently at the desired value V_CM. Due to the use of a common-source stack structure, the CMFB output is fed back to the G_m2 branches, which inherently limits the output swing because of the added transistors in the signal path. The open-loop gain of G_m2 is also verified using Monte Carlo simulations. By running 200 samples, when the process variation and random mismatch are considered, as shown in Figure 8b, the expectation of the G_m2’s open-loop gain is 32.98 dB, while the standard deviation is 1.48 dB. As shown in Figure 9a, the schematic of G_m3 represents a two-stage amplifier designed to ensure rail-to-rail output swing. The second stage of this amplifier is a Class-A amplifier, which is used to improve efficiency. Moreover, the two-stage amplifier operates with a bias current of 11 nA under a 1.8 V supply. The open-loop gain of G_m3 is further validated through Monte Carlo simulation, using 200 samples to account for both process variation and random mismatch. As plotted in Figure 9b, the expected open-loop gain of G_m3 is 91.66 dB, with a standard deviation of 4.15 dB.

4. Simulation Results

The simulations were designed to verify three primary objectives of the proposed NS SAR ADC: (1) Noise-shaping performance—confirm that the passive FIR + IIR loop filter achieves first-order 20 dB/dec noise-shaping and the target SNDR of 68.4 dB;.(2) Chopper effectiveness—quantify the ripple reduction factor (RRF) of the chopper-stabilized comparator. (3) Statistical robustness—evaluate the variation in key parameters (open-loop gains of G_m1, G_m2, G_m3, and RRF) under process variations and device mismatch. To achieve these objectives, the following simulation scenarios were defined: Scenario A (noise-shaping): Input frequency = 4.5 MHz, sampling rate = 36 MHz, bandwidth = 10 MHz, OSR = 2, FFT with 8192 points; Scenario B (chopper effectiveness): Chopping frequency f_CH = 10 kHz, with and without RC integrator, output spectrum analysis; and Scenario C (statistical robustness): 200-sample Monte Carlo simulations with process variation (5% tolerance on device parameters) and random mismatch.

All results presented in this section are obtained from post-layout simulations using Cadence Spectre for a 180 nm CMOS process, unless otherwise specified. Monte Carlo simulations with 200 samples were performed to account for process variations and device mismatch. From Figure 10a, the active area of the proposed ADC architecture is 0.170 mm². The compact layout allows for seamless integration into biomedical and sensor applications while maintaining low power consumption. To further enhance performance, the floor plan is carefully optimized to minimize crosstalk between analog and digital domains. Operating at a 1.8 V supply voltage, the architecture consumes 650 µW, as depicted in Figure 10b. Regarding battery-powered wearable operation, the 650 μW power consumption corresponds to approximately 42 days of continuous operation from a standard 220 mAh CR2032 coin cell (3 V → 660 mWh). For typical intermittent biomedical monitoring (e.g., 1% duty cycle for ECG acquisition), the effective battery life exceeds 10 years. The ADC also supports a power-down mode with <1 μW leakage current, making it suitable for event-driven wearable systems.

Figure 11a shows the simulated output spectrum with and without an RC-integrator. The ripple reduction approach reduces the ripple in the comparator output at a chopping frequency f_CH of 10 kHz from 70.5 mV to 0.11 mV, with a ripple reduction factor (RRF) of 56.13 dB. Figure 11b shows the RRF statistical distributions produced from 200 Monte Carlo simulations. It accounts for both process variations and arbitrary mismatches. With a standard deviation of 11.27 dB, the average RRF is 55.51 dB. This low-power operation is enabled by the passive NS technique and the chopper-stabilized comparator, both of which effectively suppress quantization and input-referred noise, thereby improving overall system efficiency.

The proposed design achieves an SNDR of 68.4 dB and an ENoB of 10.6 bits when operating at an input frequency of 4.5 MHz with a 10 MHz bandwidth, as illustrated in Figure 12. According to the oversampling principle, increasing the OSR by a factor of 2 yields a 3 dB improvement in SNDR, thereby enhancing ADC accuracy. This enhancement occurs because quantization noise is spread across a broader frequency range, reducing in-band noise and improving overall performance. However, maintaining the signal bandwidth while doubling the OSR necessitates a corresponding increase in the sampling rate, which in turn doubles power consumption. As a result, relying solely on oversampling to improve ADC accuracy is not energy-efficient. Hence, to balance power efficiency and performance, the proposed architecture limits OSR to 2, as shown in Figure 13. It provides an optimization between SNDR enhancement and power efficiency, ensuring that the ADC maintains high-resolution conversion while operating within a low-power envelope. In addition, the input magnitude spectrum of the comparator decreased from −25.3 dB to −36.4 dB, effectively suppressing both comparator and quantization noises within the target frequency band, as illustrated in Figure 14.

Figure 15 shows the MC simulation results of the ENoB corresponding CDAC mismatch rate. The impact of CDAC mismatch on noise-shaping performance is evaluated using a behavioral ADC model with Monte Carlo simulations, following the methodology in prior work. As the mismatch increases from 1% to 2%, the average ENoB degrades from 10.5 bits to 10.2 bits, confirming that capacitor mismatch significantly limits the achievable resolution. This degradation arises because CDAC mismatch introduces errors in the residue voltage V_RES, which is processed by the FIR–IIR loop filter. To mitigate this effect, the unit capacitor size is selected as C_u = 35.6 fF to ensure that the mismatch remains below 1%. This choice reflects the trade-off between capacitor area and matching accuracy, as mismatch is inversely proportional to capacitor area according to Pelgrom’s law. Further improvement in linearity can be achieved using foreground calibration techniques.

Although the proposed ADC demonstrates a 10 MHz bandwidth at 36 MHz sampling rate, this specification targets emerging multi-channel time-division multiplexed biosensor arrays and impedance spectroscopy applications. For conventional low-frequency bio-signals (ECG, EEG, and EMG), the ADC can be operated at reduced sampling rates—e.g., f_s = 1 MHz for 250 kHz bandwidth—lowering power consumption to approximately 18 μW while maintaining > 10-bit resolution. This scalability makes the design versatile across a wide range of biomedical applications

Finally, the proposed ADC is benchmarked against prior work in

Table 1. Performance comparison of the proposed NS SAR ADC.

Ref.	Tech. (nm)	BW (kHz)	Power (μW)	SNDR (dB)	ENoB (bits)	FoMs (dB)	Supply (V)	Architecture
This work	180	10	650	68.4	10.6	170.2	1.8	Passive FIR + IIR, Chopper
[7]	40	0.5	12.5	71.2	11.5	177.2	0.9	2nd-order NS with EFS
[9]	65	0.625	95	74.0	12.0	172.2	1.0	2nd-order with temp. comp.
[10]	130	20	1200	69.5	11.2	161.7	1.2	CIFF with OTA
[11]	65	5	460	79.7	12.9	180.1	1.2	Dynamic amp FIR-IIR
[13]	180	1	61	74.1	12.0	177.3	1.2	Passive integrator
[17]	28	12.5	4270	79.9	13.0	174.6	1.1	2nd-order pipelined NS
[18]	28	60	2130	68.2	11.0	172.7	1.1	2-1 bit/cycle NS
[19]	65	40	284	71.2	11.5	173.6	1.0	1st-order with dynamic amp
[20]	180	0.078	417	78.0	12.7	168.0	1.8	2nd-order with dynamic amp

FoMs = SNDR + 10log10(Bandwidth/Power).

, achieving an average chip area largely due to the 180 nm CMOS process. Compared to prior art, the proposed ADC achieves a competitive FoM of 170.2 dB while operating at the highest bandwidth (10 MHz) among 180 nm implementations. Designs in advanced nodes (28 nm, 65 nm) demonstrate superior power efficiency but require higher fabrication costs and are less accessible for academic prototyping. Furthermore, unlike most prior NS SAR ADCs that rely on OTAs or dynamic amplifiers—which suffer from PVT sensitivity or calibration overhead—our passive FIR-IIR filter consumes zero static power, and the chopper-stabilized comparator eliminates offset without calibration, offering a robust performance suitable for wearable biomedical systems. In terms of energy efficiency, the proposal consumes 650 µW, reflecting a notably low energy usage compared to other NS ADC designs. This improvement stems from integrating passive NS with a chopper comparator, which effectively minimizes quantization noise and V_OS without incurring additional power overhead. The simulation results demonstrate that the design achieves an FoM of 170.2 dB, outperforming other comparable solutions. Furthermore, performance evaluation based on key ADC metrics shows that the proposed ADC achieves an SNDR of 68.4 dB and an ENoB of 10.6 bits, making it well suited for high-resolution biomedical applications.

5. Conclusions

A passive architecture designed using the CIFF model and integrating FIR and IIR filters is optimized for wearable medical applications. While the presented results are based on post-layout simulations, the proposed architecture is currently being prepared for tape-out. Experimental validation will be reported in future work. By implementing an 8-bit DAC alongside the passive NS technique, the proposed SAR ADC achieves an ENoB of 10.6 bits, consumes 650 µW from a 1.8 V supply, and fits within a compact 0.170 mm² area. In summary, this architecture is highly suitable for biomedical wearable systems, offering several advantages, including effective suppression of quantization, input-referred, and kT/C noises, and high energy and area efficiency for integration into health monitoring systems. For low-voltage (sub-1.2 V) wearable applications, the proposed architecture faces limitations primarily in comparator gain and charge pump efficiency. Simulations at 0.9 V supply indicate a 5–8 dB SNDR degradation due to reduced G_m1 open-loop gain. Mitigation strategies include using native-VT devices, reducing the charge pump ratio from 3 to 2, or replacing the TSCA with a dynamic comparator. A low-voltage-optimized version of this design is currently under development and will be reported in future work. Nevertheless, for standard 1.8 V coin-cell-powered wearables with LDO regulation, the proposed design offers a robust, high-performance solution without requiring low-voltage design techniques.