Parasitics-Aware Quantum Transport Simulation of Stacked Si Nanosheet LGAA-nFETs for Sub-2 nm Node RF Applications

Abstract

This work presents a comprehensive quantum transport modeling and simulation framework to evaluate parasitic effects and radio frequency (RF) performance in stacked silicon (Si) nanosheet (NS) lateral gate-all-around (LGAA) nFETs targeting the sub-2 nm technology node. Leveraging the non-equilibrium Green’s function (NEGF) method, the proposed framework integrates detailed modeling of parasitic resistances (R_para) and capacitances (C_para) to enable a holistic analysis of both intrinsic and extrinsic figures-of-merit, including transconductance (g_m), output conductance (g_d), cutoff frequency (f_T), and maximum oscillation frequency (f_max). The effects of nanosheet geometry, crystal orientations, and dual-k spacers on high-frequency performance are systematically investigated. The analysis reveals key design trade-offs, with optimized device configurations yielding f_T exceeding 400 GHz and f_max approaching 1.2 THz. These findings highlight the potential of stacked NS LGAA-nFETs for future millimeter-wave and terahertz applications, providing critical insights into parasitics management and quantum-transport-aware design strategies at advanced CMOS nodes.

1. Introduction

The relentless advancement of wireless communication systems, the Internet of Things (IoT), medical imaging, military and aerospace applications has imposed unprecedented demands on the high-frequency performance of CMOS integrated circuits (ICs) [1,2,3]. Particularly, the transition toward 6G and beyond requires carrier frequencies extending into the terahertz range, which imposes even more stringent requirements on the high-frequency figures-of-merit of CMOS ICs [4]. To realize high-efficiency wireless applications and advanced terahertz detection at such frequencies, it is essential to characterize non-linear carrier dynamics and phase transitions using rigorous physical models [5].

As the cornerstone of CMOS technology, transistors must simultaneously deliver high drive current and low parasitic losses to meet the increasingly challenging requirements of advanced technology nodes [6]. While FinFETs have served as the foundation of CMOS ICs for over a decade, their inherent limitations in gate electrostatic control, channel width scalability, and current drivability have prompted the exploration of lateral gate-all-around (LGAA) architectures for next-generation transistors [7,8,9]. In particular, stacked silicon (Si) nanosheet (NS) LGAA-FETs, with their enhanced gate control, higher effective channel width, and improved short-channel immunity, are widely regarded as the most promising successor of FinFET to extend Moore’s Law beyond 2 nm technology node [10,11,12]. On one hand, the aforementioned advantages may help reduce the drain field penetration and output conductance to maintain signal integrity, making the device structure ideal for both logic and analog/RF applications [13,14]. On the other hand, the intricate multi-stack structure can introduce more parasitic capacitances (C_para) and resistances (R_para) that degrade RF performance metrics such as cutoff frequency (f_T) and maximum oscillation frequency (f_max) [15,16]. However, existing studies on stacked Si NS LGAA n-type FETs (nFETs) have predominantly focused on DC performance for logic applications [17,18,19,20]. The channel width, thickness, and crystal orientation configurations of the NS channel have been demonstrated to significantly influence carrier mobility and DC characteristics [21,22,23]. Spacer engineering has been proposed to decouple gate electrostatic control from parasitic coupling [24,25,26]. For example, dual-k spacers consisting of low-k outer layers and high-k inner layers have shown promise in reducing C_para and OFF-state leakage without compromising short channel immunity [25,26]. Nevertheless, their impact on the RF performance of Si NS LGAA-nFETs has to be analyzed in conjunction with the interdependent effects of channel geometry, crystal orientation, and contact materials. While recent studies, often utilizing commercial TCAD tools such as Synopsys Sentaurus [27,28], have made significant progress in analyzing RF performance, a holistic analysis of silicon nanosheets that integrates these parasitic effects with a more fundamental quantum transport simulation (NEGF) remains underexplored. Addressing parasitic effects together with quantum effects remains a critical challenge for sub-2 nm node RF applications. Prior works explored the RF-oriented design of Si NS LGAA-FETs with the help of commercial solvers like Sentaurus and specialized field solvers like Raphael [29,30,31], but they often oversimplified the quantum transport properties, such as sub-band splitting and non-parabolicity, which are pivotal for sub-2 nm channels. This necessitates the development of a quantum-accurate, parasitics-aware simulation framework that bridges carrier transport with device high-frequency response. While industry-standard compact models, such as the BSIM-CMG, are widely used for circuit-level design, they increasingly rely on quantum-mechanical corrections to account for nanoscale phenomena. High-order simulation frameworks like the NEGF method are critical for benchmarking these compact models, providing the physical basis for their parameter extraction in the absence of experimental data. The framework presented in this work bridges the gap between fundamental quantum transport and technology pathfinding, ensuring that the predictive design rules for sub-2 nm nodes are grounded in rigorous physics.

This article is a revised and expanded version of [32]. Based on the non-equilibrium Green’s function (NEGF) formalism, this work demonstrates a holistic simulation framework that integrates dissipative quantum transport, parasitics modeling, and RF performance evaluation for stacked Si NS LGAA-FETs. Instead of the widely used effective mass approximation model [33,34], a two-band k·p Hamiltonian is employed so that the effects of non-parabolicity, sub-band splitting, and quantum confinement on conduction band structure can be captured more explicitly [32,35]. Considering different configurations of channel dimensions, crystal orientation, dual-k spacer, and contact materials, parasitic effects and RF figures-of-merit are analyzed systematically for the sub-2 nm technology node. The remainder of this paper is organized as follows: Section 2 details the device structure, parasitic modeling, and the complete simulation framework. Section 3 presents and analyzes numerical results on parasitics and device performance metrics. Section 4 concludes the work.

2. Modeling and Simulation Framework

2.1. Device Structure Modeling

Figure 1a and Figure 1b present the three-dimensional (3-D) and cross-sectional schematics of a Si NS LGAA-FET structure, respectively, where all parasitic resistance and capacitance components are explicitly depicted. The x–, y–, and z–coordinate axes align with the device’s length (transport direction), width, and height/thickness, respectively. The metal contacts are positioned atop the source (S)/drain (D) epitaxial (EPI) and the gated regions, with silicide serving as an interfacial layer at the S/D contact. A dual-k spacer consisting of Si₃N₄ and HfO₂ is deposited within the gaps between metal contacts, encapsulating the entire extension (EXT) region. The geometric parameters of the device are defined and summarized in Table 1, whose default values are configured to comply with sub-2 nm node specifications according to the 2023 International Roadmap for Devices and Systems (IRDS) [6].

Figure 1. Stacked NS LGAA-nFET structure with various parasitic components in (a) three-dimensional schematic of single-stack NS LGAA-FET and (b) x–z cross-sectional view of 3-stack NS LGAA-FETs. Source and drain regions are symmetric with respect to the gate.

Table 1. Design parameters of stacked NS GAAFETs.

Symbol	Physical Meaning (Unit)	Value
Lcon	Metal contact length (nm)	8
Wcon	Metal contact width (nm)	20
Lsd	Length of S/D epitaxy (nm)	14
Wsd	Width of S/D epitaxy (nm)	36
Lext	S/D extension length (nm)	8
Lg	Gate/channel length (nm)	10
Wch	NS channel width (nm)	6–28
Tch	NS channel thickness (nm)	3–4
Tox	Oxide thickness (nm)	1
Tsp	Inner spacer thickness (nm)	10
Nstack	No. of NS stacks	3
NSD	S/D doping concentration (cm−3)	2 × 1020

2.2. Parasitic Components Modeling

The total C_para arises from the electrostatic coupling between various conductive regions of the device, as illustrated in Figure 1, which can be broken down into several key components: the contact-to-contact capacitance, gate-to-contact capacitance, gate-to-EPI capacitance, and gate-to-EXT capacitance. These components can be modeled using parallel-plate (C_par), perpendicular-plate (C_per), and co-planar-plate (C_pi) capacitors models, with their geometric configurations depicted in Figure 2a and Figure 2b, and Figure 2c, respectively.

Figure 2. Geometries and electric field distributions of (a) parallel-plate, (b) perpendicular-plate, and (c) co-planar-plate capacitor models. (d) Schematics of Schottky barrier formed at the metal contact/Si interface, where the current conduction mechanism contains the competition of thermionic emission (TE), thermionic-field emission (TFE), and field emission (FE).

To clarify the field-coupling topology of the parasitic capacitance network illustrated in Figure 1b, the labeled components are described below from the top of the device to the substrate. The highest red symbol represents the parallel-plate capacitance formed between the inner vertical sidewalls of the two metal contacts. Moving down, the green symbols represent the contact-to-gate and contact-to-S/D EPI fringing perpendicular-plate capacitance. It captures the electrostatic coupling between the vertical sidewall of the metal contact and the top horizontal surfaces of the gate electrode and S/D epitaxy. In the middle region of the structure, the red symbol represents the parallel capacitance formed between the vertical sidewalls of the gate electrode and the S/D EPI. This is a major component of the gate-to-S/D parasitic coupling. At the lower levels near the nanosheet channels, the multiple green symbols represent the perpendicular fringing capacitances between the gate stack and the S/D extension regions across the inner spacers. These C_per components model the fringing fields emanating from the gate to the extension regions that are not directly parallel. In addition, all the purple symbols represent the coplanar capacitance components between different conductive surfaces, contributed by the coupling of contact-to-contact, contact-to-S/D EPI, and gate-to-S/D EPI regions.

C_par is calculated as εlw/d, where ε represents the constant and uniform permittivity of the dielectric material between two parallel conductive plates with length l, width w, and separation distance d. Leveraging conformal mapping and elliptic integral techniques, both C_per and C_pi can be calculated via an inclined-plate capacitor model [36]. The inner capacitance between two conductive plates inclined at an angle φ is formulated as

$$C_{\phi }(k)=\epsilon w{\displaystyle \frac{K\left(k\right)}{K\left(k^{\prime }\right)}}$$

(1)

where φ is π/2 and π for C_per and C_pi, respectively. K(k) is the complete elliptic integral of the first kind, and the modulus k is given by

$$k=\sqrt{{\displaystyle \frac{\left({\left(r_1+l_1\right)}^{\pi /\phi }-r_1^{\pi /\phi }\right)\left({\left(r_2+l_2\right)}^{\pi /\phi }-r_2^{\pi /\phi }\right)}{\left({\left(r_1+l_1\right)}^{\pi /\varphi }+r_2^{\pi /\phi }\right)\left({\left(r_2+l_2\right)}^{\pi /\phi }+r_1^{\pi /\phi }\right)}}}$$

(2)

and $k^{\prime }=(1-k^2{)}^{1/2}$.

The minimal distances of the plates to the origin are r₁ and r₂, the lengths of which are l₁ and l₂, respectively. Substituting the corresponding values of φ, r₁, r₂, l₁, and l₂ into (2) for C_per and C_pi based on Figure 2b,c, we have

$$k_{\mathrm{per}}=\sqrt{{\displaystyle \frac{\left({\left(r_1+l_1\right)}^2-r_1^2\right)\left({\left(r_2+l_2\right)}^2-r_2^2\right)}{\left({\left(r_1+l_1\right)}^2+r_2^2\right)\left({\left(r_2+l_2\right)}^2+r_1^2\right)}}}$$

(3)

$$k_{\mathrm{pi}}=\sqrt{{\displaystyle \frac{L_1{L}_2}{\left(L_1+D\right)\left(L_2+D\right)}}}$$

(4)

As illustrated in Figure 1, the total R_para can be divided into contact resistance (R_con), S/D EPI resistance (R_epi), spreading resistance (R_sp), and S/D EXT resistance (R_ext). R_para is modeled as the R_con in series with the parallel combination of three identical branches, one for each nanosheet channel. Each of these branches consists of the series combination of the R_epi, R_sp, and R_ext. In our framework, R_ext can be well handled by the dissipative NEGF simulation; the other extrinsic components are modeled analytically based on established formulas. R_epi and R_sp can be calculated by

$$R_{\mathrm{epi}}={\rho }_{\mathrm{SD}}{\displaystyle \frac{T_{\mathrm{sp}}}{W_{\mathrm{sd}}{L}_{\mathrm{sd}}}}$$

(5)

and

$$R_{\mathrm{sp}}={\displaystyle \frac{{\rho }_{\mathrm{SD}}{L}_{\mathrm{sd}}}{W_{\mathrm{ch}}{T}_{\mathrm{sp}}-\left(W_{\mathrm{sd}}-W_{\mathrm{ch}}\right)T_{\mathrm{ch}}}}\mathit{ln}\left({\displaystyle \frac{W_{\mathrm{ch}}\left(T_{\mathrm{ch}}+T_{\mathrm{sp}}\right)}{W_{\mathrm{sd}}{T}_{\mathrm{ch}}}}\right)-{\displaystyle \frac{{\rho }_{\mathrm{SD}}{L}_{\mathrm{sd}}}{W_{\mathrm{sd}}\left(T_{\mathrm{ch}}+T_{\mathrm{sp}}\right)}}$$

(6)

where ρ_SD is the bulk resistivity of n-doped Si. R_sp results from the mismatch of current pathway at the spreading region from sheet EXT to bulk EPI.

R_con arising from the current crowding effect and the Schottky barrier (SB) at the contact/Si interface, is calculated via transmission line model (TLM) as

$$R_{\mathrm{con}}={\displaystyle \frac{{\rho }_{\mathrm{con}}}{\sqrt{\frac{{\rho }_{\mathrm{con}}}{{\rho }_{\mathrm{SH}}}}\cdot W_{\mathrm{cnt}}}}\cot \mathrm{h}\left({\displaystyle \frac{L_{\mathrm{con}}}{\sqrt{\frac{{\rho }_{\mathrm{con}}}{{\rho }_{\mathrm{SH}}}}}}\right)$$

(7)

where ρ_SH is the n-Si sheet resistivity, and both ρ_SD and ρ_SH can be calculated from the electron mobility via the Masetti model [37]. ρ_con is the contact resistivity, and it is determined by the competition of thermionic emission (TE), field emission (FE), and thermionic-field emission (TFE) at the SB region, as illustrated in Figure 2d. We have

$${\rho }_{\mathrm{con},\mathrm{TE}}={\displaystyle \frac{k_B}{q_0{A}^{*}T}}\exp \left({\displaystyle \frac{{\varphi }_B}{k_{B}T}}\right)$$

(8)

$${\rho }_{\mathrm{con},\mathrm{T}\mathrm{F}\mathrm{E}}={\displaystyle \frac{k_B}{q_0{A}^{*}T}}\sqrt{{\displaystyle \frac{E_{00}}{\pi ({\varphi }_B+E_f)}}}\cosh \left({\displaystyle \frac{E_{00}}{k_{B}T}}\right)\coth {\displaystyle \frac{E_{00}}{k_{B}T}}\exp \left({\displaystyle \frac{{\varphi }_B+E_f}{k_{B}T}}-{\displaystyle \frac{E_f}{k_{B}T}}\right)$$

(9)

$${\rho }_{\mathrm{con},\mathrm{FE}}={\displaystyle \frac{\frac{k_B}{q_0{A}^{*}}\exp \left(\frac{{\varphi }_B}{E_{00}}\right)}{\frac{\pi T}{\mathit{sin}\left(\pi c{k}_{B}T\right)}-\frac{1}{c{k}_B\mathit{exp}\left(c{E}_f\right)}}}$$

(10)

where

$$E_{00}={\displaystyle \frac{q_{0}h}{4\pi }}\sqrt{{\displaystyle \frac{N_{\mathrm{SD}}}{{\epsilon }_s{m}_t^{*}}}}$$

(11)

$$E_0=E_{00}\sqrt{\cot \mathrm{h}\left({\displaystyle \frac{E_{00}}{k_{B}T}}\right)}$$

(12)

$$c={\displaystyle \frac{1}{2E_{00}}}\mathit{ln}\left({\displaystyle \frac{4{\varphi }_B}{E_f}}\right)$$

(13)

the effective Richardson constant A* is expressed as

$$A^{*}={\displaystyle \frac{4\pi q_0{m}^{*}{k}_B^2}{h^3}}$$

(14)

where φ_B and E_f are the SB height and the Fermi level, respectively.

2.3. NEGF-Based Simulation Framework

The comprehensive set of physical parameters, material constants, and simulation targets utilized in our numerical framework is summarized in Table 2.

Table 2. Stacked nanosheet LGAA-FET device parameters.

Symbol	Physical Meaning	Value (Unit)
h	Planck constant	6.626 × 10−34 (J·s)
ℏ	Reduced Planck constant	1.055 × 10−34 (J·s)
kB	Boltzmann constant	1.380 × 10−23 (J/K)
m0	Electron rest mass	9.109 × 10−31 (kg)
q0	Elementary charge	1.602 × 10−19 (C)
ε0	Vacuum permittivity	8.854 × 10−12 (F/m)
εs	Silicon relative permittivity	11.9
χs	Silicon electron affinity	4.05 (eV)
εox	Gate oxide relative permittivity	3.9
χox	Gate oxide affinity	3.34 (eV)
ρ	Silicon mass density	2329 (kg/m3)
a0	Silicon lattice constant	5.43 (Å)
Eg	Silicon band gap	1.12 (eV)
m*	Silicon overall effective mass	0.42 (m0)
ml	Longitudinal effective mass	0.91 (m0)
mt	Transverse effective mass	0.19 (m0)
Ξd	Dilatational deformation potential	1.1 (eV)
Ξu	Uniaxial deformation potential	9 (eV)
Ξu’	Shear deformation potential	7 (eV)
dop	Optical deformation potential	8.0 (eV/Å)
v	Sound velocity	9.04 × 103 (m/s)
C11	Elastic stiffness constants	1.66 × 1011 (Pa)
C12		6.40 × 1010 (Pa)
C44		7.96 × 1010 (Pa)
ℏω	Optical phonon energy	63 (meV)
T	Operating temperature	300 (K)

The detailed execution flow and the hierarchical self-consistent iteration procedures of the in-house dissipative NEGF-Poisson solver are outlined in Table 3.

Table 3. Procedures of the NEGF simulation.

Step 1:	Initially, set bias voltages (VGS, VDS) and initialize the electrostatic potential φ1. Compute the strain tensor and construct the Hamiltonian H3D using the 2-band k⋅p model.
Step 2:	Construct the scattering matrices (Mac, Mop) for acoustic and optical phonon interactions based on deformation potentials.
Step 3:	Solve the ballistic NEGF-Poisson equations self-consistently to obtain a stable initial potential profile φbal and drain current Ibal.
Step 4:	Extract the cross-sectional potential from the simulation domain and construct the mode-space basis using the Lanczos or eigenvalue method to generate the reduced-order Hamiltonian h.
Step 5:	Calculate the lead self-energies in the mode space (${\mathit{\sigma }}_{S/D}^{\mathit{R}}$, ${\mathit{\sigma }}_{S/D}^{<}$) to satisfy the open boundary conditions for the current energy grid.
Step 6:	Compute the phonon scattering self-energies (${\mathit{\sigma }}_{ac}^{\mathit{R}}$, ${\mathit{\sigma }}_{ac}^{<}$, ${\mathit{\sigma }}_{op}^{\mathit{R}}$, ${\mathit{\sigma }}_{op}^{<}$) using the current Green’s functions (${\tilde{\mathit{G}}}^{\mathit{R},1}$, ${\tilde{\mathit{G}}}^{<,1}$) and solve the Dyson and Keldysh equations to update the full Green’s functions.
Step 7:	Calculate the electron density $\tilde{n}$ and current $\tilde{I}$. If (${\displaystyle \frac{\Delta \tilde{n}}{\tilde{n}}}$) < 0.1% and current continuity error < 0.5%, go to Step 8, else update ${\tilde{\mathit{G}}}^{\mathit{R},l}={\tilde{\mathit{G}}}^{\mathit{R},l-1}$, ${\tilde{\mathit{G}}}^{<,l}={\tilde{\mathit{G}}}^{<,l-1}$ and go to Step 6. (inner self-consistent Born loop)
Step 8:	Solve the non-linear Poisson equation using the Gummel scheme to update the electrostatic potential φn for the entire device domain.
Step 9:	If $\max \left(\left|{\phi }^n-{\phi }^{n-1}\right|\right)<0.001\mathrm{V}$, end (simulation converged for the current bias point); Else ${\phi }^n={\phi }^{n-1}$, and go to Step 4. (outer NEGF-Poisson loop)

Figure 3 presents our modeling and simulation framework, designed to holistically evaluate the performance of stacked Si NS LGAA-nFETs by linking quantum transport with extrinsic parasitic effects. Our methodology is to first use our in-house developed NEGF simulator to yield the intrinsic device characteristics, which simultaneously accounts for R_ext and quantum capacitance effects. These intrinsic results are then combined with the analytically modeled extrinsic parasitic components to evaluate the final RF figures-of-merit. The simulation workflow iteratively solves the NEGF and Poisson’s equations through an outer loop for achieving self-consistent distributions of carrier density and electrostatic potential, where the reduced-order mode-space method is adopted to reduce the computational load [38]. Using the unitary transformation matrix constructed by the reduced basis, the two-band k·p Hamiltonian, self-energies, and Green’s functions are computed in a reduced-order mode-space for each energy grid. Electron–phonon interactions are incorporated through the self-consistent Born approximation [39], where the retarded and lesser self-energies of acoustic and optical phonon scattering are coupled with Green’s functions in the expressions, requiring an inner iteration loop to realize self-consistency.

Figure 3. Modeling and simulation framework for evaluating parasitic effects and device performance of the stacked Si NS LGAA-nFETs, where the flowchart of dissipative NEGF simulation is included.

As illustrated in the modeling and simulation framework in Figure 3, the tool is structured as a hierarchical evaluation system for advanced technology nodes. The physical core of the framework is the dissipative NEGF engine, which addresses the fundamental transport limits of sub-2 nm nanosheets. This engine utilizes a two-band k·p Hamiltonian, which is discretized using the finite difference method across all three spatial directions to accurately capture non-parabolicity and sub-band splitting. To ensure physical rigor while maintaining computational tractability, a reduced-order mode-space technique is implemented via a unitary transformation matrix. Conceptually, the framework bridges pure transport physics and RF engineering through two nested loops: (i) an inner self-consistent Born loop to model carrier energy relaxation via acoustic and optical phonon scattering; and (ii) an outer Poisson loop to achieve electrostatic self-consistency across the 3-D device domain. Furthermore, the framework integrates extrinsic parasitics derived from the TLM for resistances and conformal mapping with elliptical integrals for capacitances. Technically, the calculated parasitic resistances are integrated as voltage-drop elements that self-consistently modify the effective boundary potential of the NEGF solver, ensuring that the finalized RF figures-of-merit (f_T, f_max) incorporate both intrinsic quantum limits and structural parasitic losses.

Furthermore, key RF figures-of-merit, including extrinsic transconductance (g_mx), output conductance (g_dx), f_T, and f_max, are evaluated via

$$g_{mx}={\displaystyle \frac{g_m}{1+R_S{g}_m}},g_m={\left.{\displaystyle \frac{\partial I_D}{\partial V_{GS}}}\right|}_{V_{DS}}$$

(15)

$$g_{\mathrm{dx}}={\displaystyle \frac{g_d}{1+(R_S+R_D)g_d}},g_d={\left.{\displaystyle \frac{\partial I_D}{\partial V_{\mathrm{DS}}}}\right|}_{V_{\mathrm{GS}}}$$

(16)

$$f_T={\displaystyle \frac{g_m}{2\pi C_{\mathrm{GG}}}}$$

(17)

$$f_{max}={\displaystyle \frac{f_T}{2\sqrt{g_d(R_S+R_G)+2\pi f_T(R_S+R_G)C_{\mathrm{GD}}}}}$$

(18)

R_S and R_D denote the source and drain resistances, respectively, and they are equal to half of the total resistance under the assumption that they are symmetric. R_G is the gate metal resistance. C_GG is the gate capacitance and can be treated as the sum of parasitic and oxide capacitance [29].

All the simulation parameters are determined according to Table 1 and Table 2 and the device performance specifications in the 2023 IRDS [6]. For high-performance applications at a sub-2 nm node, the OFF-state current (I_OFF) is targeted at 10 nA, the supply voltage (V_DD) is set to 0.6 V, and the operational temperature T is maintained at room temperature (300 K).

3. Results and Discussion

3.1. Intrinsic Quantum Transport Properties and DC Characteristics

The energy–wave vector (E-k) dispersion curves of different conduction band sub-bands are shown in Figure 4 for a Si NS channel with 3 nm × 21 nm cross section, obtained from the two-band k·p Hamiltonian. Figure 4a,b compares the effects of channel orientations [100] and [110], revealing significant differences in band curvature, degeneracy, and subband splitting. For both orientations, the conduction band minimum resides at the Γ point and is projected from the two Δ valleys on the <001> axis, whose sub-bands dominate the electron transport properties. A valley splitting slightly below 0.17 eV is observed in both cases, identifying the energy level of the second lowest valley minimum contributed from the valleys on the <100> and <010> axes. While Δ_<100> and Δ_<010> valleys are projected onto the [100]-channel with 2-fold degeneracy, the projection onto the [110]-channel merges these valleys near the X point, leading to coincident primed sub-bands with 4-fold degeneracy. Moreover, the [110] orientation results in larger density-of-states (DOS) and lower electron effective mass.

Figure 4. Conduction band structures for Si NS channel with 3 nm × 21 nm cross section oriented along (a) [100] and (b) [110].

Figure 5 presents the cross-sectional ON-state electron density distributions in the y–z plane, for NS Si channels with different orientations and dimensions, which are obtained from the dissipative NEGF simulations. For both channel orientations, two prominent conductive layers with high electron concentration emerge adjacent to the vertical sidewalls (aligned with the thickness direction). While the [100]-channel exhibits stronger electron density localization near the midpoint of channel sidewalls, electron density maxima shift toward the four corners in the [110]-channel. This is the consequence of the valley degeneracy phenomenon depicted by Figure 4. Enlarging the cross-sectional area reduces the maximum electron density and enhances spatial uniformity, reflecting mitigated electrostatic confinement. It should be noted that while quantum effects may be addressed phenomenologically in single-device current-voltage (I-V) characteristics, their dominance is clearly observed in the performance sensitivity to structural scaling. For example, the non-linear shifts in current and capacitance as nanosheet thickness varies are intrinsic manifestations of sub-band splitting and confinement, physics that our NEGF framework captures inherently, offering predictive capabilities that classical drift–diffusion models lack without extensive recalibration.

Figure 5. Spatial electron density distributions in the y–z cross-section of ON-state channel (obtained from NEGF simulation) with orientation and cross-sectional area of (a) [100]/3 nm × 21 nm, (b) [100]/4 nm × 28 nm, (c) [110]/3 nm × 21 nm, and (d) [110]/4 nm × 28 nm, respectively.

Figure 6a and Figure 6b present the NEGF simulated transfer and output characteristics, respectively, for a [110]-oriented Si NS LGAA-nFET with a 3 nm × 21 nm sheet cross section. It is observed that I_D is saturating as V_DS approaches V_DD, and an ON–OFF ratio higher than 8 × 10³ can be achieved for V_DD = 0.6 V and I_OFF = 10 nA. A subthreshold swing (SS) of ~76 mV/dec is extracted, indicating effective gate control.

Figure 6. (a) I_D-V_GS transfer characteristics and (b) I_D-V_DS output characteristics at various V_DS for an LGAA-nFET with 3 nm × 21 nm Si NS channel oriented along [110] direction, where the supply voltage V_DD = 0.6 V and I_OFF = 10 nA for the high-performance logic applications.

3.2. Extrinsic Parasitics Effects and RF Performance

Figure 7a illustrates the dependence of ρ_con on N_SD at the S/D contact/n-Si interface for SB height ranging from 0.1 to 0.8 eV. In the low doping regime where N_SD < 2 × 10¹⁹ cm⁻³, TE governs the interfacial carrier transport, resulting in relatively high ρ_con values (>10⁻⁸ Ω·cm²) constrained by the SB height. As N_SD increases to a moderate level, TFE becomes the dominant conduction mechanism, causing a gradual reduction in ρ_con with higher doping densities. Within this range, a target ρ_con of 5 × 10⁻⁹ Ω·cm² is achievable for SB heights ≤ 0.3 eV. For the degenerate doping case (N_SD > 4 × 10²⁰ cm⁻³), ρ_con exhibits a sharper decline due to FE-dominated tunneling through the thinned SB. Notably, the effect of SB height diminishes progressively with increasing N_SD. Figure 7b demonstrates that the total R_para can be reduced by the increase in sheet dimensions and S/D doping level, owing to enhanced current-carrying capacity and improved contact characteristics. Figure 7c analyzes the total C_para modulation with the effects of spacer materials and L_ext. It indicates that increased L_ext and lower-k spacer materials effectively suppress C_para by weakening the capacitive coupling between conductive plates. Considering a dual-k spacer architecture combining Si₃N₄ (low-k) and HfO₂ (high-k) with thickness fraction α allocated to Si₃N₄, Figure 7d shows its impact on the total C_para for various NS cross-sectional sizes. The competition between gate leakage suppression and C_para minimization can be balanced by a proper α. Additionally, the expansion of the channel cross-section results in larger C_para because of reduced fringing field distances between the gate and EXT regions. To verify the accuracy of our parasitic models, independent validation points from recent literature are incorporated as scatter symbols in Figure 7b,c. Specifically, our calculated parasitic resistances show consistent scaling trends with the 3 nm and 1.5 nm benchmarks in [16], while our capacitance results for various dielectric spacers exhibit an extraordinary numerical match with the results reported in [30,31]. This cross-verification confirms that our simulation framework accurately captures the electrostatic coupling and transport physics at the sub-2 nm node.

Figure 7. (a) Contact resistivity (ρ_con) versus N_SD for various barrier heights. (b) Source/drain parasitic resistance (R_para) as a function of channel width (W_ch). (c) Parasitic capacitance (C_para) as a function of extension length (L_ext) for different spacer materials. (d) C_para versus dual-k ratio α. In (b,c), the scatter symbols represent independent validation data extracted from recent state-of-the-art studies [16,30,31] for similar nanosheet architectures.

Figure 8a and Figure 8b present C_GS-V_GS and C_GD-V_DS characteristics at V_DS = V_DD and V_GS = V_DD, respectively, for different cross-sectional sizes of the NS channel. Both C_GS and C_GD exhibit approximately direct proportionality to NS width and saturate at high biasing conditions. However, while C_GS increases sublinearly with increasing V_GS, C_GD decreases inversely with V_DS, saturating to a minimum value at high V_DS. Figure 8c and Figure 8d show the similar trends of g_mx-V_GS and g_dx-V_DS to those of C_GS-V_GS and C_GD-V_DS, respectively, for various cross-sectional areas of the NS channel. A higher voltage gain (g_m/g_d) is achieved by a smaller channel cross-section, exceeding 30 at T_ch = 3 nm and W_ch = 6 nm. This results from the improvement of gate electrostatics and suppression of the short-channel effect.

Figure 8. C-V, g_m-V, and g_d-V characteristics of [110]-oriented Si NS nFETs with different channel cross-sectional dimensions T_ch and W_ch: (a) C_GS-V_GS at V_DS = V_DD, where W_ch is 6, 9, 12, 15, 18 and 21 nm from bottom to top for T_ch = 3 nm, and it is 8, 12, 16, 20, 24 and 28 nm from bottom to top for T_ch = 4 nm; (b) C_GD-V_DS at V_GS = V_DD; (c) g_mx-V_GS at V_DS = V_DD; (d) g_dx-V_DS at V_GS = V_DD.

Figure 9a,b demonstrates the opposite trends of f_T and f_max varying with W_ch in a sub-2 nm node Si NS LGAA-nFET. f_T increases by ~40% as W_ch widens, driven by the enhancement in transconductance. Conversely, f_max decreases by ~35% over the same W_ch range due to increased parasitic resistance in narrow channels. A thinner NS channel (T_ch = 3 nm) is beneficial for improving operation frequency owing to enhanced gate control. The channel crystal orientation [100] slightly outperforms [110], achieving overall larger f_T and f_max, and this is attributed to the lower DOS and thereby weaker scattering in the electron transport. Figure 9c,d further demonstrate that both f_T and f_max are promoted by the increase of α, and [110] channel orientation helps improve f_max for thicker NS channels (T_ch = 4 nm). In general, Figure 9 reveals the potential applications of sub-2 nm Si NS LGAA-nFETs at millimeter-wave and terahertz frequencies.

Figure 9. (a) f_T and (b) f_max versus W_ch for different combinations of T_ch and channel orientation at α = 0.75. (c) f_T and (d) f_max varying with α at different W_ch for [100] and [110] channel orientations, respectively, where T_ch is fixed at 4 nm; W_ch is 8, 12, 16, 20, 24, and 28 nm from bottom to top in (c), while from top to bottom in (d).

It is worth noting that while the extracted f_T and f_max reach the THz range, the use of the quasi-static approximation (i.e., solving the Poisson equation) remains physically justified. This is because the characteristic dimensions of the sub-2 nm LGAA-FET (~100 nm) are significantly smaller than the electromagnetic wavelength at 400 GHz (ranging from 750 μm in vacuum to hundreds of micrometers in dielectric media). In such a deep sub-wavelength regime, retardation and distributed effects across the individual device are negligible, ensuring the reliability of the self-consistent NEGF-Poisson framework.

4. Conclusions

In summary, this study provides an integrated parasitics-aware quantum transport framework to evaluate the RF performance of sub-2 nm stacked Si NS LGAA-nFETs. By combining a two-band k·p model and dissipative NEGF simulations with a detailed parasitic network analysis, this work characterizes the coupled effects of channel geometry, crystal orientation, and dual-k spacers on key RF figures-of-merit. The results identify a critical design trade-off where scaling W_ch and T_ch enhances voltage gain and fmax, whereas a wider channel is required to optimize f_T. Furthermore, [100] crystal orientation is shown to mitigate electron–phonon scattering, thereby improving f_max compared to [110] configurations. Our analysis suggests that the implementation of dual-k spacers, combined with minimized Schottky barriers and optimized S/D doping, significantly reduces parasitic components, allowing projected f_T and f_max to approach the terahertz regime. Based on our simulation framework that bridges quantum effects and circuit-level performance, the findings of this work offer meaningful design insights for the development of ultra-scaled RF CMOS technology and highlight the necessity of co-designing quantum transport physics with parasitic models for the potential millimeter-wave applications of stacked-LGAA transistor structures.