Modeling and Two-Loop Sliding-Mode Control of a Bidirectional DC–DC Converter for Fast EV Charging and Vehicle-to-Grid Operation

Abstract

A bidirectional DC–DC converter is the part that lets an electric vehicle both draw a fast charge and push power back during vehicle-to-grid (V2G) operation, so its control decides how well the DC link holds up when the load jumps or the power reverses. This paper sets out a full switching-level model of a synchronous half-bridge converter that sits between a 400 V battery pack and a 750 V DC link at 50 kW, and it controls that converter with a two-loop sliding-mode scheme: an inner sliding-mode current loop with a boundary layer to limit chatter and an outer loop that holds the link voltage. The controller is written out term by term and compared against a conventional PI cascade on the same plant. Under a 40 to 100 percent load step, the sliding-mode controller settles the link in 0.71 ms with a 2.42 percent dip, against 1.75 ms and 4.20 percent for the PI cascade, and its response barely changes when the inductor is 40 percent larger and its resistance is 50 percent higher than the controller assumes, which is the invariance property sliding-mode control is meant to give. Power reverses from full discharge to full charge in 0.255 ms, about four and a half times faster than the same PI cascade taken through the reversal. A converter loss model, with conduction evaluated per switch from the RMS current, puts peak efficiency at 98.69 percent near 23 kW and 98.39 percent at the rated 50 kW. The converter is then driven by a real-world charging-demand profile taken from 41,213 charging sessions recorded at the Newcastle Helix site, and it holds the DC link within 9.12 V across the day. Every figure comes from the accompanying code and can be regenerated.

1. Introduction

Fast charging and vehicle-to-grid technology run through the same piece of hardware. Between the battery pack of an electric vehicle and the DC link of a charger or a grid-tied inverter sits a bidirectional DC–DC converter, and it has to move power cleanly in both directions: pack to link when the vehicle feeds the grid and link to pack when the vehicle charges [1,2,3]. The converter is not the glamorous part of the system, but it is the part that decides whether the DC link stays put when a charging session starts, when the load steps, and when the power flow reverses. If the link sags or overshoots, everything downstream feels it.

Controlling that converter is harder than it looks. A boost-mode DC–DC converter has a right-half-plane zero, its small-signal behaviour changes with the operating point, and the components drift: the inductor value falls as the core saturates, the winding resistance rises as it heats, and the pack voltage wanders across the state of charge [4,5]. A fixed-gain linear controller tuned at one operating point gives up performance at others. Sliding-mode control was built for exactly this kind of problem. It forces the state onto a chosen surface and holds it there, and once the state is on the surface, the closed-loop behaviour stops depending on the parts of the model that were uncertain [6,7,8]. The price is chattering, the fast switching that a naive sliding law produces, which a boundary layer or a fixed-frequency pulse-width-modulated (PWM) implementation tames [9,10].

The central contribution of this paper is a single, fully specified bidirectional-converter case study that resolves a gap the converter-control literature usually leaves open: it puts a two-loop sliding-mode controller and a like-for-like PI cascade on the same 50 kW synchronous half-bridge and measures, on one plant and with released code, the four things that decide a V2G-capable design together rather than in isolation: the load-step recovery, the invariance under parameter drift, the two-quadrant power reversal, and the chattering cost of the boundary layer, closed with a real charging-demand profile. The novelty is not a new sliding surface but this controlled, reproducible head-to-head on a named converter, with the derivation and the implementation both carried to the time-varying reference, the comparison made fair at matched bandwidth, and every number regenerable. Concretely, the contributions are the following.

• A switching-level model of a synchronous half-bridge bidirectional converter, sized for a 50 kW fast charge and V2G duty between a 400 V pack and a 750 V link, is stated in a form that generalises to other ratings through a stated per-unit design procedure.
• A two-loop sliding-mode controller is derived term by term: an inner current loop on a sliding surface with a boundary layer and an outer PI voltage loop that sets the current reference, with the reference-slew feedforward carried in the implemented law so that the Lyapunov reaching-condition proof applies to the controller that produced the results, a measurement of how fast the reference actually moves during each transient, a practical sliding error bound for the approximate law that omits the term, and an explicit rule for choosing the boundary-layer width.
• The controller is compared like-for-like against a conventional PI cascade on the same plant under a load step, a deliberate parameter mismatch, and a two-quadrant power reversal (reversible pack current at a fixed-polarity DC link), with the PI cascade taken through the same reversal rather than assumed to fail; the chattering that the boundary layer suppresses is quantified against a pure discontinuous switching law under an equal switching implementation.
• The design is tested against a 24 h charging-demand profile taken from 41,213 real session records at the Newcastle Helix site, so the DC-link regulation is checked on a demand shape the hardware would actually see rather than a synthetic square wave, and a controller-gain sensitivity study shows the result is not knife-edge in the tuning.

The claim is kept narrow on purpose. The study is a simulation, the loss model is a stated budget rather than a bench measurement, and the sliding-mode controller does not beat the PI cascade on every axis. What it offers is a reproducible, verifiable comparison of the two control approaches on one fully specified bidirectional converter, with a real-world demand profile as the final test. Section 2 places the work against the literature, Section 3 gives the model and the controllers, Section 4 reports the results, and Section 5, Section 6 and Section 7 discuss the limits and what follows.

2. Related Work

2.1. Bidirectional DC–DC Converters for Vehicles

The non-isolated half-bridge converter used here is the workhorse of the field because it is cheap, efficient, and naturally bidirectional: the same two switches boost on the way out and buck on the way back [5,11]. Reviews of the topology space set out the trade between non-isolated designs like this one and isolated dual-active-bridge designs that add a transformer for galvanic isolation at the cost of parts and loss [5,12], and recent surveys of bidirectional converters for hybrid energy-storage systems in electric vehicles map the same non-isolated-versus-isolated space against efficiency and control complexity [13]. For on-board and charger-side conversion the non-isolated design is the common choice where isolation is provided elsewhere in the chain [1,14]. The same converter class carries fuel-cell and hydrogen-vehicle powertrains, where the DC–DC stage matches a low, stiff fuel-cell voltage to the traction link [12,15], which is why the converter question sits squarely inside the electric-and-hydrogen-mobility scope.

2.2. Fast Charging, V2G, and the DC Link

Extreme fast charging pushes tens to hundreds of kilowatts through the DC–DC stage, and the DC link becomes a shared, stiff node that several converters lean on [3]. Holding that link against constant-power loads is a known stability problem: a downstream converter that draws constant power looks like a negative resistance and can destabilise the link if the source-side control is weak [16,17]. V2G adds the reversal case, where the vehicle stops charging and starts exporting, so the converter has to cross zero power without a mode-switch glitch [2,18]. Energy-storage reviews make the same point from the battery side: the converter and its control set how hard the pack is worked and how steady the link stays [19,20]. DC-microgrid work frames the link voltage itself as the quantity to regulate [21].

2.3. Sliding-Mode and Nonlinear Control of Converters

Sliding-mode control of switching converters is a mature line, and it helps to organise it by how each branch handles the one problem that defines the method, chattering, because that is where the design choices and their costs live. The foundation is first-order sliding mode: a single surface, a discontinuous reaching term, and the invariance that follows once the state reaches the surface, so matched disturbances and parameter drift stop affecting the closed loop [6,7,22]. It moved from theory into switching-converter and electric-drive practice through the 1990s and 2000s [8,23,24], where the general design issues, surface selection, existence and stability, were worked out for DC–DC converters specifically [8]. The cost of the discontinuous term is chatter, and the branches divide by their remedy. The first keeps the first-order surface but softens or paces the switching: a boundary layer that replaces the sign function with a saturation, and fixed-frequency PWM realisations that pin the switching period so a gate drive can carry it [9,10]. That is the branch this paper’s controller sits in, and its known price is a thin residual band under mismatch, which Section 4.8 measures. The second raises the order of the sliding dynamics to get finite-time convergence and a continuous control that chatters less at the source: super-twisting and higher-order sliding modes [25], applied to DC–DC boost stages, including under the constant-power loads a fast charger presents, through hybrid backstepping and super-twisting laws [26]. The third reshapes the surface itself for finite-time and better-conditioned convergence, through non-singular terminal sliding-mode laws with variable, state-dependent gains demonstrated on DC–DC converters under full-parameter perturbation [27], and extends the invariance to mismatched as well as matched uncertainty through fractional-order second-order designs [28]. A fourth, more recent branch lifts the idea to the system level, coordinating voltage and power across the storage and distributed-generation inverters that share a link [29]. Read together, these branches trade complexity for a tighter guarantee: the boundary-layer approach is the simplest and the one a designer reaches for first, the higher-order and terminal designs buy finite-time convergence and mismatched-uncertainty coverage at the cost of more states and tuning, and the coordinated schemes operate a layer above the single converter. The present controller stays in the first branch deliberately, as the fair baseline against which those richer designs should be measured, and the discussion returns to them as the natural next step.

Against sliding mode sits model predictive control, which handles multi-objective converter problems by solving an optimisation each step but leans on an accurate model [30]; the averaged-model tools both families use trace back to state-space averaging [31,32,33,34,35]. Across all of this, what the converter-control literature less often does is put a sliding-mode design and a like-for-like PI cascade on one fully specified bidirectional converter and report the difference under load steps, parameter mismatch, and power reversal together, at a matched loop bandwidth and with a real demand profile as the closing test. That controlled comparison, not a new surface, is the gap this paper fills. Table 1 places this work against a representative set of studies.

Table 1. Where this study sits relative to representative converter and control work. A check mark (✓) means the feature is present, a circle (∘) indicates that it is partial or implicit, and a dash (−) indicates its absence.

Study	Bidirectional Converter	SMC Control	PI Baseline	Parameter Mismatch	Power Reversal	Real Demand Profile
Tan, Lai & Tse 2008 [8]	∘	✓	∘	∘	−	−
Tan et al. 2005 [9]	−	✓	∘	∘	−	−
Oucheriah & Guo 2013 [10]	−	✓	∘	✓	−	−
Gorji et al. 2019 [5]	✓	−	−	−	∘	−
Du et al. 2010 [11]	✓	−	∘	−	✓	−
Monteiro et al. 2016 [2]	✓	−	∘	−	✓	−
Vazquez et al. 2017 [30]	∘	−	∘	∘	−	−
This work	✓	✓	✓	✓	✓	✓

3. Materials and Methods

3.1. Converter and Ratings

The plant is a synchronous half-bridge bidirectional DC–DC converter (Figure 1). The low-voltage side is an electric-vehicle battery pack at a nominal 400 V. The high-voltage side is a DC fast-charge link held at 750 V—the kind of link a grid-tied V2G inverter maintains. A single inductor ($L=250 \mathsf{\mu }\mathrm{H}$) sits on the pack side, and a capacitor ($C_H=470 \mathsf{\mu }\mathrm{F}$) sits across the link. The two SiC MOSFETs switch at 20 kHz, and the converter is rated at 50 kW, which matches the rapid chargers at the site whose data closes the study. Boost operation moves power from pack to link (discharge, V2G); buck operation moves it from link to pack (charge). The two directions use the same two switches, so there is no reconfiguration when power reverses.

Figure 1. The synchronous half-bridge bidirectional converter. A 400 V pack drives a 250 $\mathsf{\mu }$$\mathrm{H}$ inductor carrying $i_L$ into the switch node ($v_A$); two n-channel SiC MOSFETs—S1 (high side) and S2 (low side)—gated by the duty (d) and its complement switch at 20 kHz; a 470 $\mathsf{\mu }$$\mathrm{F}$ capacitor ($C_H$) holds the 750 V link voltage ($v_H)$ that a grid-tied V2G inverter maintains. Boost operation ($u=\overline{d}$) delivers power to the link; buck operation charges the pack. The same two switches serve both directions, so no reconfiguration is needed when power reverses.

Although the study is conducted at one operating point, 50 kW between 400 V and 750 V, the design is not tied to that rating. The plant model (1) and the control law (2)–(5) are written in physical variables, and the design generalises through a short per-unit procedure: fix the conversion ratio ($M=V_H/V_L$) and the rated current ($I_R=P/V_L$), then scale the inductor and capacitor to the chosen switching-ripple and link-ripple limits and set the surface rate (($\lambda$)) from the desired inner-loop bandwidth relative to $f_{sw}$, the reaching gain ($\eta$) from the worst-case duty slew ($v_H/L$), and the boundary layer $\varphi$ as a fixed fraction of $I_R$ (here, $\varphi =8\mathrm{A}\approx 0.06I_R$). The outer PI gains follow from the link time constant ($C_H{v}_H/I_R$). A converter at a different power or voltage is therefore re-tuned by the same recipe rather than redesigned, which the gain sensitivity of Section 4.9 supports by showing the response is stable across a wide gain range. Table 2 collects the converter, controller, and loss-model parameters in one place so the study can be rebuilt exactly.

Table 2. Converter, controller, and loss-model parameters.

Group	Parameter	Value
Power stage	Pack voltage ($V_L$)	400 V
	DC-link setpoint ($V_H^{*}$)	750 V
	Rated power	50 kW
	Inductor (L)	250 μH
	Link capacitor ($C_H$)	470 μF
	Switching frequency ($f_{sw}$)	20 kHz
Inner SMC loop	Surface rate ($\lambda$)	$2.5\times {10}^4$ s−1
	Reaching gain ($\eta$)	$2.0\times {10}^4$ A s−1
	Boundary layer ($\varphi$)	8 A
Outer voltage loop	Proportional ($k_p$)	3.0 A/V
	Integral ($k_i$)	4500 A/(V · s)
	Current limit	±180 A
PI baseline	Inner current ($k_{pc}$, $k_{ic}$)	$3\times {10}^{-3}$ , 9
Loss model	MOSFET ($R_{ds}$)	20 mΩ
	Inductor ($R_L$)	15 mΩ
	Ref. switching energy	3.75 mJ/device
	Fixed loss	120 W

3.2. Averaged Model

Write the pack-side inductor current as $i_L$ and the link voltage as $v_H$, and let $d\in [0,1]$ be the duty of the low-side switch. Averaging the two switched sub-intervals of the synchronous half-bridge over a switching period, in the standard state-space-averaging sense [4,31,33], gives the boost-form model:

$$L{\displaystyle \frac{\mathrm{d}{i}_L}{\mathrm{d}t}}=V_L-(1-d)v_H-R_L{i}_L,C_H{\displaystyle \frac{\mathrm{d}{v}_H}{\mathrm{d}t}}=(1-d)i_L-i_{\mathrm{load}},$$

(1)

where $V_L$ is the pack voltage, $R_L$ is the inductor copper resistance, and $i_{\mathrm{load}}$ is the current the link feeds downstream. The sign of $i_L$ sets the power direction, so (1) covers charge and discharge in one set of equations. The right-half-plane zero of the boost mode lives in the $v_H$ equation, which is why a current-mode inner loop, fast and local to $i_L$, is the right structure to wrap the slower voltage loop around [4,31].

3.3. Two-Loop Sliding-Mode Control

The controller has two nested loops (Figure 2). The inner loop is a sliding-mode loop and acts on the current; the outer loop is a proportional-integral law on the link voltage that produces the current reference.

Figure 2. Two-loop control architecture with standard summing junctions (+ forward input, − feedback). The outer PI loop (Equation (5)) turns the link-voltage error ($e_v=V_H^{*}-v_H$) into the current reference ($i_{\mathrm{ref}}$); the inner sliding-mode loop (Equations (2)–(4)) turns the current error $e_i=i_{\mathrm{ref}}-i_L$ into the duty (d), driving the inductor current onto the sliding surface. The two feedbacks are measurements separate from the converter: the link voltage ($v_H$) is tapped at the output and returned to the outer junction, and the inductor current ($i_L$) is tapped as a converter state and returned to the inner junction, on distinct lanes that cross no block. The block shading (blue for the setpoint, purple for the two controllers, green for the converter) only groups the stages and carries no quantitative meaning; solid arrows are the forward signal path and the two lower arrows are the voltage and current feedback. The inner loop is fast and local, which lets the outer loop stay simple.

For the inner loop, we define the sliding surface as the current error, i.e.,

$$s=i_L-i_{\mathrm{ref}}.$$

(2)

Because the surface depends on the reference, its derivative is $\dot{s}={\dot{i}}_L-{\dot{i}}_{\mathrm{ref}}$, so setting $\dot{s}=0$ and solving (1) for the duty gives the equivalent control, the duty that would hold the state on the surface in the ideal case, i.e.,

$$d_{\mathrm{eq}}=1-{\displaystyle \frac{V_L-R_L{i}_L-L{\dot{i}}_{\mathrm{ref}}}{v_H}}.$$

(3)

The $L{\dot{i}}_{\mathrm{ref}}$ term is the feedforward of the reference slew; it is what makes the equivalent control exact when $i_{\mathrm{ref}}$ moves, as it does during a load step, and it vanishes only for a constant reference. This term is carried in the implementation, not dropped. Every number reported in Section 4 comes from (3) as written, so the control law that produced the results is the same one the Lyapunov argument of Section 3.4 is written for. Section 3.5 measures ${\dot{i}}_{\mathrm{ref}}$ during each transient, shows why the earlier quasi-static shortcut cannot be justified by a time-scale argument, and gives the tracking-error bound that applies if the term is dropped anyway.

The derivative is not obtained by differentiating a measured signal. Because $i_{\mathrm{ref}}$ is produced by the outer PI (5), its slew is available in closed form as ${\dot{i}}_{\mathrm{ref}}=k_i{e}_v-k_p{\dot{v}}_H$ with $e_v=V_H^{*}-v_H$, and ${\dot{v}}_H=\left[(1-d)i_L-i_{\mathrm{load}}\right]/C_H$ follows from the second row of (1) using quantities the controller already has. The term is set to zero whenever the reference sits on its $\pm 180\mathrm{A}$ clamp, where ${\dot{i}}_{\mathrm{ref}}=0$ by construction, and whenever the reference is an externally commanded step, which is not differentiable; the reversal test of Section 4.4 is that second case, and the duty saturation discussed below is what governs it.

A reaching term drives the state onto the surface and rejects the mismatch the equivalent control does not know about. To keep the switching finite rather than infinitely fast, the discontinuous $sign\left(s\right)$ is replaced by a saturation across a boundary layer of half-width $\varphi$, i.e.,

$$d_{\mathrm{sw}}=-{\displaystyle \frac{L}{v_H}}\left[\lambda s+\eta sat\left({\displaystyle \frac{s}{\varphi }}\right)\right],d=clip\left(d_{\mathrm{eq}}+d_{\mathrm{sw}},0,1\right),$$

(4)

with $\lambda$ setting how fast the surface is approached and $\eta$ representing the reaching gain. The boundary layer trades a thin band of steady-state error for a bounded switching frequency, the standard chatter fix [9,10]. The gains used here are $\lambda =2.5\times {10}^4$ s⁻¹, $\eta =2.0\times {10}^4$ A s⁻¹, and $\varphi =8$ A.

The outer loop closes the link voltage. With the inner loop tracking $i_{\mathrm{ref}}$ quickly, the link behaves like a capacitor charged by a controllable current, and a PI law, i.e.,

$$i_{\mathrm{ref}}=k_p(V_H^{*}-v_H)+k_i\int (V_H^{*}-v_H)\mathrm{d}t,$$

(5)

holds $v_H$ at its setpoint of $V_H^{*}=750\mathrm{V}$, with $k_p=3.0$ A V⁻¹ and $k_i=4500$ A V⁻¹ s⁻¹ and $i_{\mathrm{ref}}$ limited to ±180 A. Because $i_{\mathrm{ref}}$ can take either sign, the same controller sources or sinks pack current, so charge, discharge, and the reversal between them are one continuous control problem.

The choice of a sliding-mode inner loop with a PI outer loop, rather than sliding mode on both loops, is deliberate. The inner loop is where invariance is worth having because it is the current dynamics that carry the right-half-plane zero and the drifting inductor, so putting the sliding surface on $i_L$ is what buys the robustness this paper measures. The outer loop regulates the link voltage, a slow state set by the link capacitance, where a well-damped PI is adequate and avoids a second discontinuous term. A sliding-mode outer loop would add a second switching surface and a second chattering source, with little to gain on a state that already moves slowly. The reviewer’s concern that a PI outer loop can hand the inner loop a reference that is, itself, jittery and thereby add to the inner-loop burden is real; it is contained here in three ways. The outer PI carries no derivative term, so it does not differentiate measurement noise into the reference; the reference is hard-limited to ±180 A, so a transient cannot demand an unbounded current; and the inner loop is roughly two orders of magnitude faster than the outer loop, so the reference is quasi-static on the inner-loop time scale and the inner loop tracks it without a fight. The gain sensitivity study of Section 4.9 confirms that the closed loop tolerates a wide range of outer-loop gains without the reference destabilising the inner loop.

3.4. Reaching Condition

The reaching term is what guarantees the surface is actually attained. Take the Lyapunov candidate as $V=\frac{1}{2}{s}^2$, so $\dot{V}=s\dot{s}$ with $\dot{s}={\dot{i}}_L-{\dot{i}}_{\mathrm{ref}}$. Substituting the current dynamics (1) under the control ((3) and (4)), the reference-slew term is carried by the feedforward and cancels exactly, so outside the boundary layer, where $sat(s/\varphi )=sign\left(s\right)$,

$$\dot{V}=s\dot{s}=-\lambda s^2-\eta \left|s\right|<0\mathrm{for}s\ne 0,$$

(6)

so V decreases and the state is driven onto the surface in finite time; the $\eta \left|s\right|$ term sets the reaching speed, and the $\lambda s^2$ term sharpens it as the surface is approached. Because (6) is obtained from the same equivalent control the implementation uses, it applies to the controller that produced every result in Section 4, and it holds whatever the reference does: no bound on ${\dot{i}}_{\mathrm{ref}}$ is needed because the term is cancelled rather than dominated. Inside the boundary layer, the switching term becomes the linear feedback ($-\eta s/\varphi$), which turns the ideal sliding motion into a fast first-order approach with a small, bounded band around $s=0$ instead of infinitely fast switching. This is the standard trade behind (4): a thin steady-state band in exchange for a finite switching frequency the gate drive can deliver [9,10].

The analysis assumes the duty is in the interior of its range, i.e., $0<d<1$; the clip in (4) enforces the physical limits. In steady operation and through the load step, the duty stays well inside $[0,1]$, so the sliding analysis applies directly. The one place the duty reaches a limit is the deliberate full-swing power reversal, where it touches zero for a few tens of microseconds while the pack drives the current from $+125$ to $-125$ A. While the duty is clipped, the reaching term is saturated and the surface is not actively enforced; the state re-enters the sliding regime the moment the duty comes off the limit, so the reversal completes cleanly, as the reversal test confirms. The valid operating region for the invariance guarantee is therefore the unsaturated set of $0<d<1$, which the design occupies except at that reversal instant.

3.5. How Fast the Reference Actually Moves

The feedforward in (3) is kept because the usual argument for dropping it does not hold up once the term is measured. That argument runs as follows: the outer loop is two orders of magnitude slower than the inner one, so ${\dot{i}}_{\mathrm{ref}}$ is negligible. The separation of time scales is real, but it constrains the closed-loop bandwidth of the outer loop, not the peak slew of its output during a transient, and those are different quantities. When the link voltage falls, the proportional path of (5) differentiates that fall straight into the reference. At the instant a load step of $\Delta i_{\mathrm{load}}$ hits, the link derivative jumps to ${\dot{v}}_H=-\Delta i_{\mathrm{load}}/C_H$, and the reference slew follows immediately,

$$|{\dot{i}}_{\mathrm{ref}}{|}_{max}\simeq {\displaystyle \frac{k_p\Delta i_{\mathrm{load}}}{C_H}}+k_i{\left|e_v\right|}_{max},$$

(7)

which, for the 40 to 100 percent step here, i.e., $\Delta i_{\mathrm{load}}=40$ A into $C_H=470$ μF with $k_p=3$ A V⁻¹, gives about $2.6\times {10}^5$ A s⁻¹ before the integral path adds anything. Neither the outer-loop bandwidth nor the inner-to-outer ratio appears in (7). A slow loop with a finite proportional gain still produces a fast reference edge when its input moves fast.

Table 3 reports the measured peak against the reaching gain of $\eta =2.0\times {10}^4$ A s⁻¹ for every transient in the paper, and Figure 3a plots the load-step case. The peak is $2.78\times {10}^5$ A s⁻¹, which is $13.9\eta$, and $|{\dot{i}}_{\mathrm{ref}}|$ stays above $\eta$ for $0.99$ ms, which is longer than the $0.71$ ms the link takes to settle. Under a constant-power load and under the +40 percent inductance mismatch, the picture is the same, i.e., $14.0\eta$ and $14.4\eta$. Even the slow Helix demand profile, whose hourly steps are the mildest disturbance in the study, reaches $5.6\eta$ and exceeds $\eta$ on one-fifth of its samples. Only once the link has settled does the quasi-static picture hold, and there the margin is very wide: $|{\dot{i}}_{\mathrm{ref}}|$ falls to $4.5\times {10}^{-6}$ A s⁻¹, ten orders of magnitude under $\eta$. The conclusion is that the reaching condition of $\eta >|{\dot{i}}_{\mathrm{ref}}|$ would be violated by more than an order of magnitude and for the whole of the interval the paper is measuring if the feedforward were dropped. That is the reason it is not.

Table 3. Measured reference slew against the reaching gain of $\eta =2.0\times {10}^4$ A s⁻¹. Peaks are taken over the 2 ms window following the disturbance; the settled row is the same run after 10 ms.

Transient	Peak $|{\dot{\mathit{i}}}_{\mathbf{ref}}|$ (A/s)	Ratio to $\mathit{\eta }$	Time Above $\mathit{\eta }$ (ms)
Load step, 40 to 100% rated	$2.78\times {10}^5$	13.9	0.99
Load step, constant-power load	$2.81\times {10}^5$	14.0	1.19
Load step, $L+40\%$, $R_L+50\%$	$2.89\times {10}^5$	14.4	1.13
Helix demand profile	$1.13\times {10}^5$	5.6	20% of samples
Settled operation	$4.5\times {10}^{-6}$	$2\times {10}^{-10}$	0
Power reversal, $+125$ to $-125$ A	commanded step: ${\dot{i}}_{\mathrm{ref}}$ impulsive; see text

Figure 3. Why the reference-slew term is carried in the implemented law. (a) The reference slew $|{\dot{i}}_{\mathrm{ref}}|$ produced by the outer PI during the 40 to 100 percent load step, against the reaching gain $\eta$. The peak is $2.78\times {10}^5$ A s⁻¹, $13.9\eta$, and the shaded region is the 0.99 ms over which the quasi-static reaching condition of $\eta >|{\dot{i}}_{\mathrm{ref}}|$ would fail. (b) The sliding variable through the same step. With the feedforward of (3), the surface is held to 0.03 A without it, the state is pushed into a practical sliding band that peaks at 9.50 A, inside the 10.3 A bound of (9) and well outside the boundary layer ($\varphi$).

The reversal of Section 4.4 is a different case and is worth separating because there, $i_{\mathrm{ref}}$ is an externally commanded step rather than the output of the outer loop. Its derivative is impulsive, so no finite $\eta$ and no finite feedforward can meet it, and what limits the response is the converter rather than the control law. The inductor sets that ceiling: with the link stiff at 750 $\mathrm{V}$ and the pack at 400 $\mathrm{V}$, the fastest available current slew on the buck side is $|V_L-v_H|/L=1.4\times {10}^6$ A s⁻¹, so a 250 $\mathrm{A}$ swing cannot complete in less than $0.179$ $\mathrm{m}$$\mathrm{s}$. The measured reversal takes $0.255$ $\mathrm{m}$$\mathrm{s}$ with the duty resting on its lower limit for 139 $\mathsf{\mu }$$\mathrm{s}$, which is the saturated regime already identified below: the surface is not enforced while the duty is clipped, and sliding resumes when it comes off the limit. Because a piecewise-constant reference has zero derivative everywhere except at the discontinuity, the feedforward contributes nothing here, and the reversal result is numerically identical to the term enabled or disabled.

Raising $\eta$ instead of adding the feedforward was considered and rejected. Meeting $\eta >2.8\times {10}^5$ A s⁻¹ requires the reaching gain to be fourteen times larger, which moves the near-surface pole ($\lambda +\eta /\varphi$) from $2.75\times {10}^4$ s⁻¹ to about $6\times {10}^4$ s⁻¹. That is within a factor of two of the 20 $\mathrm{k}$$\mathrm{Hz}$ carrier, so the inner loop would no longer be fast relative to the modulator that has to realise it, and the chatter the boundary layer exists to control would come back. The feedforward cancels the same term at no cost in loop gain, which is why it is the route taken.

3.6. Bound if the Feedforward Is Dropped

For completeness and because a quasi-static implementation remains a reasonable engineering choice on hardware without a usable ${\dot{v}}_H$ estimate, the approximate law is analysed on its own terms rather than being justified by the exact one. Drop the $L{\dot{i}}_{\mathrm{ref}}$ term from (3) and let the true plant carry an inductance ($L_p$) and a copper resistance ($R_p$) that differ from the values the controller assumes. Substituting the resulting duty into the true current dynamics gives

$$\dot{s}=-\theta \left[\lambda s+\eta sat\left(\frac{s}{\varphi }\right)\right]+w,\theta ={\displaystyle \frac{L}{L_p}},w=-{\dot{i}}_{\mathrm{ref}}+{\displaystyle \frac{(R_L-R_p)i_L}{L_p}},$$

(8)

so the neglected slew enters exactly as a matched disturbance, lumped with the parametric error into $\left|w\right|\le W$. The reaching term no longer dominates w, so ideal sliding is lost, and what remains is practical sliding: with $V=\frac{1}{2}{s}^2$ and $\left|s\right|>\varphi$, $\dot{V}\le -\theta \lambda s^2-(\theta \eta -W)\left|s\right|$, which is negative whenever $\left|s\right|$ exceeds the ultimate bound, i.e.,

$${\left|s\right|}_{\infty }\le max\left\{\varphi ,{\displaystyle \frac{W-\theta \eta }{\theta \lambda }}\right\},W=|{\dot{i}}_{\mathrm{ref}}{|}_{max}+{\displaystyle \frac{|R_L-R_p|I_{max}}{L_p}}.$$

(9)

Inside the layer, the same substitution gives the tighter ${\left|s\right|}_{\infty }\le W/\left[\theta (\lambda +\eta /\varphi )\right]$, so the state is not driven to the surface, but it is driven into a band around it whose width is set by the slew the controller ignores, and it stays there. Table 4 evaluates (9) with the measured slews of Table 3 and checks it against the peak $\left|s\right|$ from the simulation. The bound holds in every case, with 8 to 12 percent of margin left over. At the nominal load step, it predicts $\left|s\right|\le 10.3$ A, which is about 8 percent of the rated pack current, against $9.50$ $\mathrm{A}$ measured; Figure 3b shows both traces with the bound drawn on. The corresponding cost at the link is small but real: the dip grows from 2.42 to 2.66 percent, so a quarter of a percentage point of link voltage buys the simpler implementation. Once the transient passes, W collapses to the settled slew, and the band closes to nothing, which is why the quasi-static law still shows exact steady-state tracking.

Table 4. Ultimate bound (9) for the quasi-static law, evaluated with the measured slews of Table 3, against the peak sliding variable observed in simulation. $\theta =L/L_p$.

Case	$\mathit{\theta }$	W (A/s)	Bound (A)	Measured ${\left|\mathit{s}\right|}_{max}$ (A)	% of ${\mathit{I}}_{\mathit{R}}$
Load step, nominal	1.000	$2.78\times {10}^5$	10.31	9.50	8.2
Load step, constant-power load	1.000	$2.81\times {10}^5$	10.42	9.69	8.3
Load step, $L+40\%$, $R_L+50\%$	0.714	$2.93\times {10}^5$	15.59	14.21	12.5
Helix demand profile	1.000	$1.13\times {10}^5$	4.10	3.77	3.3
Settled operation	1.000	$4.5\times {10}^{-6}$	<${10}^{-9}$	<${10}^{-9}$	0

3.7. Choosing the Boundary-Layer Width

The boundary-layer half-width ($\varphi$) is a design quantity, not an arbitrary one, and it is worth saying how it is chosen and what replacing the discontinuous sign with the saturation does to robustness. With an exact equivalent control, the surface is held by $d_{\mathrm{eq}}$ alone, so at steady state, $\varphi$ has no effect; its role appears only under the model error the equivalent control does not know, where the linear near-surface feedback ($-\eta s/\varphi$) has to carry the correction. That fixes the trade at both ends. A narrow layer gives a high near-surface gain that approaches the discontinuous law and, at a finite sampling and PWM rate, re-introduces the chatter the boundary layer was meant to remove. A wide layer lowers that gain and leaves a larger residual current band under a persistent mismatch. The width is therefore set as the smallest value that keeps the switching bounded at the PWM rate while still covering the expected steady-state current-error band; here, $\varphi =8$ A, which is about six percent of the rated pack current, sits in that window. The robustness cost of the substitution is confined to the thin band: for any disturbance large enough to keep $\left|s\right|>\varphi$, the motion is fully sliding, and the matched uncertainty is rejected exactly as the discontinuous law would; only inside the band is invariance softened to a fast linear approach. Section 4.8 measures both ends of this trade. State-dependent variable-gain and non-singular terminal sliding-mode designs offer a principled way to adapt the near-surface gain rather than fix it and have been analysed specifically for DC–DC converters under full-parameter perturbation [27]; that is a natural next step beyond the fixed-$\varphi$ law used here.

3.8. Baseline PI Cascade

For a fair comparison, the same converter is controlled by a conventional two-loop PI cascade: the same outer-voltage PI feeding an inner PI current loop that sets the duty around the nominal operating point of $d_0=1-V_L/v_H$. The inner-current PI uses $k_{pc}=3\times {10}^{-3}$ and $k_{ic}=9$, tuned for a stable, well-damped response. This is the controller a designer reaches for first, and it is the fair benchmark to beat.

3.9. Loss and Efficiency Model

Efficiency comes from a stated loss budget, not a bench measurement. Three load-dependent terms and one fixed term are summed. The conduction loss is taken per switch from the RMS current: in the synchronous half-bridge, the inductor current ($i_L$) flows through the low-side device for a fraction (d) of the switching period and through the high-side device for the complementary fraction ($1-d$), so each device dissipates $R_{ds}{i}_L^2$ times its own conduction duty and the two-device total is $R_{ds}(i_L^{2}d+i_L^2(1-d))=R_{ds}{i}_L^2$, since only one device carries $i_L$ at a time. To that are added the inductor copper ($R_L{i}_L^2$); the switching loss ($2E_{sw}{f}_{sw}$) with the per-device switching energy ($E_{sw}$) scaled by the blocked voltage and the switched current; and a fixed 120 W for gate drive, auxiliary supplies, and sensing. The device parameters are $R_{ds}=20 \mathrm{m}\mathsf{\Omega }$, $R_L=15 \mathrm{m}\mathsf{\Omega }$, and a reference switching energy of 3.75 mJ per device at 750 V and 125 A. These are representative SiC values, stated so the efficiency curve can be recomputed for other devices.

3.10. Real-World Duty Profile from the Newcastle Helix Dataset

The regulation tests above use idealised steps. The closing test drives the converter with a charging-demand shape taken from real records. The Newcastle Helix site, an urban innovation district beside Newcastle University with a live smart-grid and open-data testbed [36,37], logged 41,213 valid charging sessions across six rapid and fast chargers between 18 March 2021 and 22 July 2026. The observed session records give a mean delivered energy of 24.81 kWh, a mean session power of 33.85 kW, and a strongly daytime demand shape that peaks near mid-day. The hourly session counts, a measured quantity, are scaled to the converter’s 50 kW rating to form a 24-point power-demand reference, and the converter is asked to track that reference while holding the DC link. Two things about this test must be stated so it is not over-read. It is a demand shape derived from the real dataset, not a bench measurement of this converter, and the 24 hourly points are replayed on a compressed timescale, with one millisecond standing for one hour, so the whole day plays out in 24 ms of simulation; this is a deliberate compression that makes the switching-level run tractable, not a literal 24 h dynamic simulation. Because the demand changes far more slowly than the control bandwidth, whether at real speed or compressed, the compression faithfully reproduces the shape-tracking task without changing what the controller has to do at each hourly transition; what the test shows is that the link holds through the rise and fall of a real demand shape, and the reported deviation should be read as the response to those hour-to-hour changes, not as a full-bandwidth 24 h transient.

3.11. Computing Environment and Reproducibility

The model, both controllers, the loss budget, and the plotting are written in Python 3.11 (Python Software Foundation, Wilmington, DE, USA) with the NumPy 2.5.3 and SciPy libraries 1.18.1. The switching-level loops integrate at a 100 $\mathrm{n}$$\mathrm{s}$ step. Seeds are fixed. The complete code is provided with the manuscript. Every number, table, and figure regenerates from dcdc_sim.py, round2_sims.py, and chatter_r2.py, with the control-dependent results produced by regen_ff.py and regen_paramvar.py, which run the sliding-mode law with the reference-slew feedforward of (3) enabled. The slew measurements of Table 3 and the bound check of Table 4 come from iref_slew.py; the figures follow from make_figs.py, make_round2_figs.py, and make_slew_fig.py. Each script writes a JSON result file, so any number in the paper can be traced to the run that produced it. Both control laws, i.e., the exact and quasi-static control laws, are kept in the released code behind a single flag, so the comparison in Section 3.6 can be reproduced as well as the reported results.

4. Results

4.1. Efficiency and Losses

Figure 4 shows converter efficiency against through-power. The curve peaks at 98.69 percent near 23 kW, where the load-dependent losses have grown enough to dominate the fixed 120 W but the conduction term has not yet taken over, and it falls to 98.39 percent at the rated 50 kW as conduction and switching losses climb. Table 5 breaks the loss into its parts at five power levels. At light load, the fixed term is most of the loss; at rated power, the per-switch conduction is 313 W of the 817 W total. Figure 5 shows the same breakdown as stacked bars, where the per-switch conduction overtakes the fixed term above roughly 35 kW and dominates at rated power. The efficiency band, 98.3 to 98.7 percent across the working range, is what a SiC design of this size is expected to reach, and the point of stating the budget is that a reader can substitute different device numbers and redraw the curve.

Figure 4. Converter efficiency against through-power under the stated SiC loss budget, with conduction taken per switch from the RMS current. Peak efficiency is 98.69 percent near 23 kW; rated efficiency at 50 kW is 98.39 percent.

Table 5. Loss breakdown at five power levels (W), from the stated loss budget.

Power (kW)	Conduction	Inductor Copper	Switching	Fixed	Total Loss	Efficiency (%)
10	13	9	30	120	172	98.31
20	50	38	60	120	268	98.68
30	113	84	90	120	407	98.66
40	200	150	120	120	590	98.55
50	313	234	150	120	817	98.39

Figure 5. Loss breakdown against power. Per-switch conduction overtakes the fixed term above roughly 35 kW and dominates at rated power.

4.2. Load-Step Response: Sliding-Mode Against PI

Figure 6 shows the link voltage when the load steps from 40 to 100 percent of rated power at 4 ms. The sliding-mode controller pulls the link back to 750 V in 0.71 ms, with a worst dip of 2.42 percent (about 18 V). The PI cascade, tuned to be stable and well damped, takes 1.75 ms and dips 4.20 percent (about 31 V). Both settle to zero steady-state error because both carry an integral term in the outer loop. The sliding-mode controller is therefore about 2.5 times faster to settle and dips a little over half as far. The reason is structural: the inner sliding-mode loop drives the current onto its surface almost immediately, so the outer loop sees a near-ideal current source and can recover the link faster, while the PI inner loop has its own finite bandwidth that slows the whole cascade.

Figure 6. DC-link voltage under a 40 to 100 percent load step at 4 ms. Sliding-mode control settles in 0.71 ms with a 2.42 percent dip; the PI cascade takes 1.75 ms and dips 4.20 percent. The dotted horizontal line marks the 750 V setpoint; the vertical dotted line marks the load-step instant at 4 ms.

One might ask whether that speed is just a bandwidth artefact, the sliding-mode inner loop being simply tuned faster than the PI current loop. To rule that out, the PI current loop was retuned to the sliding-mode inner-loop pole. The near-surface dynamics of (4) give an effective inner pole at $\lambda +\eta /\varphi \approx 2.75\times {10}^4$ s⁻¹; matching the PI current loop’s crossover to it raises its proportional gain from $k_{pc}=3\times {10}^{-3}$ to $9.2\times {10}^{-3}$. With that bandwidth-matched inner loop, the PI cascade settles the same load step in 1.82 ms with a 4.01 percent dip, essentially unchanged from the standard tuning (1.75 ms, 4.20 percent). The bottleneck is not the inner-loop bandwidth but the outer voltage loop and the finite link capacitor, which the two cascades share; the sliding-mode advantage comes from the reaching law forcing the large current swing directly and from the near-ideal current source the inner loop presents, not from a higher inner-loop bandwidth. The comparison is therefore fair at matched bandwidth, and the gap stands.

Figure 7 shows what the inner loop is doing underneath that response. The top panel is the sliding surface (s), i.e., the current error. From the initial condition, it is driven into the boundary layer within a fraction of a millisecond and stays there, jumping only briefly at the 4 ms step before returning inside $\pm \varphi$. The bottom panel is the duty, which stays well inside $[0,1]$ around 0.47, the value $1-V_L/V_H^{*}$ that the equivalent control predicts. The loop is neither saturating the duty nor chattering across the full range; it is sitting on the surface. Figure 8 zooms in on the current itself around the step and shows the inductor current riding its reference: the outer loop lifts the reference to meet the new load and the inner loop tracks it with almost no lag, which is the mechanism behind the fast link recovery.

Figure 7. Inner-loop behaviour during the load step. (Top): The sliding surface (s) is driven into the boundary layer $\pm \varphi$ and held there. (Bottom): The duty stays inside $[0,1]$ near its equivalent-control value, so the loop rides the surface rather than chattering across the range.

Figure 8. Detail around the 4 ms step: the inner sliding-mode loop tracks the outer-loop current reference with almost no lag as the reference rises to meet the new load.

4.3. Robustness to Parameter Mismatch

The invariance claim is tested directly. Figure 9 repeats the same load step, but now the true inductor is 40 percent larger, and its resistance is 50 percent higher than the value the controllers were designed around—the kind of drift a hot, partly saturated inductor shows. The sliding-mode response barely moves: it settles in 0.72 ms against 0.71 ms nominal, and its dip grows only from 2.42 to 2.68 percent. The PI cascade degrades more, with its dip growing from 4.20 to 4.64 percent. This is the property sliding-mode control is chosen for. Once the current is on the sliding surface, the matched part of the model uncertainty stops reaching the closed loop, so a large inductor error costs almost nothing. The PI cascade has no such guarantee and leans on the plant matching its design point.

Figure 9. The same step with the inductor 40 percent larger and its resistance 50 percent higher than assumed. The sliding-mode response is almost unchanged (dip from 2.42 to 2.68 percent); the PI cascade degrades further. The dotted horizontal line marks the 750 V setpoint.

It is worth being precise about what the invariance does and does not remove because a small link dip remains even for the sliding-mode controller and that can look like a contradiction. Invariance is a property of the inner current loop: once $i_L$ is on the surface, its tracking is insensitive to the matched inductor and resistance uncertainty. The link-voltage dip during a load step is a different quantity. When the load current jumps, the extra energy must be resupplied to the finite link capacitor ($C_H$) through the inductor, and the depth of the dip is set by $C_H$, by how fast the outer loop raises the current reference, and by the inductor current slew the pack voltage can support, not by the inductor mismatch. That is exactly why the dip is small in absolute terms (2.42 percent) and why it barely grows to 2.68 percent under a 40-percent inductor error: the mismatch enters only through the second-order path of a slightly slower current build-up, while the first-order cause of the dip, the capacitor being momentarily undersupplied, is unchanged. A larger $C_H$ or a faster outer loop would shrink the dip further; the sliding-mode structure is what keeps that dip from growing when the plant drifts.

One mismatch case is not enough to characterise robustness, and it is worth being careful about what “more robust” means. Table 6 sweeps the inductance and the copper resistance one at a time and together and reports each controller’s dip alongside its change relative to its own nominal dip, which is the fair way to compare. Two things stand out, and one of them corrects an over-strong reading of the earlier single case. Against the resistance error, the sliding-mode controller is almost perfectly invariant: a 50 percent change in $R_L$ moves its dip by 0.4 percent because $R_L$ enters through the same channel as the control and is exactly the matched uncertainty a first-order sliding surface rejects. Against the inductance error, it is not: a 40 percent change in L moves the sliding-mode dip by about 10.5 percent, and in relative terms, that is not smaller than the PI cascade’s 10.1 percent because L multiplies the control input itself so changes the plant for both controllers rather than entering as a matched disturbance. What stays true across every case is the absolute margin: the sliding-mode dip is smaller than the PI dip in all of them, from 2.24 against 3.93 percent to 2.68 against 4.64 percent. The honest summary is that the sliding-mode structure buys near-exact rejection of the matched resistance and pack-voltage drift and a consistently smaller absolute dip, not a smaller relative sensitivity to every parameter; the inductance, which is an input-gain uncertainty, is the one a first-order surface does not fully cover, which is exactly the mismatched case the fractional-order and terminal designs of the discussion are built to handle.

Table 6. Load-step dip under one-at-a-time and combined parameter mismatch, each controller against its own nominal (SMC of 2.42 % and PI of 4.20%). The relative change is the fair robustness measure.

Mismatch	SMC Dip (%)	SMC $\mathbf{\Delta }$ (%)	PI Dip (%)	PI $\mathbf{\Delta }$ (%)
Nominal	2.42	—	4.20	—
L$+40\%$	2.67	$+10.5$	4.63	$+10.1$
L$-40\%$	2.24	$-7.5$	3.93	$-6.6$
$R_L$$+50\%$	2.43	$+0.4$	4.22	$+0.3$
$R_L$$-50\%$	2.41	$-0.4$	4.19	$-0.3$
L$+40\%$, $R_L$$+50\%$	2.68	$+11.0$	4.64	$+10.5$

“—” marks the nominal (reference) case, whose change relative to itself is zero by definition.

A separate question is the load itself. The steps above drive the link with a current step referenced to the nominal 750 V. A fast charger, though, is closer to a constant-power load: the downstream stage draws a set power, so its current rises as the link voltage sags, the negative-incremental-resistance behaviour that is a known source of DC-link instability [16,17,26]. Re-running the same 40-to-100-percent step with the load modelled as true constant power, i.e., $i_{\mathrm{load}}=P/v_H$ rather than $P/750$, the sliding-mode controller holds the link almost as well: the dip grows from 2.42 to 2.52 percent and the settling from 0.71 to 0.74 ms. The inner current loop is fast enough that the extra energy the constant-power load pulls during the sag is resupplied before it can run away, so the destabilising negative resistance does not get a foothold. The current-step and constant-power results are close because the sag is small; a converter with a softer link or a slower loop would show the difference more sharply.

4.4. Two-Quadrant Power Reversal

V2G needs the converter to cross from delivering power to absorbing it smoothly. The operation is two-quadrant: the pack current reverses sign while the DC-link voltage keeps a fixed polarity, so the converter moves along the $+i$ and $-i$ axes at $v_H>0$ rather than through all four quadrants of the voltage-current plane. The earlier “four-quadrant” wording overstated this and has been corrected. Figure 10 commands the pack current from $+125$ A (full discharge, boost) to $-125$ A (full charge, buck) at 3 ms, with the link held stiff by the grid-tied inverter it feeds. The inner sliding-mode loop reverses the 250 A swing in 0.255 ms, limited only by how fast the pack voltage can drive current through the inductor, and there is no discontinuity at zero crossing because the same sliding law covers both signs. To test the earlier claim that a PI cascade would need a mode switch, the same reversal was run with the PI current loop in place of the sliding-mode loop: it also reverses continuously, with no explicit mode switch, but takes 1.139 ms—about four and a half times longer—because the linear current loop has no reaching term to force the large current swing quickly. The honest statement is therefore not that the PI cannot reverse but that the sliding-mode loop reverses the same current far faster on the same converter.

Figure 10. Pack current commanded from full discharge ($+125$ A) to full charge ($-125$ A) at 3 ms with a stiff link. The sliding-mode loop reverses the current in 0.255 ms; the PI cascade taken through the same reversal completes in 1.139 ms. Both cross zero continuously; neither needs a mode switch.

4.5. Duty Cycle Averaged Against the Switching Model

Two points of modelling need to be stated plainly because they bound how the results should be read. First is the duty itself. Figure 11 plots the duty over time for the load step, the mismatched load step, and the power reversal. In the two load-step cases, it sits near its equivalent-control value of about 0.47 and moves only a little at the step, staying well inside $[0,1]$; the sliding analysis, which assumes an unsaturated duty, therefore applies to all the regulation results. The one excursion to a limit is the power reversal, where the duty drops to zero for a few tens of microseconds while the pack drives the current negative, then recovers, which is the saturated interval the stability discussion of Section 3.3 identifies and that the reversal still completes cleanly through.

Figure 11. Duty cycle over time for the load step, the mismatched load step, and the power reversal. The duty stays in the interior of $[0,1]$, except at the reversal instant, where it touches zero for a few tens of microseconds. The dashed vertical line in each panel marks the disturbance instant (the load step at 4 ms; the reversal at 3 ms).

Second is which model produces which number. The load step, the parameter-mismatch sweep, the constant-power case, the power reversal, and the real-world profile are all run on the averaged model of (1), where the duty is a continuous variable; this is the standard state-space-averaged description and is what makes a fair, fast comparison of the two controllers possible. The chattering study of Section 4.8 is the exception: it runs at the switching level, with the two devices as a binary state because chatter is a switching phenomenon the averaged model cannot show. To check that the averaged load-step numbers are not an artefact of averaging, the load step was re-run at the switching level, the sliding-mode duty was applied through a 20 kHz PWM and the half-bridge was switched device by device. Figure 12 shows the result: the switching model gives a 2.75 percent dip and a 0.87 ms settling, against 2.42 percent and 0.71 ms from the averaged model, which is close enough to confirm that the averaged comparison holds at the switching level, with the small extra dip coming from the finite PWM ripple the averaged model smooths over.

Figure 12. Switching-model check of the averaged load step. Driving the same sliding-mode law through a 20 kHz PWM and switching the half-bridge device by device gives a 2.75 percent dip, against 2.42 percent from the averaged model, confirming the averaged results. The dotted horizontal line is the 750 V setpoint; the dashed vertical line marks the load-step instant at 4 ms.

4.6. Regulation Under a Real-World Charging Profile

The last test drives the converter with the Helix demand shape (Section 3.10), replayed on the compressed timescale of one millisecond per hour. Figure 13a shows the 24-point charging-power reference, scaled to the 50 kW rating, with its real daytime peak near mid-day and its quiet overnight hours. Figure 13b shows the link voltage the controller holds while the converter sources that demand. Across the run, the link stays within 9.12 V of the 750 V setpoint, a worst-case deviation of 1.2 percent, with a root-mean-square deviation of 3.07 V. Those deviations are the response to the hour-to-hour steps in the demand shape; the demand changes far more slowly than the control bandwidth, so the regulation is comfortable and the compression does not flatter it. The point is that the shape is a real one: a public rapid-charging hub loads its converters in the daytime, and the controller holds the link through that real rise and fall rather than only through a clean step. It is a test of shape-tracking, not a claim of a full-bandwidth 24 h transient.

Figure 13. Real-world duty test, with the 24 hourly demand points replayed at one millisecond per hour. (a) A charging-power reference derived from 41,213 real sessions at the Newcastle Helix site, scaled to 50 kW. (b) The DC link the two-loop sliding-mode controller holds while sourcing that demand: worst-case deviation of 9.12 V, rms 3.07 V. In panel (a) the shaded band highlights the evening demand window (about 16:00–20:00); in panel (b) the dotted line marks the 750 V setpoint. This is a shape-tracking test on a compressed timescale, not a full-bandwidth 24 h transient.

4.7. Head-to-Head Summary

Table 7 collects the comparison in one place. The sliding-mode controller leads on settling time and dip in both the nominal and the mismatched case, and the gap it opens under mismatch is the part that matters most: its dip grows by 0.38 percentage points when the inductor is 40 percent off, against 0.44 for the PI cascade, and its settling time is essentially unchanged. Both hold zero steady-state error, and the two-quadrant power reversal completes in 0.255 ms for the sliding-mode loop, against 1.139 ms for the PI cascade on the same converter.

Table 7. Head-to-head summary of the two controllers on the same converter.

Metric	Two-Loop SMC	PI Cascade
Settling, nominal step (ms)	0.71	1.75
Dip, nominal step (%)	2.42	4.20
Settling, +40% L, +50% $R_L$ (ms)	0.72	1.57
Dip, +40% L, +50% $R_L$ (%)	2.68	4.64
Steady-state link error	0	0
Power reversal $+125\to -125$ A (ms)	0.255	1.139

The arrow (“→”) denotes the commanded change of pack current, from $+125$ A to $-125$ A.

4.8. Chattering and the Boundary Layer

The boundary layer is this paper’s answer to the chattering a naive sliding law produces, so it is measured rather than asserted, and the comparison is set up so the switching implementation is the same for both laws. That fairness matters: an earlier version timed the discontinuous law at a 50 ns step against the boundary-layer law inside a 20 kHz PWM, which is not like-for-like because the 20 kHz is the PWM carrier, not a property of the control law. Here the inner loop is run at the switching level; the two devices are run as a binary state; and the two reaching laws, i.e., the discontinuous $sign\left(s\right)$ and the boundary-layer $sat(s/\varphi )$, are placed inside the same 20 kHz PWM, sampled once per carrier period. The only difference is then the reaching law.

Under that equal implementation, the two are almost indistinguishable: both switch at the 20 kHz carrier, and the steady inductor-current ripple is 38.9 A for the sign law, against 37.5 A for the saturation law, with the ripple being set by the inductor and the carrier rather than by the reaching term. This is the honest result, and it says something precise about what the boundary layer does. It is not that the boundary layer lowers the switching frequency once a carrier is fixed; it is that the boundary layer is what lets a fixed-frequency carrier be used at all. The discontinuous law has no such freedom: implemented as it is defined, switching the instant (s) crosses zero with no carrier; it free-runs at a frequency set only by the hardware—about 9.4 MHz at the 50 ns step here and unbounded in principle—far past any SiC gate drive. Figure 14a shows the two currents overlapping under the shared 20 kHz PWM, with the native carrier-free frequency of the sign law noted for contrast. The boundary layer, in short, is the device that converts an unbounded-frequency reaching law into one a fixed-frequency modulator can carry.

Figure 14. Chattering and the boundary layer, compared fairly. (a) The discontinuous $sign\left(s\right)$ law and the boundary-layer $sat(s/\varphi )$ law inside the same 20 kHz PWM: the inductor currents overlap, and the steady ripple (38.9 A against 37.5 A) is set by the carrier, not the reaching law. The native carrier-free sign law instead free-runs at about 9.4 MHz (noted), which is the chatter the boundary layer exists to avoid. (b) Under a deliberate $3\times$ inductor-resistance mismatch, the steady current error grows with the boundary-layer half-width ($\varphi$); the design value of $\varphi =8$ A sits low on the curve.

Figure 14b shows what the width then costs in tracking. Because an exact equivalent control holds the surface on its own, the boundary layer has no steady-state effect until the model is wrong, so the trade is exposed under a deliberate mismatch, with the inductor copper set to three times the value the equivalent control assumes. The steady current error grows with the width, from 0.43 A at $\varphi =2\mathrm{A}$ to 0.59 A at $\varphi =64\mathrm{A}$, corresponding to a shallow, monotonic rise. The design value of $\varphi =8\mathrm{A}$ sits low on that curve, holding the residual band near 0.54 A. Thus, the width is set small enough to keep the residual error tight and large enough that, at a real sampling and PWM rate, the near-surface gain does not push the loop back toward the unbounded switching the boundary layer exists to avoid.

4.9. Controller-Gain Sensitivity

A control design is only as useful as its tolerance to the gains being off, so each gain was perturbed by $\pm 50\%$ around its design value, and the load step was re-run. Table 8 collects the settling time and the dip on the nominal plant in the upper panel and on the mismatched plant of Section 4.3 in the lower one. Two panels are needed because on the nominal plant, the inner gains do nothing at all: with the reference-slew feedforward carried, the equivalent control holds the surface on its own, $\left|s\right|$ never exceeds $0.03$ $\mathrm{A}$, and halving or raising $\lambda$, $\eta$, or $\varphi$ leaves the settling and the dip unchanged to three decimals. That is the sliding-mode structure working as designed rather than a flat result, but it means the nominal panel says nothing about how the inner gains behave when there is something for them to reject.

Table 8. Load-step settling time and dip when each controller gain is perturbed by $\pm 50\%$ from its design value. Upper panel: nominal plant (nominal 0.71 ms, 2.42%). Lower panel: L$+40\%$, $R_L$ $+50\%$ (nominal 0.72 ms, 2.68 %, ${\left|s\right|}_{max}$ 3.69 A), where the reaching term has a real disturbance to reject. A dash means the dip stayed inside the 2% band, so no settling time is defined.

Gain (Design Value)	−50%			+50%
	Settle (ms)	Dip (%)	${\left|\mathbf{s}\right|}_{max}$ A	Settle (ms)	Dip (%)	${\left|\mathbf{s}\right|}_{max}$ A
Nominal plant
Surface rate ($\lambda$, $2.5\times {10}^4$ )	0.71	2.42	0.03	0.71	2.42	0.03
Reaching gain ($\eta$, $2.0\times {10}^4$ )	0.71	2.42	0.03	0.71	2.42	0.03
Boundary layer ($\varphi$, 8 A)	0.71	2.42	0.03	0.71	2.42	0.03
Outer proportional ($k_p$, 3.0)	0.99	3.35	0.01	—	1.88	0.05
Outer integral ($k_i$, 4500)	1.08	2.67	0.03	0.56	2.29	0.03
Mismatched plant, L$+40\%$, $R_L$ $+50\%$
Surface rate $\lambda$ ( $2.5\times {10}^4$ )	0.73	2.77	6.10	0.71	2.65	2.66
Reaching gain $\eta$ ( $2.0\times {10}^4$ )	0.72	2.69	3.84	0.72	2.68	3.56
Boundary layer $\varphi$ (8 A)	0.72	2.67	3.43	0.72	2.69	3.79
Outer proportional $k_p$ (3.0)	1.00	3.63	2.48	0.40	2.14	5.27
Outer integral $k_i$ (4500)	1.05	2.86	3.42	0.60	2.62	4.01

Italic rows are panel sub-headings that identify the plant (nominal or mismatched) for the block of rows beneath them.

The lower panel supplies that. With the inductor 40 percent larger and its copper 50 percent higher, the equivalent control is wrong by a known amount, and the reaching term has to cover the difference, so the inner gains start to matter, and they matter in the direction the theory predicts: halving the surface rate ($\lambda$) lets the peak sliding variable grow from 3.69 to $6.10$ $\mathrm{A}$, raising it pulls the peak down to $2.66$ $\mathrm{A}$, and the link-side dip follows weakly behind (2.77 against 2.65 percent). The reaching gain ($\eta$) and the boundary layer ($\varphi$) move $\left|s\right|$ by less than half an ampere either way, which is consistent with $\lambda$ setting the approach rate and $\eta$ and $\varphi$ shaping only the near-surface behaviour. Throughout, the effect on the quantity the user sees, the link dip, stays under a tenth of a point.

The outer PI gains do more in both panels, as expected of the loop that shapes the recovery. A lower proportional gain ($k_p$) slows the settling to 0.99 ms and deepens the dip to 3.35 percent; a higher one damps the dip to 1.88 percent, which never leaves the 2-percent settling band at all, so no settling time is defined for that case. The integral gain ($k_i$) trades settling against dip in the usual way. Across the whole $\pm 50\%$ box, the loop stays stable and well damped, with the dip between 1.88 and 3.35 percent on the nominal plant and between 2.14 and 3.63 percent on the mismatched one and the settling between 0.40 and 1.08 ms. The design is therefore not knife-edge in its tuning, and with respect to the concern about the cascade structure, the reference the outer loop hands the inner loop does not destabilise it anywhere in this range.

5. Discussion

The results line up into one message: the sliding-mode inner loop buys speed and, more importantly, robustness at a cost that is mostly complexity rather than performance. On the nominal load step, the sliding-mode controller settles about 2.5 times faster and dips roughly half as far as the PI cascade. That difference alone would not settle the choice because a PI cascade can be pushed harder if its inner loop is fast enough. The robustness result is the one that does settle it. When the inductor is 40 percent off, the sliding-mode response barely changes while the PI cascade degrades, and in a real converter, the inductor is always somewhat off because it saturates under high current and heats under load. A controller whose transient does not depend on the exact inductor value is worth the extra design effort in a part that has to work across a wide operating range. The parameter sweep of Table 6 pins down which part of the uncertainty the surface rejects. The copper resistance enters through the same channel as the control, so it is the matched uncertainty a first-order surface handles, and the sliding-mode dip barely moves under a 50 percent resistance error. The inductance is different: it multiplies the control input itself, so it is an input-gain uncertainty the first-order surface does not fully cover, and it is the inductance error, not the resistance, that accounts for essentially all of the small dip growth under the combined mismatch. The sliding-mode controller still holds a smaller absolute dip than the PI cascade in every case, but its edge is near-exact rejection of the matched resistance and pack-voltage drift rather than a uniformly smaller relative sensitivity. Fractional-order second-order and non-singular terminal sliding-mode designs have recently been shown to extend the invariance to mismatched, input-gain uncertainty as well [27,28], and adopting such a surface would tighten the guarantee for precisely the inductance drift this converter sees; it is a clear direction for the next version of the controller.

The reversal result matters for V2G specifically. Because the same sliding law covers positive and negative current, the converter crosses zero power in a quarter of a millisecond with no glitch, which is what a vehicle switching from charging to exporting needs. A design that splits charge and discharge into separate controllers with a hand-off between them would have to manage that hand-off carefully; the single sliding surface removes the problem rather than solving it. Taking the converter from this device-level result to a full grid interaction is the next step up: the DC link this converter holds is, in a V2G stack, the shared node several converters lean on, and coordinating voltage and power across the storage and distributed-generation inverters on the load side is where a device-level current controller like this one plugs into a system-level scheme [29]. The fast, glitch-free reversal shown here is what such a coordinated layer needs underneath it.

The efficiency numbers are a stated budget, evaluated term by term with the conduction loss taken per switch from the RMS current, and they behave as an SiC design should, peaking near 98.7 percent at part load and holding above 98.3 percent to rated power. The value of writing the budget out is that it separates the control contribution, which this paper measures, from the device contribution, which a reader can substitute; anyone can drop in a different $R_{ds}$, switching energy, or fixed loss and redraw the curve. The real-world profile test then closes the loop on realism: the converter holds the link within 1.2 percent through a demand shape taken from tens of thousands of real charging sessions, not a synthetic waveform.

6. Limitations

Several limits bound what this study claims. The work is a simulation at the averaged and switching-model level, not a hardware build, so parasitics, dead-time effects, sensor noise, and thermal dynamics are not captured, and the chatter the boundary layer suppresses would need checking on a real gate drive. The loss model is a representative SiC budget, so the absolute efficiency figures should be read as indicative and recomputed for a specific device. The pack is modelled as a stiff 400 V source, which ignores the pack’s own impedance and the voltage droop across the state of charge, both of which a full design would include. The real-world duty profile uses the Helix hourly demand shape scaled to the converter rating; it is an aggregate site profile, not a single-vehicle current trace, and the sub-second dynamics between the hourly points are not represented. Finally, the comparison is against a PI cascade taken at both its standard tuning and at an inner-loop bandwidth matched to the sliding-mode loop; a differently structured linear controller or a model predictive controller would shift the margins, though not the robustness argument, which follows from the sliding-mode structure rather than from the tuning.

7. Conclusions and Future Work

Against a like-for-like PI cascade on the same 50 kW bidirectional converter, the two-loop sliding-mode controller settled a 40 to 100 percent load step in 0.71 ms, against 1.75 ms with a smaller dip; stayed almost unchanged when the inductor was 40 percent larger and its resistance 50 percent higher; and reversed full pack current in 0.255 ms, against 1.139 ms for the PI cascade taken through the same reversal. The result that carries the most weight is the robustness one because invariance follows from the sliding-mode structure rather than from the tuning: the transient holds when the inductor drifts, which, in a real converter, it always does as the core saturates and the winding heats. That property, not raw speed, is the reason to prefer the sliding-mode inner loop in a part that must work across a wide operating range. The stated SiC loss budget, with conduction evaluated per switch from the RMS current, put efficiency between 98.3 and 98.7 percent across the range, and the converter held the DC link within 9.12 V through a time-compressed charging-demand profile taken from 41,213 real sessions at the Newcastle Helix site. Future work should take the design to a hardware-in-the-loop, then a bench build with a real SiC gate drive to test the chattering behaviour; add the pack impedance and state-of-charge droop; drive the converter with second-by-second real current traces rather than an hourly shape and compare the sliding-mode design against the fractional-order and terminal sliding-mode variants and a model predictive controller on the same plant.