Low-Latency Edge Computing Architectures for Real-Time Vehicle Warning Systems: A Review

Real-time vehicle warning systems are critical for collision prevention, yet they face stringent sub-10 ms latency requirements under severe energy and computational constraints. This review systematically surveys low-latency edge computing architectures for such systems, explicitly comparing CPU-based, GPU-accelerated, FPGA-based, ASIC/NPU-embedded, fog, and cloud-only processing paradigms. We examine edge intelligence frameworks for intelligent transportation systems, the computational demands of collision avoidance algorithms, V2X communication protocols, and hardware accelerators. A key contribution is a comparative analysis of latency, power consumption, and area trade-offs, revealing that FPGA accelerators achieve deterministic sub-millisecond processing at 5–15 W, while emerging NPUs offer 1–5 W alternatives for fixed-function inference. A critical synthesis of the literature identifies major gaps: the absence of standardized benchmarks, insufficient field-testing of FPGA prototypes, and underutilized potential of approximate computing in safety loops. Furthermore, we introduce fog computing as a vital intermediary layer to bridge edge-cloud gaps. This review consolidates over 58 core studies and offers practical, actionable insights for designing next-generation vehicular safety systems.