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SensorsSensors
  • Article
  • Open Access

6 July 2021

20 Pages

Efficient FPGA Implementation of a Dual-Frequency GNSS Receiver with Robust Inter-Frequency Aiding

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1
Department of Electrical Engineering, National Cheng Kung University (NCKU), Tainan 70101, Taiwan
2
National Applied Research Laboratories (NARLabs)-National Space Organization (NSPO), Hsinchu 30078, Taiwan
*
Author to whom correspondence should be addressed.
This article belongs to the Section Remote Sensors

Abstract

Multiple frequency global navigation satellite system (GNSS) has become more complex due to the existence of extra channels. Typically, auxiliary methods are used to synchronize the second signals at other bands by aiding the acquired channel parameters. However, there are critical limitations because the reception of GNSS signals is subject to uncertainties due to noise carrier injection or circuit interference. The relationship between the two Doppler frequencies can be affected by uncertainties. Therefore, we aimed to implement an efficient dual-frequency field-programmable gate array (FPGA), performing a direct aid tracking method for the secondary channel to achieve resource efficiency and inner aid robustness. A robust estimator that directly links two loops in the two bands is proposed. In this scheme, (1) a robust estimator able to cope with uncertainty; (2) a primary tracking scheme to obtain the error boundary, and (3) a tracked bit-boundary for the initial code phase of the second channel are used. Based on experiments on the FPGA, the robust channel link can achieve direct aid tracking, and 31.02% of the original hardware resources from the aided acquisition module were released satisfactorily.

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