Search Results (136)

Single-crystal diamond is regarded as one of the most promising semiconductor materials for next-generation high-power electronic devices, quantum technologies, and extreme environmental applications, owing to its ultra-wide bandgap, exceptionally high carrier mobility, ultra-high breakdown electric field, and excellent thermal conductivity. However, the lateral dimensions of both natural and synthetic single-crystal diamond are limited, which severely restricts their large-scale industrial application. Mosaic growth, in which multiple small single-crystal seeds are laterally arranged and fused at the interfaces through homoepitaxial growth, offers a promising approach to overcoming the size limitation of seed crystals and producing inch-scale single-crystal wafers. This review systematically covers the entire mosaic growth process, including seed crystal preparation, geometric design, growth parameter optimization, and innovative processing methods. Particular emphasis is placed on the mechanisms of interfacial stress generation, along with characterization techniques and stress control strategies. Finally, future perspectives on the fabrication of large-size, low-stress single-crystal diamond wafers are outlined. Full article

Silicon micromachining serves as the foundational enabling technology for high-precision MEMS inertial sensors. However, the relentless pursuit of enhanced sensitivity and multi-functionality in emerging applications encounters a fundamental bottleneck when confined to two-dimensional scaling. The evolution toward complex three-dimensional (3D) stacking architectures is an inevitable trajectory for devices including MEMS inertial sensors, yet performance is constrained by the limitations of conventional processes in fabricating and integrating intricate 3D hollow structures. Specifically, uniformity in large-area deep silicon etching, structural integrity of convex corners in wet etching, and residual stress induced by multi-layer wafer bonding have emerged as critical, shared challenges. To address these issues, this paper proposes a triple-layer wafer-level stacking scheme that synergistically combines wet/dry hybrid etching with low-temperature adhesive bonding. This stacking scheme incorporates an innovative linear compensation model for wet-etched convex corners, enabling high-precision fabrication of complex corner structures under deep etching conditions. Furthermore, a collaborative strategy involving temporary bonding and plasma flow-field optimization improves the uniformity and integrity of dry etching for large perforated structures. A low-temperature triple-layer wafer-level stacking process is developed, encompassing precise adhesive dispensing, optical alignment, and a stepped low-temperature curing profile, thereby achieving highly symmetric 3D integration with controlled adhesive distribution. The efficacy of this stacking scheme is validated through the fabrication of a symmetrically stacked triple-layer MOEMS accelerometer sensing element. Test results demonstrate a noise floor as low as 0.40 µg/√Hz and a bias instability of 1.81 µg over 10 min. Compared with a double-layer counterpart, improved performance is obtained. The wafer-level stacking scheme established in this work not only provides a viable pathway for pushing the manufacturing limits of high-precision inertial devices but also offers a generic methodology for tackling complex hollow structure formation and low-temperature integration, holding referential value for broader applications in high-precision 3D microsystems. Full article

Few-layer hexagonal boron nitride (hBN) is a promising two-dimensional dielectric for electronic and neuromorphic devices. However, its practical deployment is often hindered by the thickness nonuniformity of as-grown samples and by defects introduced during the transfer-stacking process of assembled samples. In particular, the influence of the initial hBN quality on the final stacked-film quality remains insufficiently understood. Here, we report a wafer-scale strategy for fabricating high-quality few-layer hBN based on ultraflat single-crystal hBN (USC-hBN) monolayers. Compared with transfer-stacked hBN grown on Cu foil (rough hBN), stacked few-layer USC-hBN shows a much lower surface roughness and a drastically reduced wrinkle density, indicating superior flatness and interfacial cleanliness. Furthermore, memristors fabricated from six-layer USC-hBN exhibit clearer resistive-switching behavior and a higher ON/OFF ratio than those based on rough hBN, owing to the more uniform surface/interface. These results demonstrate that source-material flatness is a critical determinant of transfer-stacked hBN quality and device performance. This work provides an effective route toward reliable integration of high-quality two-dimensional dielectric films. Full article

Reconfigurable radio frequency (RF) attenuators are critical passive components for 5G-Advanced and emerging 6G wireless systems. Conventional tunable attenuators rely on solid-state switches combined with fixed resistor networks, which suffer from unavoidable static power consumption and severe parasitic degradation at high frequencies. Here, we systematically demonstrate HfO₂-based non-volatile memristors as RF switches with tunable ON-state resistance (R_ON), enabling a switching-attenuation-integrated multistate attenuator. The fabricated Au/HfO₂/Ag devices exhibit stable bipolar resistive switching with an ON/OFF ratio exceeding 10⁹, reliable retention of 10⁵ s, and programmable R_ON continuously tuned from 5.8 Ω to 197.5 Ω. On-wafer RF characterizations from 10 MHz to 43.5 GHz reveal low insertion loss (−0.53 dB), high isolation (−26.8 dB), and clear scaling laws governing the effects of device geometry and R_ON on RF performance. Leveraging these unique characteristics, we propose a symmetric π-type programmable all-memristor attenuator architecture with a cascaded 2-unit configuration. The design achieves 12 discrete attenuation levels from 2 dB to 24 dB, a return loss better than 10 dB across the full band, and zero static power consumption without additional passive components or bias networks. This work establishes the fundamental material-device-RF performance relationship in HfO₂-based RF switches and provides a compact, low-power, and highly integrable solution for next-generation reconfigurable RF front-ends. Full article

To address the accuracy limitations in identifying micro-scale and low-distinguishability defects, we proposes an improved EfficientNet model for wafer defect classification in semiconductor fabrication. In particular, we construct the model using EfficientNetV2 architectures as the backbone and introduce a multi-scale self-attention enhancement module to strengthen the capture capability for critical defect characteristics. This module consists of four parallel self-attention enhancement modules, aiming to obtain spatial context information at different levels and enhance relevant features through a self-attention mechanism. Meanwhile, we merge the manually extracted features of defects with the CNN’s fully connected layer, effectively compensating for the deficiency of automatic features in the differentiated representation of defects. The manual feature extraction module leverages image processing techniques to capture diverse morphological characteristics of defects including geometric features, moment features and texture features. We simulate and generate a lithography SEM image dataset with various types of defects based on the typical line-space structure and the ICCAD2019 mask pattern dataset. The total sample size of the wafer defect dataset is 1500, covering 15 typical defects with an average distribution. The classification performance of models is evaluated on the simulated defect dataset. The results indicate that the overall classification accuracy of the improved model reaches 96.60%, representing an improvement of 8.14% compared to the original EfficientNetV2. This demonstrates the superiority of the proposed model in addressing classification tasks involving micro-scale and low-distinguishability defects. Full article

Josephson junctions are key elements in superconducting qubits. Their efficient wafer-scale characterization is crucial for process control and optimization, motivating analysis approaches that extend beyond conventional cryogenic measurements. In this work, we demonstrate that room temperature (RT) capacitance and current–voltage measurements, combined with appropriate data analysis, enable extraction of relevant junction parameters such as oxide thickness, tunnel coefficient, and interfacial defect density. Furthermore, different charge transport mechanisms can be identified from detailed current–voltage analysis. We evaluate our characterization technique using tunnel junctions fabricated on 200 mm wafers in a complementary metal–oxide–semiconductor (CMOS)-compatible subtractive process. The results show a homogeneous average oxide thickness across the wafer with a variation below 3%. A dependence of the tunnel coefficient on oxide thickness indicates a stoichiometry gradient within the oxide. Additionally, low interfacial defect densities in the range of 70–5000 defects/cm² are observed in our junctions, increasing with decreasing oxide thickness, suggesting that wet etching used for thickness control introduces interfacial trap states. Our study highlights the importance of advanced RT characterization for extracting tunnel junction parameters on the wafer scale, enabling effective process monitoring and optimization in industrial superconducting qubit manufacturing. Full article

The semiconductor industry has long relied on Statistical Process Control (SPC) for yield and reliability management. In early technology nodes, classic univariate tools such as Shewhart charts, cumulative sums (CUSUM), exponentially weighted moving averages (EWMA), and the Cp/Cpk exponent could effectively monitor a finite set of key variables. However, sub-5nm and emerging 3 nm technologies have fundamentally changed the statistical environment. Advanced patterning, high-aspect-ratio etching, atomic layer deposition (ALD), chemical-mechanical polishing (CMP), and novel materials have drastically narrowed the process window. At these scales, nanometer-level deviations in critical dimensions (CD), overlay, or surface roughness can significantly impact yield. Simultaneously, modern wafer fabs generate massive amounts of high-frequency sensor data and high-dimensional metrology data. Traditional SPC assumptions—such as independence, normality, low dimensionality, and stationarity—often do not hold. Semiconductor data exhibits: (i) extremely high-dimensionality and strong intervariate correlations; (ii) a hierarchical structure encompassing fab → tooling → chamber → recipe → batch → wafer → field; and (iii) metrological delays and sampling limitations leading to incomplete and asynchronous observations. To address these challenges, this paper reviews advanced statistical methods applicable to wafer fabrication. These methods include multivariate statistical process control (MSPC) approaches such as Hotelling T² statistics, PCA/PLS combining T² and Q statistics, contribution diagnostics, time-series drift and change point detection, and Bayesian hierarchical modeling for uncertainty-aware monitoring in data-limited scenarios. Furthermore, we discuss how to integrate these methods with fault detection and classification (FDC), line-to-line monitoring (R2R), advanced process control (APC), and manufacturing execution systems (MES). This paper focuses on scalable, interpretable, and maintainable implementations that transform statistical analysis from a passive monitoring tool into an active component of data-driven fab control. Full article

Previous studies have shown that the external quantum efficiency (EQE) of conventional red Micro-Light emitting diodes(Micro-LEDs) decreases markedly with reducing chip size. This degradation is generally attributed to enhanced non-radiative recombination at sidewall defects, which leads to increased carrier loss in size-scaled LEDs. In this work, AlGaInP quaternary semiconductor epitaxial wafers incorporating multiple quantum wells (MQWs) with different well-layer strain states were grown by metal–organic chemical vapor deposition (MOCVD). Through wafer bonding, photolithography, etching, and metal evaporation, these epitaxial structures were fabricated into Micro-LED arrays with single-pixel pitches of 10, 20, 50, and 100 μm. The experimental results reveal that, with increasing indium (In) composition in the GaInP well layers—corresponding to a gradual increase in lattice mismatch (Δa/a) from 0% to 1%—smaller-sized Micro-LED arrays exhibit superior EQE performance. For devices with a pixel pitch of 10 μm, the EQE of Micro-LED arrays with a 1% lattice mismatch in the well layer is approximately three times higher than that of lattice-matched (0%) counterparts. In contrast, for devices with a pixel pitch of 100 μm, the EQE of lattice-matched (0%) Micro-LED arrays is about 1.3 times higher than that of devices with a 1% lattice mismatch. These results indicate that, to achieve maximum EQE in Micro-LEDs, the strain state of the MQW-layer material must be carefully considered as a priority factor. Optimal device performance requires appropriate matching between LED size and the well-layer growth strain. Full article

Photolithography is the mainstream technology used in micro/nanofabrication. While projection photolithography is widely used in production, with a resolution close to the wavelength of the light source, its processes are complicated and expensive. Moreover, in projection photolithography, scanning and splicing are required to achieve large-area exposure at the wafer level, which reduces throughput in production. Contact photolithography offers a cost-effective and parallel exposure solution, but achieving uniform resolution over large areas with micrometer or sub-micrometer resolution remains a challenge. In this study, we propose a conformal contact photolithography strategy based on a wafer-scale embedded elastomeric mask. By optimizing metal patterning and embedding transfer processes, we significantly improve the area (wafer-scale) and efficiency (lift-off and metal transfer process within seconds) of metal-embedded elastomeric mask fabrication. This method enables the rapid and cost-effective fabrication of large-area sub-micrometer-resolution structures, with broad applications in the production of sub-micrometer devices and academic research. Full article

Surface-enhanced Raman scattering (SERS) holds great promise for ultrasensitive chemical analysis but is often limited by the trade-off between performance and fabrication simplicity. This work presents a facile strategy to prepare monolayer silver microplates combining the top-down and bottom-up fabrication concepts. Silver microplates with uniform nanoscale thickness (~93.5 nm) and micron-scale lateral size (D₅₀ = 3.33 µm) are prepared via a scalable mechanical ball-milling process. These silver microplates served as building blocks for spontaneous interfacial self-assembly at the air/water interface to form a macroscopically continuous monolayer film. The silver microplate monolayer film is transferred onto a plasma-treated silicon wafer as a SERS substrate. The resulting SERS substrate exhibits a porous, network-like microstructure composed of densely packed microplates, which generates a high density of electromagnetic hot spots at the nanogaps. Using Rhodamine 6G as a probe molecule, the substrate demonstrates a SERS detection limit of as low as 1 nM and good spatial uniformity with a relative standard deviation of ~9.94%. This study provides a cost-effective and scalable self-assembly route of physically reshaped silver microplates to fabricate high-performance SERS substrates. Full article

To investigate the drag reduction mechanism of shark skin placoid scales and develop high-efficiency drag-reducing surfaces, this study designed and fabricated a biomimetic shark skin surface featuring staggered microscale groove structures. The fabrication process involved laser etching on silicon wafers to create a placoid microstructure template, followed by polydimethylsiloxane (PDMS) replication to obtain biomimetic shark skin samples. Sedimentation experiments demonstrated that the biomimetic surface significantly reduced settling time compared to a smooth surface, achieving a drag reduction rate of 5.65%. Further computational fluid dynamics (CFD) simulations were conducted to analyze the near-wall flow characteristics around the biomimetic surface. The results revealed that the drag reduction mechanism primarily stems from the effective regulation of near-wall laminar flow by the micro-groove structures: a low-velocity fluid layer formed within the grooves reduces the near-wall velocity gradient, thereby decreasing frictional drag, while stable recirculation zones develop within the grooves, contributing to momentum redistribution and reduced energy dissipation. Additionally, the staggered arrangement of the grooves promotes a smoother pressure distribution along the flow direction, mitigating pressure drag by reducing the pressure differential between windward and leeward surfaces. The experimental and simulation results showed excellent agreement (simulated drag reduction rate: 5.08%), collectively verifying the feasibility and effectiveness of the proposed biomimetic placoid structure in achieving fluid drag reduction. Full article

Stringent cleanliness standards govern process fluid transport in integrated circuit (IC) manufacturing. Cavitation-induced surface defects on flow control components promote bacterial adhesion, thereby compromising wafer fabrication. To elucidate the coupling mechanisms among surface topography, hydrodynamics, and bacterial retention, this study utilizes a one-way coupled Computational Fluid Dynamics and Discrete Element Method (CFD-DEM) approach integrated with extended Derjaguin–Landau–Verwey–Overbeek (XDLVO) theory. We constructed a numerical model of rod-shaped Pseudomonas aeruginosa, integrated with a customized API-based coupling scheme to resolve temporal scale disparities, and systematically simulated flow evolution and adhesion behaviors across varying groove geometries (quadrilateral, triangular, and semicircular) and inlet velocities (1–3 m/s). The results indicate that groove-induced flow separation and recirculation vortices drive bacterial accumulation at the trailing edge. Triangular profiles exhibited superior flow stability, yielding significantly lower adhesion than quadrilateral and semicircular shapes. Bacterial retention scaled inversely with flow velocity due to enhanced hydrodynamic shear. These findings provide theoretical and engineering insights for the anti-contamination design of ultra-clean flow control components in IC manufacturing. Full article

Porous silicon (PSi), characterized by its high specific surface area and highly tunable morphology, presents significant potential across optoelectronics, energy storage, and biomedical applications. This review provides a systematic analysis of the synthesis methodologies, interfacial chemical engineering, and diverse applications of PSi. Initially, fabrication techniques are examined, contrasting the pore formation mechanisms of electrochemical anodization, metal-assisted chemical etching (MACE), and emerging vapor-phase etching methods, while elucidating the control of geometric parameters from microporous to macroporous scales. To address the thermodynamic instability of the hydride-terminated surface, this review systematically evaluates modification strategies such as thermal oxidation, hydrosilylation, carbonization, and atomic layer deposition (ALD). We critically analyze their efficacy in mitigating oxidative drift and enabling specific functionalization. Subsequently, the review summarizes current applications in sensing (refractive index and photoluminescence modulation), energy storage (lithium-ion battery anodes and supercapacitors), and microsystem technologies (radio frequency (RF) isolation, gettering, and micro-electro-mechanical systems (MEMS) sacrificial layers), emphasizing the critical role of structure–property relationships. Finally, an objective assessment is provided regarding the challenges in translating PSi technology to industrial scales, specifically addressing the trade-offs between biodegradability and stability, wafer-scale process uniformity, and the compatibility of wet-chemical processing with standard complementary metal–oxide–semiconductor (CMOS) integration flows. Full article

Monolayer ${\mathrm{MoS}}_2$ memtransistors offer gate-tunable hysteresis for neuromorphic reservoir computing, yet the role of operating window and fading-memory dynamics in CVD devices remains underexplored. We grow CVD monolayer ${\mathrm{MoS}}_2$, fabricate back-gated memtransistors, and use a single device as a time-multiplexed reservoir node for one-step Lorenz-63 prediction. Mobility, ON/OFF, hysteresis, and drift are quantified to identify stable, tunable bias regimes. We used a transistor with field-effect mobility on the order of $10 {\mathrm{cm}}^2 {\mathrm{V}}^{-1} {\mathrm{s}}^{-1}$, an ON/OFF ratio above ${10}^5$, and a moderate hysteresis window quantified by $H\approx 2.1 \mathsf{\mu }$A·V at $V_{\mathrm{DS}} = 50$ mV and $H\approx 17 \mathsf{\mu }$A·V at $V_{\mathrm{DS}} = 500$ mV over $V_{\mathrm{GS}}\in [-10,30]$ V. Performance is bias/memory-limited rather than FET-metric-limited. Sweeping gate-window and reservoir hyperparameters shows an optimum at intermediate hysteresis with moderate drift. Performance improves when the input clock matches the fading-memory time, achieving normalized root mean square error (NRMSE) = 0.09 for one-step Lorenz-63 x-prediction. Device-level statistics (discussed in the main text) show that, despite substantial scattering in electrical parameters, the resulting device-to-device NRMSE variation remains very small under fixed operating conditions. Classical FET metrics are not limiting here; NRMSE improvement instead requires engineering the hysteresis spectrum and gate stack. The demonstration of Lorenz-63 prediction using CVD-grown monolayer ${\mathrm{MoS}}_2$ memtransistors highlights their potential as a wafer-scalable platform for compact chaotic time-series predictions. Full article

Vanadium dioxide (VO₂) is a highly promising material for infrared laser protection due to the pronounced optical switching effect during its metal–insulator transition (MIT). However, due to the relatively high MIT temperature of VO₂ and the low transmittance contrast before and after the MIT, practical applications face challenges in modulation depth and response time. In this study, we address these issues using a wafer-scale VO₂/GaN/Al₂O₃ heterostructure fabricated by oxide molecular beam epitaxy. The conductive GaN interlayer enables local Joule heating of the VO₂ film, permitting direct control of the MIT via an external bias with a threshold of 4.7 V. This structure exhibits a substantial resistance change of four orders of magnitude and enables adaptive limiting of a 3.7 μm laser, reducing transmittance from 60% to 10%. Our work demonstrates a practical, wafer-scale laser-protection device and introduces a pre-excitation strategy via external biasing to enhance response performance. Full article