Search Results (316)

The operational reliability of Insulated Gate Bipolar Transistor (IGBT) modules in demanding transportation applications, such as traction systems, is critically challenged by solder layer and bond wire failures under cyclic thermal stress. To address this, this paper proposes a novel health monitoring framework that innovatively synergizes micro-scale spatial thermal analysis with microsecond electrical dynamics inversion. The method requires only non-invasive temperature measurements on the module baseplate and utilizes standard electrical signals (load current, duty cycle, switching frequency, DC-link voltage) readily available from the converter’s controller, enabling simultaneous diagnosis without dedicated voltage or high-bandwidth current sensors. First, a non-invasive assessment of solder layer fatigue is achieved by correlating the normalized thermal gradient ($\nabla T_{\mathrm{P}}$) on the baseplate with the underlying thermal impedance ($Z_{\mathrm{JC}}$). Second, for bond wire aging, a cost-effective inversion algorithm estimates the on-state voltage ($V_{\mathrm{ce},\mathrm{on}}$) by calculating the total power loss from temperature, isolating the conduction loss ($P_{\mathrm{cond}}$) with the aid of a Foster-model-based junction temperature ($T_{\mathrm{J}}$) estimate, and finally computing $V_{\mathrm{ce},\mathrm{on}}$ at a unique current inflection point ($I_{\mathrm{C},\inf }$) to nullify $T_{\mathrm{J}}$ dependency. Third, the health states from both failure modes are fused for comprehensive condition evaluation. Experimental validation confirms the method’s accuracy in tracking both degradation modes. This work provides a practical and economical solution for online IGBT condition monitoring, enhancing the predictive maintenance and operational safety of transportation electrification systems. Full article

In an era of rapid technological advancements and growing necessity for effective power management systems, the significance of silicon Metal–Oxide–Semiconductor Field-Effect Transistors (MOSFETs) in contemporary power electronics is more critical than ever. This review explores the advancements in silicon MOSFET technology through the lens of Design Technology Co-Optimization (DTCO). By integrating design and process technology strategies, DTCO optimizes power, performance, area, and cost (PPAC) metrics, addressing the limitations of traditional scaling methods. The manuscript presents an exhaustive analysis of the foundational principles of MOSFET technology, the progression of DTCO, and its implications on critical design metrics. The inclusion of machine learning techniques enhances the DTCO process, enabling vast simulations and efficient design iterations, which are crucial for navigating the complexities of advanced semiconductor device physics. Empirical evidence from TCAD simulations augmented by machine learning insights demonstrates the effectiveness of DTCO in enhancing device performance, reliability, and manufacturing yield. This review emphasizes the significance of DTCO and machine learning in addressing contemporary challenges and influencing the future trajectory of silicon MOSFET technology. Full article

The growing demand for energy-efficient memory systems in artificial intelligence (AI) accelerators has intensified research into novel device technologies and computing-in-memory (CIM) architectures. While conventional binary SRAM architectures using CMOS and FinFET devices have been widely explored, ternary-based designs offer potential benefits in terms of storage density and computational efficiency. This work presents a low-power analysis of a sense-amplifier embedded (SE) 9-transistor (9T) ternary SRAM architecture implemented using Carbon Nanotube Field-Effect Transistors (CNFETs) and Gate-All-Around Field-Effect Transistors (GAAFETs). The comparative results show a substantial reduction in total power consumption—from 109.2 $\mathsf{\mu }$W in FinFET to 26.73 $\mathsf{\mu }$W in GAAFET—and an ultra-low power of only 0.0004 $\mathsf{\mu }$W in CNFET, representing a 99% reduction compared to FinFET designs. Similarly, the total delay decreases from 0.01108 ns in FinFET to 0.004 ns in GAAFET, while the CNFET design shows a modest delay of 0.017 ns. Overall, GAAFET offers the best trade-off between power and delay, whereas CNFET achieves the lowest power consumption, making it highly suitable for ultra-low-power AI applications. These findings emphasize the superior energy efficiency and scalability potential of CNFET- and GAAFET-based designs over traditional FinFETs, offering a promising pathway toward next-generation ternary CIM-enabled SRAM architectures. Furthermore, fabrication challenges related to CNFET and GAAFET technologies are discussed, providing insights into their practical feasibility for large-scale integration. Full article

Multi-acceptor and all-acceptor polymers solve the fundamental challenge of achieving unipolar electron transport without compromising stability in n-type polymer field-effect transistors. By systematically replacing electron-rich donors with acceptor units, these architectures push LUMO levels below −4.0 eV and HOMO levels below −5.7 eV. Consequently, electron mobilities exceeding 7 cm² V⁻¹ s⁻¹, on/off ratios approaching 10⁷, and months-long ambient operation can be achieved. This review connects the molecular architecture to device function. We assert that short-range π-aggregation matters more than crystallinity—tight π-stacking over 5–10 molecules drives transport in rigid backbones. Device optimization through interface engineering (e.g., amine-functionalized self-assembled monolayers reduce the threshold voltages to 1–5 V), contact resistance minimization, and controlled processing transform the intrinsic material potential into working transistors. Current challenges, such as balancing the operating voltage against stability, scaling synthetic yields, and reducing contact resistance, define near-term research directions toward complementary circuits, thermoelectrics, and bioelectronics. Full article

With continued transistor scaling and increasing interconnect density in very large-scale integration (VLSI) circuits, the parasitic capacitance of interconnect has become a major contributor to circuit delay and signal integrity degradation. Fast and accurate parasitic capacitance extraction is therefore essential in the back-end-of-line (BEOL) stage. Currently, 2.5D parasitic capacitance extraction flow based on the pattern matching method is widely used by commercial tools, which still suffer from lengthy pattern library construction, cross-section preprocessing, pattern mismatch, and poor accuracy for small capacitance extraction. To overcome these limitations, this work proposes an end-to-end parasitic capacitance extraction workflow, named residual multilayer perceptron interconnect parasitic capacitance extraction (RMLP-Cap), which leverages a residual multilayer perceptron (ResMLP) to enhance traditional workflow. RMLP-Cap integrates parasitic extraction (PEX) window acquisition, pattern definition, feature extraction, dataset generation, ResMLP model training, and capacitance aggregation into a unified flow. Experimental results show that RMLP-Cap can automatically define and model complex 2D patterns with 100% matching accuracy. Compared with a field solver based on the boundary element method (BEM), the ResMLP model achieves an average relative error below 0.9%, a standard deviation under 0.2%, and less than 0.5% error for small capacitances, while providing a 900% speed improvement for extraction speed. Full article

The proposed work introduces a sizing algorithm to achieve a desired linear transconductance in the optimization of operational transconductance amplifiers (OTAs) by applying the $g_m/I_D$ method to find the initial width (W) and length (L) sizes of the transistors. These size values are used to run the non-dominated sorting genetic algorithm (NSGA-II) to perform a multi-objective optimization of three OTA topologies. The $g_m/I_D$ method begins with transistor characterization using MATLAB R2024a generated look-up tables (LUTs), which map normalized transconductance of the transistor channel dimensions, and key performance metrics of a complementary metal–oxide–semiconductor (CMOS) technology. The LUTs guide the initial population generation within NSGA-II during the optimization of OTAs to achieve not only a desired transconductance but also accuracy alongside linearity, high DC gain, low power consumption, and stability. The feasible W/L size solutions provided by NSGA-II are used to enhance the CMOS design of a memristor emulator, where the OTA with the desired transconductance is adapted to tune the behavior of the memristor, demonstrating improved pinched hysteresis loop characteristics. In addition, process, voltage and temperature (PVT) variations are performed by using TSMC 180 nm CMOS technology. The memristor-based on optimized OTAs is used to design a Leaky Integrate-and-Fire (LIF) neuron, which produces identical spike counts (seven spikes) under the same input conditions, though the time period varied with a CMOS inverter scaling. It is shown that increasing transistor widths by 100 in the inverter stage, the spike quantity is altered while changing the spiking period. This highlights the role of device sizing in modulating LIF neuron dynamics, and in addition, these findings provide valuable insights for energy-efficient neuromorphic hardware design. Full article

This work presents the simulation and design of 3C-SiC power MOSFETs, focusing on critical parameters including avalanche impact ionization, breakdown voltage, bulk and channel mobilities, and the trade-off between on-resistance and breakdown voltage. The device design is carried out by evaluating the blocking voltage of scaled structures as a function of the blocking layer’s doping concentration. To mitigate edge-effect breakdown at the p-well/n-drift interface, a step-profile doping strategy is employed. Multiple transistor layouts with varying pitches are developed using a commercially available device simulator. Results are benchmarked against a one-dimensional analytical model, validating the on-state resistance, current–voltage behavior, and overall accuracy of the simulation approach. For the selected material properties, simulations predict that a 600 V 3C-SiC MOSFET achieves an on-state resistance of 0.8 mΩ·cm², corresponding to a 7 μm drift layer with a doping concentration of 1 × 10¹⁶ cm⁻³. Full article

With the discovery of amorphous oxide semiconductors, a new era of electronics opened. Indium gallium zinc oxide (IGZO) overcame the problems of amorphous and poly-silicon by reaching mobilities of ~10 cm²/Vs and demonstrating thin-film transistors (TFTs) are easy to manufacture on transparent and flexible substrates. However, mobilities over 30 cm²/Vs have been difficult to reach and other materials have been introduced. Recently, polycrystalline In₂O₃ has demonstrated breakthroughs in the field. In₂O₃ TFTs have attracted attention because of their high mobility of over 100 cm²/Vs, which has been achieved multiple times, and because of their use in scaled devices with channel lengths down to 10 nm for high integration in back-end-of-the-line (BEOL) applications and others. The present review focuses first on the material properties with the understanding of the bandgap value, the importance of the position of the charge neutrality level (CNL), the doping effect of various atoms (Zr, Ge, Mo, Ti, Sn, or H) on the carrier concentration, the optical properties, the effective mass, and the mobility. We introduce the effects of the non-parabolicity of the conduction band and how to assess them. We also introduce ways to evaluate the CNL position (usually at ~E_C + 0.4 eV). Then, we describe TFTs’ general properties and parameters, like the field effect mobility, the subthreshold swing, the measurements necessary to assess the TFT stability through positive and negative bias temperature stress, and the negative bias illumination stress (NBIS), to finally introduce In₂O₃ TFTs. Then, we will introduce vacuum and non-vacuum processes like spin-coating and liquid metal printing. We will introduce the various dopants and their applications, from mobility and crystal size improvements with H to NBIS improvements with lanthanides. We will also discuss the importance of device engineering, introducing how to choose the passivation layer, the source and drain, the gate insulator, the substrate, but also the possibility of advanced engineering by introducing the use of dual gate and 2 DEG devices on the mobility improvement. Finally, we will introduce the recent breakthroughs where In₂O₃ TFTs are integrated in neuromorphic applications and 3D integration. Full article

The epidemic of infectious diseases, such as influenza A, has imposed a severe health burden on the population. Early detection, diagnosis, reporting, isolation, and treatment are crucial for the prevention, control, and management of infectious diseases. Nucleic acid testing represents a vital approach for the rapid diagnosis of pathogenic microorganism types. However, current nucleic acid detection methods face notable bottlenecks: traditional CRISPR fluorescence assays require time-consuming pre-amplification of target nucleic acids, while existing carbon-nanotube field-effect transistor (FET)-based platforms, though amplification-free, often necessitate complex chip surface modification and probe immobilization, and suffer from non-reusable chips, all limiting their utility in point-of-care testing (POCT) and large-scale screening. This study reports a CRISPR-based amplification-free RNA detection platform (CRISPR-FET) for the rapid identification of influenza A virus. The CRISPR-FET platform described herein enables the detection of viral RNA without amplification within 20 min, with a limit of detection as low as 1 copy/μL. Secondly, a reporter RNA conjugated with gold particles is used to achieve signal amplification in FET detection; meanwhile, the method eliminates probe immobilization, thereby omitting this step and simplifying chip modification to reduce complex work-flows and pre-treatment costs. The chip’s reusability further enhances cost-effectiveness. Additionally, streptavidin-modified magnetic bead adsorption minimizes background errors from excessive reporter RNA and non-target nucleic acids. Finally, validation with 24 clinical samples confirmed the platform’s efficacy. By integrating rapidity, simplicity, and high sensitivity, alongside cost advantages from reusable chips, this CRISPR-FET platform meets the critical need for early influenza A diagnosis and holds promise for advancing POCT and large-scale epidemiological screening. Full article

Germanium (Ge) has long been regarded as a promising channel material, owing to its superior carrier mobility and highly tunable electronic band structure. The new generation of low-power electronics is approaching the formation of fully depleted (FD) transistors on Si-on-insulator (SOl) and Ge-on-insulator (GOl) substrates. In this work, we present a full process of a novel FDGOI transistor formed on a strained GOI with low defect density. This scalable and industry-compatible approach enables the formation of uniform 50 nm thick Ge layers by using spinning wet etch with ultrasmooth surfaces (RMS roughness = 0.262 nm) and a low etch-pit density of ~10⁵ cm⁻². Electrical measurements reveal excellent carrier transport properties, with back-gate (BG) transistors achieving mobilities of 550–600 cm²/V·s, while front-gate (FG) devices exhibit sharp switching behavior and steep subthreshold slopes, yielding I_ON/I_OFF ratios up to 10⁵. Temperature-dependent measurements further demonstrate a pronounced enhancement of device performance: the I_ON/I_OFF ratio increases to 106, the subthreshold swing (SS) decreases from 179 mV/dec at room temperature to 137 mV/dec at 120 K, and the threshold-voltage shift with temperature is as low as 1.87 mV/K across the range of 30–300 K. Such behavior highlights the potential of band-gap engineering for precise threshold-voltage control. Taken together, these results establish GOI as a CMOS-compatible material platform and provide a solid technological basis for the development of next-generation low-power transistors beyond conventional CMOS scaling. Full article

Memristors, as novel one-port electronic elements, have very good memory and commutating properties, insignificant power consumption, and a good compatibility to present CMOS integrated chips. They are applicable in neural networks, memory arrays, and various electronic devices. This paper proposes a simple LTSPICE model of an adapted activation function and a neuron built on memristors. In the neuron, synaptic bonds are implemented by single memristors, allowing a decreased circuit complexity. The summing and scaling schemes are based on op-amps and memristors. The applied modified tangent-sigmoidal activation function is implemented with MOS transistors and memristors. Analyses and simulations are conducted using a simple and high-rate operating memristor model with parasitic parameters—resistance, inductance, capacitance, and small-signal DC components. Their influence on the normal operation of the memristors in the neuron is analyzed, paying attention to their usage and adjustment. The proposed memristor-based artificial neuron is analyzed in MATLAB–Simulink and LTSPICE simulators. A comparison between the derived results confirms the correct operation of the proposed memristor neuron. The generation and analyses of the suggested memristor-based neuron is a significant and promising step for the design and engineering of high-complexity neural networks and their realization in ultra-high-density integrated neural circuits and chips. Full article

In this review, we focus on group IV one-dimensional devices for quantum technology. We outline the foundational principles of quantum computing before delving into materials, architectures and fabrication routes, separately, by comparing the bottom-up and top-down approaches. We demonstrate that due to easily tunable composition and crystal/interface quality and relatively less demanding fabrications, the study of grown nanowires such as core–shell Ge-Si and Ge hut wires has created a very fruitful field for studying unique and foundational quantum phenomena. We discuss in detail how these advancements have set the foundations and furthered realization of SETs and qubit devices with their specific operational characteristics. On the other hand, top-down processed devices, mainly as Si fin/nanowire field-effect transistor (FET) architectures, showed their potential for scaling up the number of qubits while providing ways for very large-scale integration (VLSI) and co-integration with conventional CMOS. In all cases we compare the fin/nanowire qubit architectures to other closely related approaches such as planar (2D) or III–V qubit platforms, aiming to highlight the cutting-edge benefits of using group IV one-dimensional morphologies for quantum computing. Another aim is to provide an informative pedagogical perspective on common fabrication challenges and links between common FET device processing and qubit device architectures. Full article

Organic field-effect transistors (OFETs) have emerged as a transformative platform for high-performance sensing technologies, yet their full potential can be realized only through coordinated performance optimization. This article provides a comprehensive review of recent strategies employed in polymer OFETs to enhance key parameters, including carrier mobility (μ), threshold voltage (Vth), on/off current ratio (I_on/I_off), and operational stability. These strategies encompass both physical and chemical approaches, such as annealing, self-assembled monolayers (SAMs), modification of main and side polymer chains, dielectric-layer engineering, buffer-layer insertion, and blending or doping techniques. The development of high-performance devices requires precise integration of physical processing and chemical design, alongside the anticipation of processing compatibility during the molecular design phase. This article further highlights the limitations of focusing solely on high mobility and advocates a balanced optimization across multiple dimensions—mobility, mechanical flexibility, environmental stability, and consistent functional performance. Adopting a multi-scale optimization framework spanning molecular, film, and device levels can substantially enhance the adaptability of OFETs for emerging applications such as flexible sensing, bioelectronic interfaces, and neuromorphic computing. Full article

A new and transformative era in semiconductor packaging is underway, wherein, there is a shift from transistor scaling to system scaling and integration through advanced packaging. For advanced packaging, interconnect scaling is a key driver, with interconnect density requirements for chip-to-substrate microbump pitch below 5 μm and half-line pitch below 1 μm for Cu redistribution layer (RDL). Here, we present a comprehensive theoretical comparison of thermal cycling behavior in accordance with JESD22-A104D standard, intermetallic thickness evolution, and steady-state thermal analysis of Cu-microbump assembly for different bonding materials and substrates. Bonding materials studied include solder caps such as SAC105 (Sn98.5Ag1.0Cu0.5), eutectic Sn-Pb (Sn63Pb37), eutectic Sn-Bi (Sn42Bi58), Pb95Sn5, Indium, and Cu-Cu TCB structure. Effect of substrates including Si, glass and FR-4 is evaluated for various microbump structures with varying pitches (85 µm, 40 µm, 10 µm, and 5 µm) on their fatigue life. Results indicate that for Cu-microbump assemblies at an 85 µm pitch. The Pb95Sn5 exhibits the longest predicted fatigue life (3267 cycles by Engelmaier and 452 cycles by Darveaux), while SAC105 shows the shortest (320 and 103 cycles). Additionally, the Cu-Cu TCB structure achieves an estimated lifetime of approximately 7800 cycles, which is significantly higher than all solder-based Cu-microbump assemblies. The findings contribute to advanced packaging applications by providing valuable theoretical references for optimizing solder materials and structural configurations. Full article

Schmitt Triggers are essential building blocks in noise-resilient systems and are useful in managing switching behavior in low-power designs. Yet, as CMOS technologies scale down, their designs become increasingly challenging. This paper presents a comprehensive investigation into the performance and reliability of multiple Schmitt Trigger topologies across two CMOS technology nodes (180 nm and 45 nm), with a particular focus on transistor sizing and layout optimization through multi-finger transistor structures. A series of pre-layout and post-layout simulations reveal that fingered implementations significantly enhance hysteresis robustness, switching speed, and delay consistency in PVT variations. Notably, post-layout results in 45 nm technology demonstrate remarkable improvements in both speed and power efficiency. This highlights the inadequacy of schematic-level models to predict the true behavior of fingered transistor configurations. Additionally, we explored the implications of finger designs on reliability concerns including electromigration and IR drop to determine the tradeoff between interconnect reliability optimization and internal routing. The findings establish practical design guidelines for optimizing number of fingers based on device width and technology node, offering new insights into layout-aware Schmitt Trigger design for high-performance and area-constrained applications. Full article