LTSPICE Memristor Neuron with a Modified Transfer Function Based on Memristor Model with Parasitic Parameters ^†

Abstract

Memristors, as novel one-port electronic elements, have very good memory and commutating properties, insignificant power consumption, and a good compatibility to present CMOS integrated chips. They are applicable in neural networks, memory arrays, and various electronic devices. This paper proposes a simple LTSPICE model of an adapted activation function and a neuron built on memristors. In the neuron, synaptic bonds are implemented by single memristors, allowing a decreased circuit complexity. The summing and scaling schemes are based on op-amps and memristors. The applied modified tangent-sigmoidal activation function is implemented with MOS transistors and memristors. Analyses and simulations are conducted using a simple and high-rate operating memristor model with parasitic parameters—resistance, inductance, capacitance, and small-signal DC components. Their influence on the normal operation of the memristors in the neuron is analyzed, paying attention to their usage and adjustment. The proposed memristor-based artificial neuron is analyzed in MATLAB–Simulink and LTSPICE simulators. A comparison between the derived results confirms the correct operation of the proposed memristor neuron. The generation and analyses of the suggested memristor-based neuron is a significant and promising step for the design and engineering of high-complexity neural networks and their realization in ultra-high-density integrated neural circuits and chips.

1. Introduction

The electro-chemical communications in biological neural cells, analyzed in human brain and other organisms are the main motivating reasons for the generation of artificial and spiking neural networks [1]. Artificial neural networks and schemes are energy-effective and high-speed ones. They could perform complex computing tasks and have promising applications in low-power electronic circuits for artificial intelligence (AI) [2]. Neural networks based on MOS transistors and optical devices were regularly used in the past. Nowadays, some of the newest achievements in this area are the neural networks, based on memristors, which are generally used for realization of synaptic weights [3,4]. Memristors, also known as “memory resistors”, are two-terminal, passive electronic components that have the ability to partially hold their state and resistance in relation to the passed electrical charges [5]. Their state and conductance could be changed by applied voltage or current impulses. Many times, memristors are employed as tunable resistors [6,7]. Frequently, doped metal oxides are utilized for memristor realizations. Generally, memristors have very low power utilization, good switching and memory properties, high operating rate, nano-scale dimensions, and very good compatibility with the present integrated CMOS circuits [8]. Usually, memristors are fabricated as crossbars and arrays, included in integrated circuits. They are easily applicable in neural networks, memory arrays, and various other electronic circuits and devices. In artificial neural networks, they are commonly used for synaptic realization [9,10]. Various types of memristor-based synapses and neurons are reported in the scientific literature [7,8]. A drawback in some synapses, founded on single memristors and MOS transistors, is the realization of only positive synaptic weights. Other complex neural schemes contain two and more memristor elements per synapse. Bridge memristor synapses guarantee negative, zero, and positive synaptic weights [7]. Their key disadvantage is the bigger number of memristors per synaptic connection. Commonly, three or more memristor elements are employed, and two or more op-amps are used. An opportunity for realization of each synapse by only one memristive element is available, and this significantly decreases the neural circuits’ complexity [11]. Sometimes, the variations in parameters of memristors could affect the synaptic weights, and thus the robustness, accuracy, convergence, efficiency, and operating speed of artificial neurons could be changed. For efficient analysis of memristor-based neurons in complex neural networks, high-speed and simple SPICE memristor models are needed for reducing the simulation time [11,12,13].

In this work, an improved and simplified LTSPICE memristor model with parasitic parameters [14,15] is proposed. The unavoidable parasitic capacitance, inductance, and resistance are addressed. Additional small-signal DC voltage and current sources are used for expressing the shifting of the cross-section of the i-v curve according to the origin of the coordinate system at high-frequency signals [14,16]. Activation voltage threshold [16] is incorporated in the suggested memristor models. Along with the other SPICE family products, like Or CAD PSPICE, HSPICE, Micro-Cap, and others, LTSPICE is a preferable software simulator [11,12,17]. It has a user-friendly interface and free license. It has good convergence properties and no restrictions on the number of electronic elements and their connections [11,12]. The LTSPICE software simulator, together with MATLAB and Simulink, are used for the conducted analyses in this work.

After a detailed reference check, it was established that a few publications provide complete structures of memristor synapses, neurons, and activation functions, modeled in electronic simulators, and corresponding results with comparisons. This was the general motivation for the present research. The purpose of this paper is to propose a simple memristor neuron in LTSPICE, having negative and positive synaptic weights, using the least number of electronic elements. A total implementation of a memristor-based neuron in LTSPICE is presented. A modified activation function with MOS transistors and memristors is suggested. A modified and simple memristor model with parasitic parameters is presented. The influence of related parasitic parameters on the normal operation of the memristor-based neuron is analyzed in LTSPICE.

The rest of the paper is presented as follows. Section 2 briefly presents memristor structure, operation, and modeling. Experimental investigation, adjustment in MATLAB–Simulink, generation, and analysis of the corresponding LTSPICE model are described in Section 3. The proposed LTSPICE memristor-based neuron and transfer functions are discussed in Section 4. The results derived are compared and commented on in Section 5. A discussion is provided in Section 6. The conclusion of the paper is presented in Section 7.

2. Memristors, Modeling, and LTSPICE Implementation

Here, a brief explanation of memristors’ fundamentals is first offered for a better understanding of their structure, operation, modeling, and investigations [13,16].

2.1. Structure of Memristor Elements and Their Operation

There are many kinds of memristors—metal-oxide-based ones, metal-chalcogenide, polymeric, ferroelectric, and others [18,19,20]. Metal-oxide [20] and metal-chalcogenide memristors [18,19] are in the focus of the present research, owing to their stable characteristics, good memory, and switching properties, which are based on passing of electric charges under applied voltage or current electric pulses. For better understanding of their operation, a simple schematic of a metal-oxide memristor is presented in Figure 1a. It contains two metallic electrodes, denoted as anode (a) and cathode (c). The active layer is based on a metallic oxide, partially doped by oxygen vacancies [20]. The size of the doped layer is denoted as w, while the complete memristor structure has a length of D. The state variable x is represented as a ratio between the sizes of the doped layer and those of the whole memristor element [5]. It is restricted in the scope between zero and one, owing to the limited sizes of the memristor element.

The main parasitic parameters are as follows: resistance, inductance, and capacitance [14,15]. The parasitic resistance is denoted by R_par, and it represents the unavoidable resistance of the metallic electrodes. The parasitic inductance is represented as L_par. It is related to generation of magnetic fields around the current paths in the memristor [14]. Parasitic capacitance C_par is related to the equivalent elementary capacitor, created between the metallic electrodes of the memristor [14]. Different models are available, related to the equivalent schematics of the metal-oxide memristor [14]. In [15], parasitic capacitance C_par is directly connected to the memristor nanostructure. In the present research, another model is proposed. It is related to attachment of the parasitic capacitance to the input terminals of the memristor. In this way, the other possible and additional capacitances are included in the considered capacitance [14]. The additional small-signal DC voltage and current sources J_par and L_par are included for representation of the shifting of the i-v pinched hysteresis loop for middle and high-frequency signals [14,15]. Figure 1b represents the corresponding equivalent scheme of the metal-oxide memristor. The memristor nanostructure is presented, according to the scheme of Figure 1a, as a series connection of two state-dependent and nonlinear resistors [5,16].

The current–voltage relations of the discussed parasitic elements are presented with Formula (1) [15]. They will be utilized in the next paragraphs for memristor modeling.

$$v_{R_{par}}=R_{par}{i}_{L_{par}};v_{L_{par}}=L_{par}{\displaystyle \frac{d{i}_{L_{par}}}{dt}};i_{C_{par}}=C_{par}{\displaystyle \frac{d{v}_{total}}{dt}}$$

(1)

2.2. Memristor Modeling

In the theory of memristor modeling, at least two equations are needed for defining a memristor model [16]. The first one represents the current-voltage relation. It includes the memristance M(x) or the memductance G(x), which are state-dependent quantities [16]. The following equation relates the memristor voltage (or current) to the time derivative of memristor state variable x [5]. A big assembly of regularly employed models of voltage-controlled memristors, like these of Strukov–Williams [5], Joglekar [21], Biolek [10], and Prodromakis [22] is described by the next system (2).

$$\left|\begin{array}{l}{v}_{mem}=M\left(x\right)i_{mem}=\left[R_{ON}x+R_{OFF}\left(1-x\right)\right]i_{mem}\\ {\displaystyle \frac{dx}{dt}}=\dot{x}=k·i_{mem}\left(v_{mem}\right)·f\left(x\right);x_{t=0}=x_0\end{array}\right.$$

(2)

The measures R_ON and R_OFF are the ON-state and OFF-state memristances, k is a physical parameter of the memristor element, i_mem and v_mem are the memristor voltage and current, x₀ is the initial value of the state variable at time t = 0, and f(x) represents a window function [11]. It is applied for restricting the memristor state variable in the range between zero and unity.

In the next paragraph, the proposed memristor models B_6m and B_6par are discussed.

2.3. The Proposed Memristor Model (B_6m)

The proposed modified memristor model without parasitic parameters is denoted as B_6m and is presented in Formula (3). The first equation relates the memristor current i_mem to its voltage v_mem. The quantities R_ON and R_OFF are the limiting values of its memristance. The initial value of the state variable is x₀. The third expression represents the state differential equation. It is based on the standard Lehtonen–Laiho model, according to the time derivative of the state variable [20]. The quantity η is a polarity coefficient. For a forward-biased memristor, it has a value of 1, and it is −1 if the memristor is connected in a reverse direction. The applied window function is the standard and simple parabolic Strukov–Williams window. A voltage activation threshold v_thr is applied in the model. The final expression presents a smooth and differential step-like function; it is very similar to the classical Heaviside step function [9]. The coefficient m has negative values and determines the steepness of this function. If the memristor voltage v_mem is lower than the activation threshold v_thr, then the element behaves as a simple and linear resistor. In this mode, the state variable has a constant value [16]. When the memristor voltage is equal or higher than the activation threshold, then the state variable changes proportionally to the time integral of the applied memristor voltage.

$$\left|\begin{array}{l}{v}_{mem}=\left[R_{ON}x+R_{OFF}\left(1-x\right)\right]·i_{mem}\\ x_{\left(t=0\right)}=x_0\\ {\displaystyle \frac{dx}{dt}}=\dot{x}=\eta ·k·{v_{mem}}^3·\left(x-x^2\right)·f_{thr}\left(v_{thr},v_{mem}\right)\\ f_{thr}\left(v_{thr},v_{mem}\right)={\displaystyle \frac{1}{1+\exp \left[m·\left(\left|v_{mem}\right|-v_{thr}\right)\right]}}\end{array}\right.$$

(3)

The first equation in (3) represents symmetrical current–voltage relations [5]. It is based on Strukov–Williams memristor model [5].

The modified memristor model with parasitic parameters is denoted as B_6par and is presented with system (4). It is founded on (2) and (3) and on the memristor model presented in Figure 1b.

$$\left|\begin{array}{l}{v}_{mem}=i_{mem}·\left[R_{ON}x+R_{OFF}\left(1-x\right)\right],x\left(t=0\right)=x_0\\ {\displaystyle \frac{dx}{dt}}=\dot{x}=\eta k{v_{mem}}^3\left(x-x^2\right){\displaystyle \frac{1}{1+\exp \left[m·\left(\left|v_{mem}\right|-v_{thr}\right)\right]}}\\ i_{Cpar}=C_{par}{\displaystyle \frac{d}{dt}}{v}_{total};i_{Lpar}=i_{Rpar}=i_{mem}-J_{par}\\ i_{total}=i_{Lpar}+i_{Cpar}\\ -v_{total}+i_{Lpar}{R}_{par}+v_{mem}-E_{par}+L_{par}{\displaystyle \frac{d}{dt}}{i}_{Lpar}=0\end{array}\right.$$

(4)

The current through the parasitic capacitance i_Cpar is expressed, applying the definition for a current through a capacitor [16]. The current through the parasitic inductor is expressed as a difference between the current through the memristor and the current of the DC current source J_par, according to the topology of the presented schematic. The total input current i_total is expressed by an algebraic summation of the currents through the parasitic inductor and capacitor, according to the KCL. The final equation is written for the loop, including the input signal v_total, the parasitic resistor R_par, and inductor L_par, the additional DC voltage source E_par, and the memristor, according to the KVL.

The inclusion of the discussed parasitic parameters additionally increases the memristor model complexity. In many cases and at different frequencies, only one or two of the discussed parasitic parameters are really needed. For keeping the memristor model with a comparatively low complexity, only the important parasitic parameters, which affect the normal operation of the memristors in a significant extent, should be included. The parasitic parameters with a low influence could be ignored.

3. Experimental Investigation, Adjustment in MATLAB–Simulink, and Generation and Analysis of the Corresponding LTSPICE Memristor Model

3.1. Experimental Measurements

Here the utilized experimental setup equipment for the measurement of the current–voltage relations of Knowm memristors are discussed [18,19]. Usually, Knowm memristors are related to asymmetrical i-v relations. The memristors under analysis are included in integrated circuits, presented in Figure 2a. An electronic breadboard and a digital oscilloscope are also used. A computer with intel i5, 2-core 2.4 GHz processor, 512 SSD, 8 GB RAM, and MS Windows 10 Pro is used for computer simulations. As specialized software, MATLAB–Simulink [23,24] version R2016a and LTSPICE XVII [12,13] are utilized for the present analyses. One of the Knowm memristors is randomly selected for the investigations. A limiting resistor with a value of 10 kΩ is connected in a series to the memristor element. It is applied for restricting the memristor current and for protection of the memristor element from high-valued currents [25].

A principal schematic related to Figure 2a is presented in Figure 2b. The memristor voltage denoted as v_total is applied to the horizontal channel of the oscilloscope. Its vertical channel is connected to the limiting resistor R, whose voltage is proportional to the memristor current. This schematic is used for visualization and recording of the current–voltage relations of the Knowm memristor at applied different sine-wave and pulse signals at different amplitudes and frequencies. The i-v characteristics are first visualized and then recorded as .csv files, which are converted to .xls format and applied for parameter estimation in Simulink, described in Section 3.2 [23,24].

3.2. Adjustment of the Proposed Memristor Model in MATLAB–Simulink, According to the Experimental Data of Knowm Memristors [19]

The modified memristor model with parasitic parameters, denoted as B_6par and presented by (4), is tuned in the MATLAB–Simulink environment, utilizing experimentally recorded current–voltage relationships of self-directed channel Knowm memristors [19]. The initial values of the model’s parameters are randomly selected. Two .xls files are used. The first one contains two columns. The first column represents the time variable, sampled with a time step of 100 ps, corresponding to a sample frequency of 10 GHz. The time variable is denoted as t_out. The second column corresponds to the sampled voltage signal, applied to the Simulink memristor model under analysis. This signal is denoted as v_total. The second .xls file has a similar structure, but its second column represents the experimental current of the memristor element. It is denoted as i_mes. A Simulink model is generated according to system (4). The described above .xls files are used as a voltage source and as a reference memristor current, respectively. As an output signal, the Simulink model generates the simulated memristor current, denoted as i_total. The parameter estimation procedure is based on gradient descent algorithm. As a cost function, the squared difference between the simulated and the experimental memristor currents is used. The standard number of iterations is about 100. The end of the estimation procedure is reached when the number of iterations is finished or when the cost function is equal or lower than a previously determined value [23,24]. After finishing the parameter estimation procedure, a low relative error of about several percent between the experimental and the simulated i-v relations is obtained. Minimization of the root mean square error (RMSE) between the experimental and simulated characteristics is reached.

The trajectories of the model’s parameters during estimation process are presented in Figure 3a. Their normalized values are presented. The time diagrams of experimental and simulated memristor currents, together with the state variable and the applied voltage, are given in Figure 3b for their visual comparison. Additional comparison is presented using the simulated and experimental i-v relations, shown in Figure 3c. It is visible that a good proximity between these characteristics is established.

The derived optimal values of memristor model parameters after finishing the optimization procedure are R_par = 8.16 Ω, L_par = 0.51 pH, J_par = −1.08 uA, E_par = 0.086 V, C_par = 77.2 pF, k = 132440, x₀ = 0.9844, R_ON = 7077.9 Ω, R_OFF = 99.915 kΩ, m = −527.98, and v_thr = 0.1998 V.

3.3. Generation and Analysis of the Corresponding LTSPICE Memristor Models

Using Equation (3) and the memristor model parameters, discussed in the previous Section 3.2, LTSPICE memristor library model without parasitic parameters is generated. It is denoted as B_6m. The corresponding LTSPICE code is presented below for additional discussion.

• . subckt B6m a c Y
• .params m0=10e3 ron=7077.9 roff=99.915e3 k=132.44e3 vthr=0.1998
• C1 Y 0 {1}
• . IC V(Y)={(roff-m0)/(roff-ron)}
• R1 Y 0 10G
• G2 0 Y value={(k*pow(V(a,c),3)*(V(Y)*(1-V(Y))))*(1/(1+exp(−527.987*(abs(V(a,c))-vthr))))}
• G1 a c value={V(a,c)*((1/(ron*(V(Y))+roff*(1-V(Y)))))}
• .ends B6m

The code starts with the LTSPICE command “.subckt”, defining the new circuit element. It is followed by its abbreviation “B6m” and its main terminals—anode “a” and cathode “c”. The terminal Y is an optional one. It could be placed for the measuring of the memristor state variable x. The main model parameters are visualized in the next row of the code. This is followed by the integrating capacitor C₁, connected between the ground and the terminal Y. Its voltage is proportional to the state variable x. The next row determines the initial value of the state variable x₀, using the initial memristance m₀, and the ON-state and OFF-state resistances. The fifth row introduces an additional resistor—R₁, connected in parallel to the integrating capacitor C₁. The current of the controlled source G₂, presented in the next row, is proportional to the time derivative of memristor state variable x. It corresponds to system (3). The voltage across the memristor is denoted as V(a,c). The applied parabolic window function is (V(Y)*(1-V(Y)))), where V(Y) is related to the state variable x. The dependent current source G₁ represents the memristor current. The presented LTSPICE code finishes with the command “.ends”. The presented code could be easily adapted for use in another SPICE family software products, using Verilog-A [26]. It could be an alternative for analysis of composite- and halide-perovskite-based memristors, with applications in logic gates and functions. Noises in electronic schemes affect to some extent the normal operation of memristors and memristor-based circuits [27,28]. Usually, they are related to fluctuations of some properties and parameters of the materials. The noises slightly affect memristor accuracy, read/write operations, and memory and switching properties.

For the conducted analyses and simulations, LTSPICE software version XVII is utilized. The proposed memristor model B_6m is analyzed at sine and impulse signals, for both hard-switching and soft-switching modes [6]. The derived current–voltage relationships at sinusoidal voltage with amplitude of 1.1 V and different frequencies are presented in Figure 4a–c for verification of the model’s proper operation. It is clear that when the frequency increases, the area of the i-v pinched hysteresis loop decreases. The observed results are in a good agreement with the main features and properties of the memristor elements [13,16].

The alteration of memristance at applied positive impulse voltage is represented in Figure 5a. It is visible that during the impulses, the memristance decreases. During the pauses, the memristance has a constant value. The observed phenomenon is related to the memory effect. The results obtained from the analysis of the memristor model at negative voltage pulses are presented in Figure 5b. During the pulses, the memristance increases. The proposed memristor model is tested at bipolar pulses as well. The derived results are presented in Figure 5c.

The proposed LTSPICE memristor model with parasitic parameters is denoted as B_6par. It is based on the previously discussed memristor model B_6m and the discussed parasitic parameters—resistance, inductance, capacitance, and the small-signal DC voltage and current components. The equivalent schematic of model B_6par in LTSPICE simulator is presented in Figure 6. It corresponds to the principal schematic of this modified memristor model, as presented in Figure 1a.

The LTSPICE code, corresponding to Figure 6, is presented below. The terminals of the memristor are denoted as in₁ and in₂. The parasitic capacitance C_par is connected between these terminals. The structure of the code corresponds to the schematic presented in Figure 6 and Formula (4). For generation of the circuit element, corresponding to the described LTSPICE code, the interested readers should first create the memristor model B_6m.

Additional and detailed explanations about generation of the respective LTSPICE circuit elements are presented at the following link:

https://github.com/mladenovvaleri/Advanced-Memristor-Modeling-in-LTSpise (accessed on 12 August 2025)

9.

.subckt b6par in1 in2

10.

Cpar in1 in2 77.2p

11.

Rpar te in1 8.16

12.

Lpar mid in2 0.51p

13.

I§Jpar mid te −1.08µ

14.

V§Epar mid be 0.086

15.

XU1 te be B6m

16.

R1 be 0 10G

17.

.lib C:\Users\StoyanKirilov\Desktop\LTSPICE_MODELS\b6m.cir

18.

.backanno

19.

.ends b6par

Figure 7 presents a short comparison between the proposed memristor models B_6m and B_6par, according to the basic characteristics of the memristors. Figure 7a–c are related to simulations of these memristor models at sine-wave signals at a given amplitude and different frequencies. At the low frequency of 2 kHz, their behavior is almost identical. At 10 kHz and 20 kHz, the current–voltage relations are quite different one to another, owing to the influence of the parasitic inductance and capacitance.

The analyses conducted at pulse signals are presented in Figure 8a–c. It is visible that the parasitic parameters affect the memory and commutating properties of the memristors. Memory properties are very important during the adjustment of synaptic weights in memristor-based neural networks.

4. The Suggested Memristor-Based Artificial Neuron

In this Section, the organization and functioning of the suggested memristor-based artificial neuron are described and commented.

4.1. The Structure of a Simple Memristor-Based Artificial Neuron

A block scheme of an artificial memristor-based neuron is presented in Figure 9 for visualization of its basic structure and functioning. The input signals are denoted as x₁, x₂, x₃, x₄, x₅, and x₆. The bias signal has a value of unity.

These signals are forwarded to the memristor-based synaptic weights, represented as w₁, w₂, w₃, w₄, w₅, and w₆. The bias weight is denoted as b₁. Each synaptic weight is realized by a single memristor, whose conductance determines the synaptic weight. The signals after the synaptic weights are directed to an adder, which is realized with memristors and op-amps [6]. The output signal of the adder is denoted as y_in. This signal is applied to the input of a modified tangent-sigmoidal activation function, based on memristors and MOS transistors. The output signal of the memristor neuron is expressed as y. The operation of the commented memristor-based artificial neuron is based on feed-forward transfer of input signal and back-error propagation algorithm for updating the synaptic weights [6].

4.2. The Realization of Memristor Adder and Synaptic Connections

A principal scheme of the synaptic connections and the adder of the memristor-based neuron under analysis is presented in Figure 10 for further discussion. The memristors M₁, M₂, and M₃ are related to negative synaptic weights, and memristors M₄, M₅, M₆, and M₇ ensure positive weights [6]. The element M₇ realizes the bias of the neuron. The resistances of the memristors M₈, M₉, and M₁₀ are constants, with a value of 10 kΩ. They could be replaced by linear and simple resistors. The memristors M₈ and M₁₀ ensure the feedback for the applied op-amps. The connection between the used op-amps is realized with the memristor element M₉.

Utilizing Kirchhoff’s laws (KCL and KVL), and bearing in mind that M₈ = M₉ = M₁₀, the output signal of the adder y_in is derived [6]:

$$y_{in}=-{\displaystyle \frac{M_8}{M_1}}{x}_1-{\displaystyle \frac{M_8}{M_2}}{x}_2-{\displaystyle \frac{M_8}{M_3}}{x}_3+{\displaystyle \frac{M_{10}}{M_4}}{x}_4+{\displaystyle \frac{M_{10}}{M_5}}{x}_5+{\displaystyle \frac{M_{10}}{M_6}}{x}_6+{\displaystyle \frac{M_{10}}{M_7}}{x}_b$$

(5)

The coefficients in front of the signals in (5) represent the synaptic weights:

$$w_1=-{\displaystyle \frac{M_8}{M_1}};w_2=-{\displaystyle \frac{M_8}{M_2}};w_3=-{\displaystyle \frac{M_8}{M_3}};w_4={\displaystyle \frac{M_{10}}{M_4}};w_5={\displaystyle \frac{M_{10}}{M_5}};w_6={\displaystyle \frac{M_{10}}{M_6}};b_1={\displaystyle \frac{M_{10}}{M_7}}$$

(6)

4.3. Synaptic Weights Adjustment

The process of synaptic weights tuning is realized by applying external voltage pulses, directed to the respective memristor [3,6]. Let us assume that the applied pulses for adjustment are at a level higher than the activation threshold v_thr. Then, from (3), the following state differential Equation (7) could be obtained:

$${\displaystyle \frac{dx}{dt}}=\dot{x}=\eta ·k·{v_{mem}}^3·x\left(1-x\right)$$

(7)

After separating the memristor state variable x and the time variable t, the next differential Equation (8) is derived:

$${\displaystyle \frac{dx}{x\left(1-x\right)}}=\eta ·k·{v_{mem}}^3·dt$$

(8)

When the initial value of the memristor state is x₁, then its alteration to a new value x₂ is obtained for the voltage pulse duration T_max, according to the following equation:

$${\displaystyle \underset{x_{\min }}{\overset{x_{\max }}{\int }}\frac{1}{x\left(1-x\right)}}dx=\eta ·k·{v_{mem}}^3·{\displaystyle \underset{0}{\overset{T_{\max }}{\int }}dt}=k·{v_{mem}}^3·T_{\max }$$

(9)

The needed pulse duration T_max is expressed after solving Equation (9). It is represented by the following formula:

$$T_{\max }={\displaystyle \frac{\ln \left(x_{\max }\right)+\ln \left(1-x_{\min }\right)-\ln \left(x_{\min }\right)-\ln \left(1-x_{\max }\right)}{\eta k{v}^3}}$$

(10)

The process of tuning the weights of memristor synapses by voltage impulses is represented in Figure 11. Figure 11a is derived at positive voltage pulses, and Figure 11b is obtained for negative pulses, respectively. The applied sequence of positive pulses leads to decremented memristance and increasing the state variable, respectively. Incremental memristance and decrease in the memristor state variable are obtained at negative voltage impulses. In both incremental and decremented memristances, the pulses are with a duration of 50 µs and a level of 0.45 V. The pulse sequence is with a duty cycle of 50%.

A comparison of the results derived by formula (10) and the simulation results from Figure 11 is conducted. In the case of applied positive voltage pulses, let the initial state variable have a value of x_min = 0.1. It corresponds to a memristance with a value of M_max = 90631 Ω. The respective synaptic weight is w₁ = 10,000/M_max = 0.1103. According to Figure 11a, the final value of the state variable is x_max = 0.9328, corresponding to a memristance with a value of M_min = 13,318 Ω. The corresponding synaptic weight is w₂ = 10,000/M_min = 0.7509.

The analytical calculation of the needed effective duration of the applied pulses with a level of 0.45 V is:

$$T_{\max }={\displaystyle \frac{\ln \left(0.9328\right)+\ln \left(1-0.1\right)-\ln \left(0.1\right)-\ln \left(1-0.9328\right)}{1·132440·{0.45}^3}}=400\mu s$$

After consideration of Figure 11a and bearing in mind that the duty cycle of the pulse sequence is 50%, the same result is derived. Similar results are obtained at negative voltage pulses. A good closeness between the results is established, which confirms the proper operation of the modified memristor model under analysis.

4.4. A Modified Transfer Function, Based on Memristors and MOS Transistors

The suggested MOS transistor-memristor activation function is represented with a principal schematic, which is shown in Figure 12. The input signal y_in is forwarded from the output of the previously discussed adder. The memristors M₁₁ and the MOS transistors T₁, and T₂ conduct a nonlinear conversion on the input signal y_in [6]. The memristors M₁₂ and M₁₃ form a voltage divider, which has a voltage transmission coefficient with a value of 10. The voltage drops across the memristors are lower than the activation threshold, and due to this, these elements behave as linear resistors. The operational amplifier operates as a buffering element. It separates the described transfer function from the next neurons. The circuit presented in Figure 12 realizes a modified tangent-sigmoidal transfer function.

The realization of the above-described modified transfer function in LTSPICE simulator is illustrated in Figure 13a. The input signal could be sinusoidal or impulse one. In the present case, it has the following expression: v_out = 0.09 × tanh(3 × v_in). It is applied for analysis of the proposed transfer function.

The controlled voltage source B₁ is used for representation of an approximate mathematical expression of the modified tangent-sigmoidal function. Its signal “out₁” is utilized for comparison with the output signal “out”, which corresponds to the real output signal y. Figure 13b is placed for graphical presentation of the described output signals as functions of the input voltage and for their visual comparison. It is observable that the output signals are very close to one another. The memristors M₁₁, M₁₂, and M₁₃ operate in a linear mode, i.e., these elements are with constant resistance. In some cases, instead of M₁₁, a series connection of memristors could be applied to prevent exceeding the memristor activation threshold v_thr [6]. When a memristor operates as a linear resistor, its power consumption is about 3 µW. Otherwise, if it is operating in a soft-switching mode, its power usage is between 30 µW and 3 mW.

Based on the commented modules, a memristor-based artificial neuron is created and analyzed in the LTSPICE simulator. The corresponding scheme is represented in Figure 10 for further discussion. The voltage sources v₁–v₆ and v_b ensure the input signals x₁–x₆ and x_b. They are represented by sequences of pulses with different levels.

Table 1. Input signal levels for the memristor neuron for five cases.

Case	vin1, mV	vin2, mV	vin3, mV	vin4, mV	vin5, mV	vin6, mV	vb, mV
I	20	30	40	50	−10	−20	−30
II	−10	10	20	30	40	50	−20
III	−20	−10	10	20	30	40	10
IV	10	20	−30	30	20	−10	20
V	−30	30	10	40	−20	−20	10

represents the levels of the input signals for five different cases.

The synaptic weights and corresponding memristances, which are applied for analysis of the suggested memristor neuron in the MATLAB [23,24], Simulink, and LTSPICE simulators, are shown in

Table 2. Synaptic weights and corresponding memristances, M₇ = M₈ = M₉ = 10 kΩ.

Synapse	1	2	3	4	5	6	7
Weight	−0.2	−0.5	−1	1	0.5	0.2	0.5
M, kΩ	50	20	10	10	20	50	20

.

Figure 13a presents a schematic of the proposed transfer function. Figure 13b represents the input and the output signals of the modified transfer function.

Figure 14 presents the realization of the proposed memristor-based neuron in LTSPICE.

The applied LTSPICE memristor and neuron models are uploaded and available for use at the link: https://github.com/mladenovvaleri/Advanced-Memristor-Modeling-in-LTSpise [11] (accessed on 12 August 2025).

The time diagrams of the input and output signals of the neuron in LTSPICE are presented in Figure 15a,b.

5. Comparison and Analysis of Derived Results

In this Section, a comparison of results, derived in the MATLAB, Simulink, and LTSPICE analyses of the suggested memristor-based neuron is shown and commented. The derived results, according to the time diagrams of the input and output signals of the neuron in Simulink are presented in Figure 16a. The corresponding schematic in Simulink is presented in Figure 16b.

The sources for input signals are of type “From spreadsheet”. The synaptic weights are presented with “Gain” elements. The modified transfer function is presented with a “MATLAB function” block in the Simulink environment.

A Comparison of the Results Derived in MATLAB–Simulink and LTSPICE

A short comparison of the results, obtained in MATLAB–Simulink and LTSPICE software, is represented in

Table 3. Input and output signals of the neuron from MATLAB–Simulink and LTSPICE.

Case	Y_in MATLAB–Simulink mV	Y_in LTSpice mV	Relative Error Between Y_in MATLAB and Y_in LTSPICE, %	Y MATLAB–Simulink, mV	Y LTSpice mV	Relative Error Between Y MATLAB and Y_in LTSPICE, %
I	−33	−33.03	0.091	−8.88	−8.57	3.49
II	37	37.4	1.08	7.27	7.4	1.79
III	47	47	0	12.6	11.89	5.63
IV	66	66	0	17.6	17.16	2.5
V	12.2	12	1.67	3.24	3.1	4.32

. The average value of the relative error between the output signals is about 3.546%. This low value of the relative error confirms the correct functioning of the suggested memristor-based artificial neuron.

During the process of utilization of the neuron, the parasitic parameters do not significantly affect the signals’ transmission. The influence of the parasitic parameters on the change in the memristances and the respective synaptic weights during their adjustment by pulses is presented in

Table 4. Influence of the parasitic parameters on the adjustment of synaptic weights and memristances.

Synapse	1	2	3	4	5	6	7
Initial values of the synaptic weights	−0.2	−0.5	−1	1	0.5	0.2	0.5
Initial values of the memristances, kΩ	50	20	10	10	20	50	20
Weights achieved according to model B6m	−0.23	−0.68	−1.45	1.45	0.68	0.23	0.68
Memristances according to model B6m, kΩ	43.9	14.6	6.9	6.9	14.6	43.9	14.6
Weights achieved according to model B6par	−0.21	−0.52	−1.52	1.52	0.52	0.21	0.52
Memristances according to model B6par, kΩ	47.8	19.1	6.6	6.6	19.1	47.8	19.1

. In the first and second rows, the initial values of the synaptic weights and the corresponding memristances are presented. A pulse sequence of 10 pulses with a level of 0.4 V, duty cycle of 50%, and a pulse duration of 5 µs is used. For comparison, the considered memristor models B_6m and B_6par are applied. The derived results, according to the achieved memristances and synaptic weights are placed in the next four rows. It is visible that the error between the synaptic weights is about 4.3%. The conclusion is that for low and middle frequency signals, parasitic parameters do not strongly affect the normal operation of the neuron. For high-frequency signals, parasitic capacitance affects the plateau of the pulses, and it should be taken into account during the weight-adjustment process.

6. Discussion [11,13,16]

During the analyses in MATLAB and LTSpice, the standard Biolek, Lehtonen–Laiho and Knowm memristor models are applied, together with the discussed modified memristor models B_6m and B_6par. A short comparison of the utilized memristor models is conducted. For this purpose, several significant criteria, such as the model complexity, accuracy, operating frequency, switching properties, and simulation time, are used [11,13,16].

The complexity of a memristor model is proportional to the number of elementary mathematical operations included in the respective system of describing equations [16].

Model’s accuracy is related to its ability for precise representation of the experimentally recorded current–voltage characteristics, with a minimal RMS error [13].

The operating frequency depends on the capability of the memristor model to realistically represent the nonlinear ionic dopant drift at low-, middle-, and high-level signals, ensuring a broad range for alteration of the state variable. Low frequencies are between 1 and 1 kHz, middle frequencies are about 10 kHz, and high frequencies are higher than 10 kHz [11].

The switching properties are related to the ability of a given memristor model to represent the realistic change in the memristance and the respective state variable under applied voltage pulses, for both soft-switching and hard-switching modes [11,16].

Simulation time of a model is related and directly proportional to the complexity of the considered memristor model [11,13].

For analyses and simulations of complex memristor-based circuits, simple, accurate, and fast-operating memristor models are needed [11,16].

The results from the comparison are presented in

Table 5. A comparison of the memristor models under analysis [11].

Memristor Model	Complexity	Accuracy	Operating Frequency	Switching Properties	Simulation Time
K3 [9]	low	average	average	satisfactory	14.7 ms
K5 [20]	high	high	high	good	17.2 ms
Knowm [18,19]	high	high	high	good	17.9 ms
B6m [6]	low	high	high	good	16.1 ms
B6par	high	average	average	satisfactory	17.7 ms

to express the main advantages and disadvantages of the proposed modified memristor models. The proposed modified memristor models are with a comparatively low complexity, high operational frequency, and good accuracy and switching properties. As a little disadvantage of the modified models, their decreased accuracy should be taken into account. They are appropriate for the analysis and simulation of multipart memristor-based circuits and devices.

7. Conclusions

In the end of this paper, it could be concluded that the purpose of the work is achieved, and the related tasks are successfully resolved. Simple, accurate, and fast-operating LTSPICE models of memristors are suggested and applied in the activation function, synapses, and adder for the realization of an artificial neuron. In the applied memristor models, the main and frequently observed parasitic parameters—resistance, inductance, capacitance, and the small-signal DC voltage and current components—are considered. The synaptic connections for positive and negative weights are realized with single memristors and a summing device, implemented with two op-amps. The suggested modified tangent-sigmoidal activation function is based on MOS transistors and memristors. For the conducted analyses and computer simulations, both LTSPICE and MATLAB–Simulink software products are used. The derived results approve the correct operation of the suggested memristor-based neuron. Its main advantages are the simple hardware and software implementations. For its realization, low-power self-directed Knowm memristors with nano-sizes and good compatibility to CMOS integrated chips are applied.

The influence of the parasitic parameters on the normal operations of the memristors at medium and high frequencies is considered mainly during the adjustment of the synaptic weights, as well as during the regime of usage of the memristor neuron. The parasitic parameters and especially the capacitances distort the fronts and plateau of the pulses. The DC voltage and current small-signal sources shift the intersection point of the voltage–current characteristics of the memristors, according to the origin of the Cartesian i-v plane. The ambient temperature also affects the operating mode, but the change in memristor characteristics is very small. The conducted analyses did not expose any serious deviation of the pulse levels from the desired values.

As potential future work on the topic, a more detailed study of the influence of parasitic parameters on the switching and memory properties of the memristors and synaptic weights’ alteration in more complex neural networks is planned, focusing on the extent and significance of the influence of parasitic parameters on the normal operation of neuron and neural networks. The limited bandwidth of the operational amplifiers could also be analyzed, together with some nonlinear relations between the parasitic capacitance and the voltage.

The suggested realization of an artificial memristor-based neuron is a significant step toward novel and high-density neuromorphic electronic circuits and devices.