Search Results (331)

Erbium (${\mathrm{Er}}^{3+}$) emitters are relevant for optical applications due to their narrow emission line directly in the telecom C-band due to the ⁴I_13/2 → ⁴I_15/2 transition at 1.54 μm. Additionally, they are promising candidates for future quantum technologies when embedded in thin film silicon-on-insulator (SOI) to achieve fabrication scalability and CMOS compatibility. In this paper we integrate Er³⁺ emitters in SOI metasurfaces made of closely spaced arrays of nanodisks, to study their spontaneous emission via room and cryogenic temperature confocal microscopy, off-resonance and in-resonance photoluminescence excitation at room temperature and time-resolved spectroscopy. This work demonstrates the possibility to adopt CMOS-compatible and fabrication-scalable metasurfaces for controlling and improving the collection efficiency of the spontaneous emission from the Er³⁺ transition in SOI and that they could be adopted in similar technologically advanced materials. Full article

Protecting sensitive electronic interfaces is critical in industrial applications, where exposure to harsh conditions and fault events is common. This paper reviews and compares circuit techniques for the design of bidirectional protection switches, highlighting key features such as analog switching, high-voltage capability, thermal shutdown, galvanic input isolation, and adjustable current limiting. Based on this review, we propose a universal architecture that combines the most suitable building blocks identified in the literature, with a focus on options that would enable monolithic integration in high-voltage silicon-on-insulator (SOI) technology and capable of delivering up to 2 A at a maximum voltage of 200 V. The proposed architecture is intended as a design guide for realizing a universal switch, rather than a fabricated implementation. To demonstrate system-level interactions, behavioral MATLAB/Simulink (R2024b) simulations are presented using generic components, which show expected functional responses but are not tied to process-specific device models. Full article

This work presents the design and simulation of a time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC) implemented in GlobalFoundries’ 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS process. Motivated by the increasing demand for high-speed electrical links in data center and AI/ML applications, the proposed ADC architecture targets medium-resolution, high-throughput conversion with optimized power and area efficiency. The design leverages asynchronous SAR operation, bootstrapped sampling switches, and a hybrid binary/non-binary capacitive digital-to-analog converter (DAC) to achieve robust performance across process, voltage, and temperature (PVT) variations. System-level modeling using channel operating margin (COM) methodology guided the specification of key circuit blocks, enabling efficient trade-offs between resolution, speed, and power. Post-layout simulations demonstrated effective number of bits (ENOB) performance consistent with system requirements, while Monte Carlo analysis confirmed the statistical yield. The converter achieved competitive figures of merit compared to state-of-the-art designs, as benchmarked against the Murmann ADC survey. This work highlights critical design considerations for scalable mixed-signal architectures in advanced CMOS nodes and lays the foundation for future integration in high-speed SerDes systems. Full article

In this study, we propose a lateral power-reduced surface field FinFET (LPR-FinFET) to achieve high breakdown voltage and low on-resistance. We investigate the electric field distribution within the reduced surface field (RESURF) structure under reverse-biased conditions, as well as forward transfer and output characteristics using TCAD simulation. The proposed LPR-FinFET demonstrates a high breakdown voltage of 247 V and a low specific on-resistance of 0.255 mΩ·cm² with a high-power figure of merit of 239.3 MW/cm². The superior characteristics of our proposed LPR-FinFET show the potential for applications as a lateral power semiconductor using silicon-on-insulator (SOI) technology. Full article

In this paper, we investigate the zero-temperature coefficient (ZTC) characteristics of polycrystalline silicon (poly-Si) single-gate transistors with a silicon-on-insulator (SOI)-like structure, which offers thermal stability over a wide temperature range. While ZTC characteristics have been primarily utilized in analog and memory circuits, systematic analyses for logic transistors remain limited. The ZTC characteristic is quantitatively evaluated by considering various process parameters, including high-density three-dimensional (3D)-stacked structures. The effects of grain boundary (GB) location within the poly-Si, body thickness, and doping concentration on both the ZTC point and its temperature sensitivity are systematically analyzed. A new metric, ΔZTC, is defined to quantify the sensitivity of the ZTC point to the presence or absence of GBs. This metric is applied throughout the analysis. As a result, ZTC characteristics can be effectively optimized through structural parameter adjustment, and these characteristics are maintained or even enhanced when extended to multi-layer architectures. Notably, when GBs are confined to specific layers, the ΔZTC value is reduced by approximately 64.1% at a body thickness of 25 nm and by 62.5% at 7 nm, compared to the single-layer structure, indicating that temperature sensitivity can be significantly suppressed. Full article

We present a highly sensitive and selective gas sensor based on an advanced silicon-on-insulator tunnel field-effect transistor (SOI-TFET) architecture, enhanced through the integration of customized conducting polymers. In this design, traditional metal gates are replaced with distinct functional polymers—PPP-TOS/AcCN, PP-TOS/AcCN, PP-FE(CN)₆³⁻/H₂O, PPP-TCNQ-TOS/AcCN, and PPP-ClO₄/AcCN—which enable precise molecular recognition and discrimination of various target gases. To further enhance sensitivity, the device employs an oppositely doped source region, significantly improving gate control and promoting stronger band-to-band tunneling. This structural modification amplifies sensing signals and improves noise immunity, allowing reliable detection at trace concentrations. Additionally, optimization of the subthreshold swing contributes to faster switching and response times. Thermal stability is addressed by embedding a P-type buffer layer within the buried oxide, which increases thermal conductivity and reduces lattice temperature, further stabilizing device performance. Experimental results demonstrate that the proposed sensor outperforms conventional SOI-TFET designs, exhibiting superior sensitivity and selectivity toward analytes such as methanol, chloroform, isopropanol, and hexane. Beyond gas sensing, the unique polymer-functionalized gate design enables integration of microbial biosensing capabilities, making the platform highly versatile for biochemical detection. This work offers a promising pathway toward ultra-sensitive, low-power sensing technologies for environmental monitoring, industrial safety, and medical diagnostics. Full article

To improve the efficiency and stability of the system, this paper proposes a monolithic integrated optical path design for a cavity optomechanical accelerometer based on a 250 nm top silicon thickness silicon-on-insulator (SOI) wafer instead of readout through U-shape fiber coupling. Finite Element Analysis (FEA) and Finite-Difference Time-Domain (FDTD) methods are employed to systematically investigate the performance of key optical structures, including the resonant modes and bandgap characteristics of photonic crystal (PhC) microcavities, transmission loss of strip waveguides, coupling efficiency of tapered-lensed fiber-to-waveguide end-faces, coupling characteristics between strip waveguides and PhC waveguides, and the coupling mechanism between PhC waveguides and microcavities. Simulation results demonstrate that the designed PhC microcavity achieves a quality factor (Q-factor) of 2.26 × 10⁵ at a 1550 nm wavelength while the optimized strip waveguide exhibits a low loss of merely 0.2 dB over a 5000 μm transmission length. The strip waveguide to PhC waveguide coupling achieves 92% transmittance at the resonant frequency, corresponding to a loss below 0.4 dB. The optimized edge coupling structure exhibits a transmittance of 75.8% (loss < 1.2 dB), with a 30 μm coupling length scheme (60% transmittance, ~2.2 dB loss) ultimately selected based on process feasibility trade-offs. The total optical path system loss (input to output) is 5.4 dB. The paper confirms that the PhC waveguide–microcavity evanescent coupling method can effectively excite the target cavity mode, ensuring optomechanical coupling efficiency for the accelerometer. This research provides theoretical foundations and design guidelines for the fabrication of high-precision monolithic integrated cavity optomechanical accelerometers. Full article

As transistor dimensions continue to scale below 10 nm, traditional MOSFET architectures face increasing limitations from short-channel effects, gate leakage, and variability. FinFETs, especially junctionless FinFETs on silicon-on-insulator (SOI) substrates, offer improved electrostatic control and simplified fabrication, making them attractive for deeply scaled nodes. In this work, we propose a novel Stepped-Spacer Structured FinFET (S³-FinFET) that incorporates a three-layer HfO₂/Si₃N₄/HfO₂ spacer configuration designed to enhance electrostatics and suppress parasitic effects. Using 2D TCAD simulations, the S³-FinFET is evaluated in terms of key performance metrics, including transfer/output characteristics, ON/OFF current ratio, subthreshold swing (SS), drain-induced barrier lowering (DIBL), gate capacitance, and cut-off frequency. The results show significant improvements in leakage control and high-frequency behavior. These enhancements make the S³-FinFET particularly well-suited for Field-Programmable Gate Arrays (FPGAs), where power efficiency, speed, and signal integrity are critical to performance in reconfigurable logic environments. Full article

Nanoparticle floating gate (NPFG) transistors have gained attention as synaptic devices due to their discrete charge storage capability, which minimizes leakage currents and enhances the memory window. In this study, we propose and evaluate a mesh-type floating gate transistor (Mesh-FGT) designed to emulate the characteristics of NPFG transistors. Individual floating gates with dimensions of 3 µm × 3 µm are arranged in an array configuration to form the floating gate structure. The Mesh-FGT is composed of an Al/Pt/Cr/HfO₂/Pt/Cr/HfO₂/SiO₂/SOI (silicon-on-insulator) stack. Threshold voltages (Vth) extracted from the transfer and output curves followed Gaussian distributions with means of 0.063 V (σ = 0.100 V) and 1.810 V (σ = 0.190 V) for the erase (ERS) and program (PGM) states, respectively. Synaptic potentiation and depression were successfully demonstrated in a multi-level implementation by varying the drain current (I_ds) and Vth. The Mesh-FGT exhibited high immunity to leakage current, excellent repeatability and retention, and a stable memory window that initially measured 2.4 V. These findings underscore the potential of the Mesh-FGT as a high-performance neuromorphic device, with promising applications in array device architectures and neuromorphic neural network implementations. Full article

We developed the Global–Local Integrated Topology inverse design algorithm (denoted as the GLINT algorithm), which employs a trajectory-based optimization strategy with waveguide–substrate material-flipping structural modifications, enabling the direct optimization of discrete waveguide–substrate binary structures. Compared to the conventional Direct Binary Search (DBS), the GLINT algorithm not only significantly enhances computational efficiency through its global search–local refinement framework but also achieves a superior 20 nm × 20 nm optimization resolution while maintaining its optimization speed—substantially advancing the design capability. Utilizing this algorithm, we designed and experimentally demonstrated a 3.5 µm × 3.5 µm dual-port wavelength division multiplexer (WDM), achieving a minimum crosstalk of −11.3 dB and a 2 µm × 2 µm 90-degree bending waveguide exhibiting a 0.31–0.52 dB insertion loss over the 1528–1600 nm wavelength range, both fabricated on silicon-on-insulator (SOI) wafers. Additionally, a 4.5 µm × 4.5 µm three-port WDM structure was also designed and simulated, demonstrating crosstalk as low as −36.5 dB. Full article

This study presents a photonic integrated optical sensor based on a dual-polarization microring resonator with angular gratings on a silicon-on-insulator (SOI) waveguide, enabling simultaneous and precise refractive index (RI) and temperature measurements. Due to the distinct energy distributions for transverse electric ($\mathit{TE}$) and transverse magnetic ($\mathit{TM}$) modes in SOI waveguides, these modes show distinct sensitivity responses to the variation in ambient RI and temperature. Simultaneous measurements of both temperature and RI are enabled by exciting both these transverse modes in the microring resonator structure. Furthermore, incorporating angular gratings into the microring resonator’s inner sidewall extends the temperature measurement range by mitigating free spectral range limitations. This work presents a novel approach to dual-polarization microring resonators with angular gratings, offering an enhanced temperature measurement range and detection limit in optical sensing applications requiring an extended temperature range. The proposed structure is able to yield a simulated temperature measurement range of approximately 35 nm with a detection limit as low as $2.99\times {10}^{-5}$. The achieved temperature sensitivity is 334 pm/°C and RI sensitivity is 13.33 nm/RIU for the ${\mathit{TE}}_0$ mode, while the ${\mathit{TM}}_0$ mode exhibits a temperature sensitivity of 260 pm/°C and an RI sensitivity of 76.66 nm/RIU. Full article

This paper presents the first demonstration and comparison of two identical oscillator circuits employing piezoelectric zinc oxide (ZnO) microelectromechanical systems (MEMS) resonators, implemented on conventional printed-circuit-board (PCB) and three-dimensional (3D)-printed acrylonitrile butadiene styrene (ABS) substrates. Both oscillators operate simultaneously at dual frequencies (260 MHz and 437 MHz) without the need for additional circuitry. The MEMS resonators, fabricated on silicon-on-insulator (SOI) wafers, exhibit high-quality factors (Q), ensuring superior phase noise performance. Experimental results indicate that the oscillator packaged using 3D-printed chip-carrier assembly achieves a 2–3 dB improvement in phase noise compared to the PCB-based oscillator, attributed to the ABS substrate’s lower dielectric loss and reduced parasitic effects at radio frequency (RF). Specifically, phase noise values between −84 and −77 dBc/Hz at 1 kHz offset and a noise floor of −163 dBc/Hz at far-from-carrier offset were achieved. Additionally, the 3D-printed ABS-based oscillator delivers notably higher output power (4.575 dBm at 260 MHz and 0.147 dBm at 437 MHz). To facilitate modular characterization, advanced packaging techniques leveraging precise 3D-printed encapsulation with sub-100 μm lateral interconnects were employed. These ensured robust packaging integrity without compromising oscillator performance. Furthermore, a comparison between two transistor technologies—a silicon germanium (SiGe) heterojunction bipolar transistor (HBT) and an enhancement-mode pseudomorphic high-electron-mobility transistor (E-pHEMT)—demonstrated that SiGe HBT transistors provide superior phase noise characteristics at close-to-carrier offset frequencies, with a significant 11 dB improvement observed at 1 kHz offset. These results highlight the promising potential of 3D-printed chip-carrier packaging techniques in high-performance MEMS oscillator applications. Full article

This study provides new insight into the mechanisms governing solid state dewetting (SSD) in SiGe alloys and underscores the potential of this bottom-up technique for fabricating self-organized defect-free nanostructures for CMOS-compatible photonic and nanoimprint applications. In particular, we investigate the SSD of Si_1−xGe_x thin films grown by molecular beam epitaxy on silicon-on-insulator (SOI) substrates, focusing on and clarifying the interplay of dewetting dynamics, strain elastic relaxation, and SiGe/SOI interdiffusion. Samples were annealed at 820 °C, and their morphological and compositional evolution was tracked using atomic force microscopy (AFM), scanning electron microscopy (SEM), energy-dispersive X-ray spectroscopy (EDX), X-ray diffraction (XRD), and Raman spectroscopy, considering different annealing time steps. A sequential process typical of the SiGe alloy has been identified, involving void nucleation, short finger formation, and ruptures of the fingers to form nanoislands. XRD and Raman data reveal strain relaxation and significant Si-Ge interdiffusion over time, with the Ge content decreasing from 29% to 20% due to mixing with the underlying SOI layer. EDX mapping confirms a Ge concentration gradient within the islands, with higher Ge content near the top. Full article

In recent years, research on light-matter interactions in silicon-based micro/nano cavity optomechanical systems demonstrates high-resolution sensing capabilities (e.g., sub-fm-level displacement sensitivity). Conventional 2D photonic crystal (PhC) cavity optomechanical sensors face inherent limitations: thin silicon layers (200–300 nm) restrict both the mass block (critical for thermal noise suppression) and optical Q-factor. Enlarging the detection mass in such thin layers exacerbates in-plane height nonuniformity, severely limiting high-precision sensing. This study proposes a 500 nm thick silicon-based 2D slot-type PhC cavity design for advanced sensing applications, fabricated on a silicon-on-insulator (SOI) substrate with optimized air slot structures. Systematic parameter optimization via finite element simulations defines structural parameters for the 1550 nm band, followed by 6 × 6 × 6 combinatorial experiments on lattice constant, air hole radius, and line-defect waveguide width. Experimental results demonstrate a loaded Q-factor of 57,000 at 510 nm lattice constant, 175 nm air hole radius, and 883 nm line-defect waveguide width (measured sidewall angle: 88.4°). The thickened silicon layer delivers dual advantages: enhanced mass block for thermal noise reduction and high Q-factor for optomechanical coupling efficiency, alongside improved ridge waveguide compatibility. This work advances the practical development of CMOS-compatible micro-opto-electromechanical systems (MOEMS). Full article

The importance and challenges of ethylene detection based on combustion-type low-cost commercial sensors for agricultural and industrial applications are well-established. This work summarizes the significant progress in ethylene detection based on an innovative Gas Metal Oxide Semiconductor (GMOS) sensor and a new catalytic composition of metallic nanoparticles. The paper presents a study on ethylene and ethanol sensing using a miniature catalytic sensor fabricated by Complementary Metal Oxide Semiconductor–Silicon-on-Insulator–Micro-Electro-Mechanical System (CMOS-SOI-MEMS) technology. The GMOS performance with bimetallic palladium–platinum (Pd-Pt) and monometallic palladium (Pd) and platinum (Pt) catalysts is compared. The synergetic effect of the Pd-Pt catalyst is observed, which is expressed in the shift of combustion reaction ignition to lower catalyst temperatures as well as increased sensitivity compared to monometallic components. The optimal catalysts and their temperature regimes for low and high ethylene concentrations are chosen, resulting in lower power consumption by the sensor. Full article