Search Results (15)

This paper proposes an enhanced cooling method for multi-chip power modules (e.g., in MMC inverters) with uneven power loss in all-electric propulsion ships based on sintered heat pipe parameter optimization and special-shaped design. First, five key parameters of straight sintered heat pipes were optimized: placement directly under hotspot chips, 10 mm in diameter, quantity matching the number of hotspot chips, length equal to the heatsink side length, and direction perpendicular to heatsink fins. Then, a C-shaped heat pipe was designed using the parallel thermal resistance principle, which forms two parallel low-thermal-resistance paths and outperforms conventional U-shaped ones. Finite element simulations showed that the hotspot temperature of the conventional heatsink was 91.26 °C, while it dropped to 87.35 °C with optimized straight heat pipes and further to 80.85 °C with C-shaped ones. Experiments verified an 11.65% temperature reduction (from 86.7 °C of conventional heatsinks to 76.6 °C of C-shaped heat pipe heatsinks). This method effectively lowers hotspot temperatures, reduces device failure rates, improves the thermal reliability of power modules, and provides a generalized design methodology for heatsinks of various power electronic converters. Full article

The transient overvoltage caused by coupling of loop inductance during rapid turn off of a silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) can easily induce avalanche breakdown. Meanwhile, the instantaneous high-density heat flux generated by energy dissipation can create significant electrothermal coupling stress, potentially leading to device failure under severe conditions. To address the issue that the multi-chip parallel structure of power modules cannot linearly enhance avalanche withstand capability, an innovative device screening method based on parameter matching is proposed in this paper. The effectiveness of the proposed solution is verified through experiments, with the total current limit of dual-tube parallel devices and three-tube parallel devices achieving 1.9 times and 2.4 times that of single-tube devices, respectively. This research is of great significance for improving safe and reliable operation of the system. Full article

This paper presents a 2-stage GaN Doherty power amplifier module (DPAM) on a compact $7\times 7$ quad flat no-lead (QFN) package, designed for the needs of 5G massive MIMO base transceiver systems. The interstage and input matching networks employ high-quality factor integrated passive devices (IPDs) to achieve a small form factor. This multi-chip module consists of three GaN-HEMT bare dies used for the driver stage, carrier amplifier, and peaking amplifier. Additionally, two IPD dies are included for the interstage and input matching networks. The external load network is developed using a printed circuit board (PCB). Utilizing a 5G NR signal of 100 MHz bandwidth and a 9.3 dB PAPR within the 3.4–3.8 GHz band, the developed DPAM demonstrated a power gain exceeding 26.8 dB and a power-added efficiency (PAE) greater than 37.8% at a 39 dBm average output power. Full article

An energy- and area-efficient non-return-to-zero (NRZ) transmitter with feedforward equalization (FFE) is proposed for an extra-short-reach (XSR) data interface in chiplet-based system in packages (SiPs) and multi-chip modules (MCMs). At the system level, the final-stage 2:1 multiplexer (MUX) in the transmitter is combined with the driver to reduce the hardware and power consumption; at the circuit level, charge-steering-based moderate-swing signal processing further reduces the circuit power consumption and inter-symbol interference. Fabricated in a 28 nm CMOS process with a core area of 0.032 mm², the prototype NRZ transmitter demonstrates an energy efficiency of 0.42 pJ/b at a data rate of 50 Gb/s with an insertion loss of 10 dB, which makes it a promising candidate for XSR die-to-die (D2D) interfaces. Full article

This paper presents the design and characterisation of a novel double-sided cooling, wire-bondless half-bridge power module incorporating silver sintering technology and silicon carbide MOSFETs. Initially, the module was meticulously designed, optimised, and simulated using Ansys (Electronics Desktop 2021 R1) Q3D and Icepak to assess its stray parameters and thermal performance, respectively. The module has a low simulated stray inductance of 4.7 nH, which would be even lower in a multi-chip version of the design. Additionally, the thermal performance of the double-sided power module is compared with the single-sided version, showing a 30 °C reduction in junction temperature. Following the design work, a double-sided cooled half-bridge module was successfully fabricated, which underwent double pulse analysis and single-phase inductive load testing. Die attachment within the module employs nanosilver paste, with the flexibility to adjust the length of the copper connector to meet diverse requirements. The design exhibits remarkable compactness, and comprehensive electrical testing affirms its suitability for practical applications. Full article

Multi-chip parallel power modules are highly favored in applications requiring high capacity and high switching frequency. However, the dynamic current imbalance between parallel chips caused by asymmetric layouts limits the available capacity. This paper presents a method to optimize dynamic current distribution by adjusting the lengths and connection points of bond wires. For the first time, a response surface model and nonlinear constraint optimization algorithm are introduced, along with parameter analysis based on finite element methods, to establish the response surface models for the parasitic inductance of bond wires and DBC (direct bonded copper). By leveraging the optimization goals for parasitic inductance and the analytical expressions of all response surfaces, the dynamic current sharing issue was transformed into a nonlinear constrained optimization problem. The solution to this optimization problem identified the optimal connection points for the bond wires, enhancing dynamic current sharing performance. Simulations and experiments were conducted, revealing that the optimized automotive-grade module exhibited a significant reduction in current differences between parallel branches, from 41.7% to 5.03% compared with the original design. This indicated that the proposed optimization scheme for adjusting bond wire connection points could significantly mitigate current disparities, thereby markedly improving current distribution uniformity. Full article

In recent years, with the burgeoning application of high voltage in various industrial sectors, the deployment of unmanned equipment, such as industrial heavy-load Unmanned Aerial Vehicles (UAVs), incorporating high-capacity Insulated-Gate Bipolar Transistors (IGBTs), has become increasingly prevalent. The demand for high-voltage IGBT modules in UAV is continuously growing; therefore, exploring methods to predict fault precursor parameters of multi-chip IGBT modules is crucial for the operational health management of unmanned equipment like UAVs. This paper analyzes the gate charge degradation in multi-chip IGBT modules after thermal cycling, which can be used to evaluate the operational state of these modules. Furthermore, to delve into the electrical response of a gate drive circuit caused by local damage within the IGBT module, an RLC model incorporating parasitic parameters of the gate drive circuit is established, and a sensitivity analysis of the peak current in the gate charge circuit is provided. Additionally, in the experimental circuit, an open sample of an IGBT module with partial bond wires lifted off is used to simulate actual faults. The analysis and experimental results indicate that the peak current of the gate charge is closely related to L and C. The significant deviation in the gate current, influenced by the partial bond wires lift-off, can provide a basis for the development of predictive methods for IGBT modules. Full article

This paper presents an in-depth analysis of the oscillation phenomenon occurring in multi-chip parallel automotive-grade power modules under short-circuit conditions and investigates three suppression methods. We tested and analyzed two commercial automotive-grade power modules, one containing two chips and the other containing a single chip, and found that short-circuit gate oscillations were more likely to occur in multi-chip parallel packaged modules than in single-chip packaged modules. Through experimental and simulation analyses, we observed that gate oscillations were mainly caused by the interaction between internal parasitic parameters of the module and the external drive circuit, and we found that high drive resistance and low common emitter inductance between parallel chips could effectively suppress gate voltage oscillations. We also analyzed the two mainstream suppression schemes, increasing the drive gate resistance and placing the drive capacitors in parallel. Unfortunately, we found that these suppression schemes were not ideal solutions because both schemes changed the switching characteristics of the power module. As an alternative, we propose a simple and effective solution that involves adding parallel connections between the parallel chips. Simulation calculations showed that this optimized method reduced the emitter inductance between parallel chips in the upper bridge arm by about 30% and in the lower bridge arm by 35%. Through short-circuit experiments conducted at different DC bus voltages, it has been verified that the new optimized solution effectively resolves gate oscillation issues without affecting the switching characteristics of the power module. Full article

The insulated-gate bipolar transistor (IGBT) represents a crucial component within the domain of power semiconductor devices, which finds ubiquitous employment across a range of critical domains, including new energy vehicles, smart grid systems, rail transit, aerospace, etc. The main characteristics of its operating environment are high voltage, large current, and high power density, which can easily cause issues, such as thermal stress, thermal fatigue, and mechanical stress. Therefore, the reliability of IGBT module packaging has become a critical research topic. This study focuses on the damage of power device solder layers and applies heat transfer theory. Three typical solders for welding IGBTs (92.5Pb5Sn2.5Ag, Sn3.0Ag0.5Cu (SAC305), and nano-silver solder paste) are analyzed using JMatPro software to simulate their characteristics. First, a finite element analysis method is used to simulate the entire IGBT module with ANSYS Workbench platform. The study compares the impact of three types of solders on the overall heat transfer of the IGBT module under normal operation and welding layer damage conditions. The characteristics are analyzed based on changes in the junction temperature, heat flow path, and the law of thermal stress and deformation. The findings indicated that under steady-state working conditions, adjacent chips in a multi-chip IGBT module had significant thermal coupling, with a maximum temperature difference between chip junctions reaching up to 13 °C, and a phenomenon of heat concentration emerged. The three types of solders could change the thermal conductivity and heat transfer direction of the IGBT module to varying degrees, resulting in a temperature change of 3–6 °C. Under conditions of solder layer damage, the junction temperature increased linearly with the severity of the damage. In the 92.5Pb5Sn2.5Ag and Sn3.0Ag0.5Cu (SAC305) solders, the presence of intermetallic compounds (IMCs) led to more stress concentration points in the solder layer, with the maximum stress reaching 7.14661 × 10⁷ MPa and concentrated at the edge of the solder layer. The nano-silver solder layer had the best thermal conductivity, and the maximum thermal deformation under the same conditions was only 1.9092 × 10⁻⁵ m. Full article

A highly integrated multi-mode multi-band (MMMB) power amplifier module (PAM) using hybrid bulk complementary metal oxide semiconductor (CMOS), gallium arsenide (GaAs) heterojunction bipolar transistor (HBT), and silicon-on-insulator (SOI) technologies for low band (LB, 824–915 MHz) and high band (HB, 1710–1980 MHz) is proposed. The hybrid MMMB PAM integrates a bulk CMOS controller die, a GaAs HBT power amplifier (PA) die and a SOI switch die on a six-layer laminate. To simultaneously obtain both highly efficient and highly linear characteristics over a wide range of input power levels, a parallel dual-chain PA strategy has been adopted to provide vary bias current and gain for low-power mode (LPM) and high-power mode (HPM) operation. Additionally, a broadband two-section low-pass output matching network design based on the suppression of high-order harmonics is proposed for enhanced efficiency and linearity. In order to achieve further miniaturization, a three-dimensional (3D) die stack multi-chip module (MCM) packaging structure, where the presented CMOS controller die is stacked vertically on the GaAs HBT PA die, is implemented. The measurement results show that the fabricated MMMB PAM achieves 26.1–27 dB of power gains and 38–38.4% of PAEs at an output power (Pout) of 28 dBm in the HPM, and 20.4–20.9 dB of power gains and 12.4–13.8% of PAEs at Pout of 17 dBm in the LPM over LB. For HB, power gains of 24.3–26.7 dB while maintaining PAEs of 38.2–39.9% at Pout of 28 dBm, and power gains of 15.9–17.5 dB while maintaining PAEs of 12.3–12.8% at Pout of 17 dBm are realized in the HPM and LPM, respectively. The fabricated PAM covering five frequency bands and operating at two power modes only occupies a 5 × 3.5 mm² area. To the best of the authors’ knowledge, this work is the first demonstration of a MMMB PAM adopting an ultra-compact 3D vertical stack MCM package with favorable RF performance. Full article

This paper demonstrates the feasibility of the printed copper (Cu) paste interconnects for applications in power semiconductor modules and switching converters. Copper sinter paste interconnects denoted as “Sinterconnects” have been recently introduced as an alternative to wire-bonding technology for power electronic device packaging. However, the electrical domain properties of these novel interconnects have not yet been investigated in detail. To address this research opportunity, this paper evaluates the performance of two different types of Sinterconnects applied to multi-chip, insulated gate bipolar transistor (IGBT) power modules. First, parasitic or stray inductances of these Sinterconnected systems are calculated analytically and by using three-dimensional finite element (FE) analysis. In addition to that, resistivity ($\rho$) of those has been analysed and compared with conventional wire bond technology. Finally, the performances of the Sinterconnects in power device assemblies are experimentally investigated. Two Sinterconnect structures (i.e., printed Cu paste and Cu clip attach) as well as a state-of-the-art wire-bonded IGBT module, have been integrated into a switching DC-DC converter and benchmarked. Experimental measurements show how converters with Sinterconnects enable efficient power conversion. Full article

This study presents a novel four-channel tile-type T/R module which achieves excellent performances in ultra-wideband (2–12 GHz) and integrates all circuits in a super-light (25 g) and compact (27.8 × 27.8 × 12 mm³) mechanical structure in active phased array systems. The key advancement of this T/R module was to choose a Ball Grid Array (BGA) as the vertical interconnection and bracing between High-Temperature Co-fired Ceramic (HTCC) substrates in order to achieve a high-integration 3-D structure. Exploiting the HTCC multilayer layout, this paper presents the design and development of an ultra-wideband, compact and light, high-output power, four-channel, dual-polarization Transmit/Receive (T/R) Module. In this module, microwave circuits and power control circuits are highly integrated into electrically isolated HTCC layers or substrates, resulting in low coupling and crosstalk between signals. Furthermore, multichip assembly technology, multifunctional MMICs, and other high-integration technologies were adopted for this module. Each channel could provide more than 2 W transmit output power, more than 15 dB receive gain, and less than 5 dB receive noise figure. Every module contains four channels. The power supply and phase/amplitude conditioning of each channel can be controlled individually and showed good consistency of the amplitude and phase of all channels. The connectors of manifold port and polarization ports are all SSMP, which can achieve further integration. This module has also an automatic negative power protection function. The module has stabilized performance and mass production prospects. Full article

In this paper, an approach to determine the thermal impedance of a multi-chip silicon carbide (SiC) power module is proposed, by fusing optical measurement and multi-physics simulations. The tested power module consists of four parallel SiC metal-oxide semiconductor field-effect transistors (MOSFETs) and four parallel SiC Schottky barrier diodes. This study mainly relies on junction temperature measurements performed using fiber optic temperature sensors instead of temperature-sensitive electrical parameters (TESPs). However, the fiber optics provide a relatively slow response compared to other available TSEP measurement methods and cannot detect fast responses. Therefore, the region corresponding to undetected signals is estimated via multi-physics simulations of the power module. This method provides a compensated cooling curve. We analyze the thermal resistance using network identification by deconvolution (NID). The estimated thermal resistance is compared to that obtained via a conventional method, and the difference is 3.8%. The proposed fusion method is accurate and reliable and does not require additional circuits or calibrations. Full article

The Insulated Gate Bipolar Transistor (IGBT) is the component with the highest failure rate in power converters, and its reliability is a critical issue in power electronics. IGBT module failure is largely caused by solder layer fatigue or bond wires fall-off. This paper proposes a multi-chip IGBT module failure monitoring method based on the module transconductance, which can accurately monitor IGBT module chip failures and bond wire failures. The paper first introduces the failure mechanism and module structure of the multi-chip IGBT module; then, it proposes a reliability model based on the module transconductance and analyzes the relationship between chip failure, bond wire failure, and the transmission characteristic curve of the IGBT module. Finally, the module transconductance under chip failure and bond wire failure is measured and calculated through simulation, and the temperature is calibrated, which can eliminate the influence of temperature on health monitoring. The results show that the method has a high sensitivity to chip failures and bond wire failures, can realize the failure monitoring of multi-chip IGBT modules, and is of great significance for improving the reliability of power converters. Full article

With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs) will decrease due to higher probability of manufacturing defects especially, in dies with large area. Therefore, disintegration of large SoCs into smaller chips called chiplets will improve yield and cost of complex platform-based systems. This will also provide functional flexibility, modular scalability as well as the capability to integrate heterogeneous architectures and technologies in a single unit. However, with scaling of the number of chiplets in such a system, the shared resources in the system such as the interconnection fabric and memory modules will become performance bottlenecks. Additionally, the integration of heterogeneous chiplets operating at different frequencies and voltages can be challenging. State-of-the-art inter-chip communication requires power-hungry high-speed I/O circuits and data transfer over long wired traces on substrates. This increases energy consumption and latency while decreasing data bandwidth for chip-to-chip communication. In this paper, we explore the advances and the challenges of interconnecting a multi-chip system with millimeter-wave (mm-wave) wireless interconnects from a variety of perspectives spanning multiple aspects of the wireless interconnection design. Our discussion on the recent advances include aspects such as interconnection topology, physical layer, Medium Access Control (MAC) and routing protocols. We also present some potential paradigm-shifting applications as well as complementary technologies of wireless inter-chip communications. Full article