The Mechanism of Short-Circuit Oscillations in Automotive-Grade Multi-Chip Parallel Power Modules and an Effective Mitigation Approach

This paper presents an in-depth analysis of the oscillation phenomenon occurring in multi-chip parallel automotive-grade power modules under short-circuit conditions and investigates three suppression methods. We tested and analyzed two commercial automotive-grade power modules, one containing two chips and the other containing a single chip, and found that short-circuit gate oscillations were more likely to occur in multi-chip parallel packaged modules than in single-chip packaged modules. Through experimental and simulation analyses, we observed that gate oscillations were mainly caused by the interaction between internal parasitic parameters of the module and the external drive circuit, and we found that high drive resistance and low common emitter inductance between parallel chips could effectively suppress gate voltage oscillations. We also analyzed the two mainstream suppression schemes, increasing the drive gate resistance and placing the drive capacitors in parallel. Unfortunately, we found that these suppression schemes were not ideal solutions because both schemes changed the switching characteristics of the power module. As an alternative, we propose a simple and effective solution that involves adding parallel connections between the parallel chips. Simulation calculations showed that this optimized method reduced the emitter inductance between parallel chips in the upper bridge arm by about 30% and in the lower bridge arm by 35%. Through short-circuit experiments conducted at different DC bus voltages, it has been verified that the new optimized solution effectively resolves gate oscillation issues without affecting the switching characteristics of the power module.


Introduction
With the rise of Electric Vehicles (EVs) and Hybrid Electric Vehicles (HEVs), the demand for efficient, high-density power electronic components is increasing.Therefore, research and development in multi-chip parallel automotive-grade power modules has become particularly important.These modules play a key role in enhancing power density and system efficiency and must meet strict automotive safety and performance standards.
During the lifespan of automotive power modules, various extreme operating conditions may arise due to control unit failures, human errors, or other uncontrollable factors.One of the most common scenarios for automotive power modules is a short circuit Sensors 2024, 24, 2858 2 of 12 (SC) [1][2][3].To prevent module or power system damage under SC conditions, insulatedgate bipolar transistors (IGBTs) are designed to withstand high current and voltage conditions for a few microseconds (typically 10 µs), allowing the gate driver to shut down the IGBT before destruction [4].Under certain operating conditions, high-frequency gateemitter voltage oscillations (i.e., tens of megahertz) have been observed in both type 1 (turn-on transient) and type 2 (steady-state) SC conditions, and these oscillations can be a major problem in automotive-grade multi-chip parallel power modules [5].If the oscillation amplitude exceeds the maximum gate voltage provided in the manufacturer's datasheet, it may lead to gate oxide breakdown, permanently damaging the IGBT and severely limiting the SC robustness [6,7].These oscillations can also degrade module lifespans and cause system reliability issues due to false turn-ons, additional losses, and electromagnetic interference.
Among the different IGBT failure mechanisms under SC conditions, high-frequency gate voltage oscillations have been reported with various interpretations.Compared to single-chip modules, SC gate oscillations are more likely to occur in multi-chip parallel modules [8,9].It is well known that IGBT chips are inherently unstable at high collector voltages and high temperatures due to the presence of negative gate capacitance [10][11][12][13], and efforts have been made to improve layout designs to suppress these oscillations [8,14,15].Another possible explanation is that the oscillations are initiated by the IGBT chip and enhanced by the internal stray impedances of the module itself.Researchers have also presented the notion that IGBT high-frequency oscillations occur in different types of SCs (i.e., type 1 and type 2) [16,17].Although their work highlighted the factors that could trigger oscillations, internal module layout, IGBT characteristics, and application conditions, it provided very few details to aid the reader in understanding or suppressing the oscillations.Researchers have also investigated the plasma extraction transit time (PETT) effect as an excitation mechanism for high-frequency oscillations during the turn-off of paralleled IGBT chips [16,17], and some studies have discussed a combination of high-frequency oscillation source mechanisms, such as the dynamic impact ionization transit time (IMPATT) along with the PETT effect, during IGBT turn-off [18,19].Unfortunately, no definitive interpretation of the mechanism leading to gate voltage oscillations that occur during the SC period has been provided to date.
Since gate voltage oscillations are one of the causes of power module failure, it is very important to understand the mechanism of gate oscillations under SC conditions and establish corresponding methods to suppress these oscillations.In this paper, we investigate this issue for automotive-grade multi-chip parallel power modules using two commercial power modules.We tested and analyzed one module that contained two chips and another module with only a single chip, and we observed considerably different behavior in the gate voltage oscillations between the two modules.The multi-chip module, with a parallel chip configuration, exhibited more severe oscillations than the single-chip module with an oscillation frequency that was several tens of megahertz.Therefore, in this study, we focused on the gate voltage oscillations in modules with parallel IGBT chips.To study the mechanism of these oscillations, we conducted a small-signal analysis of the parallel circuit, and the analysis yielded effective methods to suppress gate voltage oscillations.We also analyzed the two mainstream suppression schemes: increasing gate drive resistance and placing the drive capacitors in parallel.As a result of our investigation, we propose a simple and effective solution that involves parallel connections between the chips to mitigate gate voltage oscillations.This work contributes to the understanding of gate voltage oscillations in IGBT devices and provides a novel solution to enhance device performance during SCs.
The remainder of the article is organized as follows: Section 2 describes the setup of the short-circuit testing platform and the gate oscillation phenomena observed during shortcircuit testing.Section 3 analyzes the mechanisms behind short-circuit gate oscillations.Section 4 investigates methods for controlling gate oscillations during short circuits.Finally, Section 5 concludes the paper.

Construction of Short-Circuit Experimental Platform
Two three-phase full-bridge automotive-grade power modules with upper and lower bridge arms were tested, and the structural diagrams of the two modules are shown in Figure 1a.Internally, the modules consisted of three phases, U, W, and V, with the same chip selection and layout for each phase and two bridge arms, upper and lower, per phase.In Module A, each bridge arm consisted of two sets of chips, each rated for 750 V and 300 A, in parallel.In contrast, Module B had only one chip, also rated for 750 V and 300 A, per bridge arm.For simplicity, we focused our study on SC testing of the upper and lower bridge arms of the U phase with the module test temperature set at 25

Construction of Short-Circuit Experimental Platform
Two three-phase full-bridge automotive-grade power modules with upper and lower bridge arms were tested, and the structural diagrams of the two modules are shown in Figure 1a.Internally, the modules consisted of three phases, U, W, and V, with the same chip selection and layout for each phase and two bridge arms, upper and lower, per phase.In Module A, each bridge arm consisted of two sets of chips, each rated for 750 V and 300 A, in parallel.In contrast, Module B had only one chip, also rated for 750 V and 300 A, per bridge arm.For simplicity, we focused our study on SC testing of the upper and lower bridge arms of the U phase with the module test temperature set at 25 °C.A schematic of the test platform, powered by a high-voltage DC source, is shown in Figure 1b, where Udc represents the DC bus voltage, Cdc represents the bus capacitance, and Ls represents the stray inductance of the test system.To ensure low stray inductance in the DC bus during SC testing, the upper half-bridge, MU, of the device was used as the accompanying test bridge arm, and the lower half-bridge, ML, was used as the bridge arm under test, or device under test (DUT).A constant 15 V DC signal was applied to the gate of MU to keep it always on, and an SC pulse, with a pulse duration of tsc, along with a series drive resistance of Rg was applied to the gate of MU During the test, the gate-emitter voltage, Vge, collector-emitter voltage, Vce, and SC current, Icsc, of MU were simultaneously measured along with Udc.The assembled power module SC test platform with a Cdc of 800 µF is shown in Figure 1c.The Ls of the system was 50 nH, and a comprehensive list of equipment used in the test platform is provided in Table 1.A schematic of the test platform, powered by a high-voltage DC source, is shown in Figure 1b, where U dc represents the DC bus voltage, C dc represents the bus capacitance, and L s represents the stray inductance of the test system.To ensure low stray inductance in the DC bus during SC testing, the upper half-bridge, M U , of the device was used as the accompanying test bridge arm, and the lower half-bridge, M L , was used as the bridge arm under test, or device under test (DUT).A constant 15 V DC signal was applied to the gate of M U to keep it always on, and an SC pulse, with a pulse duration of t sc , along with a series drive resistance of R g was applied to the gate of M U During the test, the gate-emitter voltage, V ge , collector-emitter voltage, V ce , and SC current, I csc , of M U were simultaneously measured along with U dc .The assembled power module SC test platform with a C dc of 800 µF is shown in Figure 1c.The L s of the system was 50 nH, and a comprehensive list of equipment used in the test platform is provided in Table 1.

Gate Oscillation Experimental Test Results
Figure 2 shows the typical U-phase waveforms of V ge , V ce , and I csc in the Module A lower bridge arm under SC conditions.The plots in Figure 2a-f show waveforms with a bus voltage (V cc ) ranging from 150 to 400 V in 50-V steps.After the IGBT was turned on, I csc rapidly increased, while Vce dropped in magnitude.As I csc increased, V ce gradually increased and V ge eventually exceeded the gate voltage level.This was caused by the displacement current flowing through the Miller capacitance.Due to the rise in V ge , an extremely high current flowed through the module, and when V ce approached the V cc level, the current became nearly constant (i.e., the device was in the active region).With V cc < 250 V, gate voltage oscillations did not occur, but with V cc ≥ 250 V, gate oscillations were present.This was because the LC oscillation circuit formed by the internal parasitic inductance and capacitance in Module A was more easily excited with high V ce , facilitating gate oscillations.

Gate Oscillation Experimental Test Results
Figure 2 shows the typical U-phase waveforms of Vge, Vce, and Icsc in the Module A lower bridge arm under SC conditions.The plots in Figure 2a-f show waveforms with a bus voltage (Vcc) ranging from 150 to 400 V in 50-V steps.After the IGBT was turned on, Icsc rapidly increased, while Vce dropped in magnitude.As Icsc increased, Vce gradually increased and Vge eventually exceeded the gate voltage level.This was caused by the displacement current flowing through the Miller capacitance.Due to the rise in Vge, an extremely high current flowed through the module, and when Vce approached the Vcc level, the current became nearly constant (i.e., the device was in the active region).With Vcc < 250 V, gate voltage oscillations did not occur, but with Vcc ≥ 250 V, gate oscillations were present.This was because the LC oscillation circuit formed by the internal parasitic inductance and capacitance in Module A was more easily excited with high Vce, facilitating gate oscillations.To investigate the gate oscillation mechanism, we disassembled the module and removed the encapsulation.The gate-emitter voltages of each IGBT chip (Vge1 and Vge2) were measured near their respective gate locations, and the results are shown in Figure 4. We observed that Vge for the two parallel chips exhibited a 180° phase shift in their voltage waveforms during oscillation, indicating that the gate oscillation occurs between the two parallel chips.

Gate Oscillation Mechanism Analysis
The results in the previous section showed that oscillations in Vge for the two-chip parallel module occurred when the IGBT was in the active region.Note that in the active region, the gain of an IGBT (dIc/dVge) is higher than it is in the saturation region.To theoretically investigate the IGBT gate oscillation mechanism, we treated the parallel circuit of the two IGBT chips in the lower bridge arm as a feedback amplifier and used small signal analysis to simulate the circuit gain.To investigate the gate oscillation mechanism, we disassembled the module and removed the encapsulation.The gate-emitter voltages of each IGBT chip (V ge1 and V ge2 ) were measured near their respective gate locations, and the results are shown in Figure 4. We observed that V ge for the two parallel chips exhibited a 180 • phase shift in their voltage waveforms during oscillation, indicating that the gate oscillation occurs between the two parallel chips.To investigate the gate oscillation mechanism, we disassembled the module and removed the encapsulation.The gate-emitter voltages of each IGBT chip (Vge1 and Vge2) were measured near their respective gate locations, and the results are shown in Figure 4. We observed that Vge for the two parallel chips exhibited a 180° phase shift in their voltage waveforms during oscillation, indicating that the gate oscillation occurs between the two parallel chips.

Gate Oscillation Mechanism Analysis
The results in the previous section showed that oscillations in Vge for the two-chip parallel module occurred when the IGBT was in the active region.Note that in the active region, the gain of an IGBT (dIc/dVge) is higher than it is in the saturation region.To theoretically investigate the IGBT gate oscillation mechanism, we treated the parallel circuit of the two IGBT chips in the lower bridge arm as a feedback amplifier and used small signal analysis to simulate the circuit gain.

Gate Oscillation Mechanism Analysis
The results in the previous section showed that oscillations in V ge for the two-chip parallel module occurred when the IGBT was in the active region.Note that in the active region, the gain of an IGBT (dI c /dV ge ) is higher than it is in the saturation region.To theoretically investigate the IGBT gate oscillation mechanism, we treated the parallel circuit of the two IGBT chips in the lower bridge arm as a feedback amplifier and used small signal analysis to simulate the circuit gain.
During the device switching process, the collector inductance and the emitter inductance together formed the power loop inductance, while the drive loop inductance was composed of the emitter inductance and the gate inductance.Depending on the switching stage, the effects of parasitic inductances on gate oscillations in the drive loop and power loop could be studied separately.Since the tested power module was a balanced threephase device, only the upper and lower bridge arms of the U phase were considered, and their equivalent circuit model was established in LT-spice.Figure 5 shows the equivalent circuit of Module A under SC conditions.In Figure 5, Q 1 , Q 2 , Q 3 , and Q 4 represent the parallel IGBT chips in the upper and lower bridge arms of module A, and D 1 , D 2 , D 3 , and D 4 represent the parallel fast recovery diode (FRD) chips in the upper and lower bridge arms of module A. Figure 5 also shows the parasitic inductance, L cx , and resistance, R cx , of the collector loop, the parasitic inductance, L gx , and resistance, R gx , of the gate loop, and the parasitic inductance, L ex , and resistance, R ex , of the emitter loop.Note that the x in the subscript for each inductance and resistance parameter corresponds to the respective IGBT chip number, and R g with no additional subscript represents the gate drive resistance.Also, recall that L s represents the stray inductance of the test system.To analyze the small-signal circuit gain, an AC signal, V 1 , was applied to the IGBT chips Q 3 and Q 4 , as shown in Figure 5.We then detected the amplitude and phase of the gate-emitter voltage V ge3 with V 1 applied to Q 3 and Q 4 , and we found that circuit oscillations occurred when Sensors 2024, 24, x FOR PEER REVIEW 6 of 12 During the device switching process, the collector inductance and the emitter inductance together formed the power loop inductance, while the drive loop inductance was composed of the emitter inductance and the gate inductance.Depending on the switching stage, the effects of parasitic inductances on gate oscillations in the drive loop and power loop could be studied separately.Since the tested power module was a balanced threephase device, only the upper and lower bridge arms of the U phase were considered, and their equivalent circuit model was established in LT-spice.Figure 5 shows the equivalent circuit of Module A under SC conditions.In Figure 5, Q1, Q2, Q3, and Q4 represent the parallel IGBT chips in the upper and lower bridge arms of module A, and D1, D2, D3, and D4 represent the parallel fast recovery diode (FRD) chips in the upper and lower bridge arms of module A. Figure 5 also shows the parasitic inductance, Lcx, and resistance, Rcx, of the collector loop, the parasitic inductance, Lgx, and resistance, Rgx, of the gate loop, and the parasitic inductance, Lex, and resistance, Rex, of the emitter loop.Note that the x in the subscript for each inductance and resistance parameter corresponds to the respective IGBT chip number, and Rg with no additional subscript represents the gate drive resistance.Also, recall that Ls represents the stray inductance of the test system.To analyze the small-signal circuit gain, an AC signal, V1, was applied to the IGBT chips Q3 and Q4, as shown in Figure 5.We then detected the amplitude and phase of the gate-emitter voltage Vge3 with V1 applied to Q3 and Q4, and we found that circuit oscillations occurred when (1)  We simulated the equivalent circuit of Figure 5 in LT-spice and monitored the amplitude and phase of V ge3 with V 1 applied to Q 3 and Q 4 and different values of L ex and R g .The simulated L ex values were set to 5, 15, and 25 nH, and the resulting amplitude and phase of V ge3 with V 1 swept from 1 MHz to 1 GHz are plotted in Figure 6.
In the low-frequency area (V 1 < 3 MHz), the phase of V ge3 was roughly 200 • , but in the high-frequency area (V 1 > 300 MHz), the phase of V ge3 was roughly 90 • .We observed a rapid phase change near 80 MHz, and with an L ex of 15 or 25 nH, the phase reached 0 • .At this point, the amplitude of V ge3 was greater than 0 dBV, and the oscillation conditions outlined in (1) were met, allowing oscillation to occur.In the low-frequency area (V1 < 3 MHz), the phase of Vge3 was roughly 200°, but in th high-frequency area (V1 > 300 MHz), the phase of Vge3 was roughly 90°.We observed a rapid phase change near 80 MHz, and with an Lex of 15 or 25 nH, the phase reached 0°.A this point, the amplitude of Vge3 was greater than 0 dBV, and the oscillation condition outlined in (1) were met, allowing oscillation to occur.
Since the Rg and Lex of each IGBT chip are relatively easy to change compared to th other parameters, we studied the relationship between oscillation conditions and the val ues of Rg and Lex. Figure 7 shows the simulated stable and oscillation regions for gate volt age with different values for Rg and Lex.From the analysis, we concluded that high re sistance between the gates of two paralleled chips and low inductance between the emit ters could effectively suppress gate voltage oscillation.Additionally, Figure 7 can be used to choose appropriate values of Rg and Lex to avoid IGBT gate oscillations.Since the R g and L ex of each IGBT chip are relatively easy to change compared to the other parameters, we studied the relationship between oscillation conditions and the values of R g and L ex .Figure 7 shows the simulated stable and oscillation regions for gate voltage with different values for R g and L ex .From the analysis, we concluded that high resistance between the gates of two paralleled chips and low inductance between the emitters could effectively suppress gate voltage oscillation.Additionally, Figure 7 can be used to choose appropriate values of R g and L ex to avoid IGBT gate oscillations.In the low-frequency area (V1 < 3 MHz), the phase of Vge3 was roughly 200°, but in the high-frequency area (V1 > 300 MHz), the phase of Vge3 was roughly 90°.We observed a rapid phase change near 80 MHz, and with an Lex of 15 or 25 nH, the phase reached 0°.At this point, the amplitude of Vge3 was greater than 0 dBV, and the oscillation conditions outlined in (1) were met, allowing oscillation to occur.
Since the Rg and Lex of each IGBT chip are relatively easy to change compared to the other parameters, we studied the relationship between oscillation conditions and the values of Rg and Lex. Figure 7 shows the simulated stable and oscillation regions for gate voltage with different values for Rg and Lex.From the analysis, we concluded that high resistance between the gates of two paralleled chips and low inductance between the emitters could effectively suppress gate voltage oscillation.Additionally, Figure 7 can be used to choose appropriate values of Rg and Lex to avoid IGBT gate oscillations.To validate our theory and small-signal simulation results, a finite element model of Module A was developed in ANSYS Q3D software to extract the corresponding emitter parasitic parameters.The IGBT chip used in the module was rated for 750 V and 300 A with a typical turn-on time of 100 ns at 25 °C for VCE = 400 V, Ic = 300 A, Rg = 6 Ω, and VGE = ±15 V. Considering the impact of different drive resistances and DC bus voltages on turn-on time under practical working conditions, the simulation frequency range was set To validate our theory and small-signal simulation results, a finite element model of Module A was developed in ANSYS Q3D software to extract the corresponding emitter parasitic parameters.The IGBT chip used in the module was rated for 750 V and 300 A with a typical turn-on time of 100 ns at 25 • C for V CE = 400 V, I c = 300 A, R g = 6 Ω, and V GE = ±15 V. Considering the impact of different drive resistances and DC bus voltages on turn-on time under practical working conditions, the simulation frequency range was set from 1 MHz to 10 MHz.Table 2 shows the extracted parasitic inductance values at 10 MHz, where the extracted L e3 is shown as 11.34 nH.This value, along with all other extracted L ex values, lies in the oscillation region identified in Figure 7, indicating the potential for oscillation.

Short-Circuit Gate Oscillation Suppression Methods
Common methods for SC gate oscillation mitigation include adjusting the gate drive resistance, adjusting the gate capacitance, and optimizing the power module's internal layout to adjust parasitic inductance.In this section, we analyze the effects of these three methods individually.

Impact of Gate Drive Resistance on Gate Oscillations
To study the impact of different gate drive resistances on SC gate oscillations, SC tests were conducted with different values of R g , and the results are shown in Figure 8. Figure 8a shows that with R g = 10 Ω and V CC = 400 V, the gate experienced severe oscillations.In this case, I csc peaked at 5797 A, approximately 9.6 times the rated current.However, Figure 8 also shows that as the gate drive resistance increased, the gate oscillations gradually weakened.When the drive resistance reached 70 Ω, the gate oscillation phenomenon disappeared, but the I csc peak current was 5033 A, approximately 8.38 times the rated current.
Sensors 2024, 24, x FOR PEER REVIEW 8 of 12 from 1 MHz to 10 MHz.Table 2 shows the extracted parasitic inductance values at 10 MHz, where the extracted Le3 is shown as 11.34 nH.This value, along with all other extracted Lex values, lies in the oscillation region identified in Figure 7, indicating the potential for oscillation.

Short-Circuit Gate Oscillation Suppression Methods
Common methods for SC gate oscillation mitigation include adjusting the gate drive resistance, adjusting the gate capacitance, and optimizing the power moduleʹs internal layout to adjust parasitic inductance.In this section, we analyze the effects of these three methods individually.

Impact of Gate Drive Resistance on Gate Oscillations
To study the impact of different gate drive resistances on SC gate oscillations, SC tests were conducted with different values of Rg, and the results are shown in Figure 8. Figure 8a shows that with Rg = 10 Ω and VCC = 400 V, the gate experienced severe oscillations.In this case, Icsc peaked at 5797 A, approximately 9.6 times the rated current.However, Figure 8 also shows that as the gate drive resistance increased, the gate oscillations gradually weakened.When the drive resistance reached 70 Ω, the gate oscillation phenomenon disappeared, but the Icsc peak current was 5033 A, approximately 8.38 times the rated current.We conclude that as the gate drive resistance increased, d i /d t gradually decreased, the turn-on became slower, and the loss increased.We further conclude that since R g significantly affects the switching characteristics of the power module, adjusting the value of R g solely for gate oscillations is not an ideal solution.

Impact of Gate Drive Capacitance on Gate Oscillations
In addition to adjusting the gate drive resistance, another common method to suppress gate oscillations is to increase the gate capacitance C g .To study the impact of different gate capacitance values on gate oscillations, we conducted tests by placing different capacitors in parallel between the gate and emitter.Figure 9a shows that with V cc = 400 V, R g = 10 Ω, and C g = 30 nF, the peak I csc was 5797 A, roughly 9 times the rated current.As C g increased, the oscillation of the gate-emitter voltage gradually weakened, and when C g increased to 400 nF, the gate oscillation disappeared.Unfortunately, we also observed a reduction in V ge with C g = 400 nF.Like the gate resistance, the gate capacitance has a significant impact on the switching characteristics of the power module and is not an optimal solution to mitigate gate voltage oscillations.
Sensors 2024, 24, x FOR PEER REVIEW 9 of 12 We conclude that as the gate drive resistance increased, di/dt gradually decreased, the turn-on became slower, and the loss increased.We further conclude that since Rg significantly affects the switching characteristics of the power module, adjusting the value of Rg solely for gate oscillations is not an ideal solution.

Impact of Gate Drive Capacitance on Gate Oscillations
In addition to adjusting the gate drive resistance, another common method to suppress gate oscillations is to increase the gate capacitance Cg.To study the impact of different gate capacitance values on gate oscillations, we conducted tests by placing different capacitors in parallel between the gate and emitter.Figure 9a shows that with Vcc = 400 V, Rg = 10 Ω, and Cg = 30 nF, the peak Icsc was 5797 A, roughly 9 times the rated current.As Cg increased, the oscillation of the gate-emitter voltage gradually weakened, and when Cg increased to 400 nF, the gate oscillation disappeared.Unfortunately, we also observed a reduction in Vge with Cg = 400 nF.Like the gate resistance, the gate capacitance has a significant impact on the switching characteristics of the power module and is not an optimal solution to mitigate gate voltage oscillations.

Impact of Adding Parallel Lines to the Common Emitter on Gate Oscillation
From the analysis in the previous sections, the parasitic emitter inductance has a significant impact on gate oscillation.Therefore, we used direct parallel bond wires on the surface of the two chip emitters to reduce the stray inductance between the emitters of each chip.The two IGBT chips connected in parallel were placed side by side, but the common emitter lines connected to the power terminals were relatively long.Therefore, we believed that directly bonding parallel wires on the emitters of the two parallel IGBT chips could effectively reduce the inductance between the two emitters.
The initial power module structure is shown in Figure 10a and the optimized structure with parallel bond wires on the common emitter of two parallel chips is shown in Figure 10b.The emitter inductance of the structure with parallel bond wires was extracted

Impact of Adding Parallel Lines to the Common Emitter on Gate Oscillation
From the analysis in the previous sections, the parasitic emitter inductance has a significant impact on gate oscillation.Therefore, we used direct parallel bond wires on the surface of the two chip emitters to reduce the stray inductance between the emitters of each chip.The two IGBT chips connected in parallel were placed side by side, but the common emitter lines connected to the power terminals were relatively long.Therefore, we believed that directly bonding parallel wires on the emitters of the two parallel IGBT chips could effectively reduce the inductance between the two emitters.
The initial power module structure is shown in Figure 10a and the optimized structure with parallel bond wires on the common emitter of two parallel chips is shown in Figure 10b.The emitter inductance of the structure with parallel bond wires was extracted using ANSYS Q3D, and the values are shown in Table 3.With parallel bond wires and a gate resistance of 10 Ω, the extracted parasitic emitter inductance remained in the stable zone to prevent oscillation.To verify our approach, we prepared samples with parallel emitter bond wires and performed SC tests at bus voltages of 250, 300, 350, and 400 V.The oscillatory behavior of the gate-emitter voltage was significantly improved compared to the module without parallel bond wires, as shown in Figure 11.In addition to mitigating gate voltage oscillation, our method preserved the switching performance of the power module, highlighting the practical utility of our approach.
the module without parallel bond wires, as shown in Figure 11.In addition to mitigating gate voltage oscillation, our method preserved the switching performance of the power module, highlighting the practical utility of our approach.

Conclusions
This study focused on the gate voltage oscillation of automotive-grade multi-chip parallel power modules under SC conditions.We performed SC tests on multi-chip parallel automotive power modules and single-chip automotive power modules.We observed gate voltage oscillation in the automotive power modules containing two chips when the IGBTs were in the active region, but we did not find oscillatory behavior in the single-chip modules.For the oscillatory behavior in the multi-chip modules, we also observed a 180 • phase shift in the gate voltage of parallel chips.
Using small-signal analysis, we analyzed the mechanism of gate oscillation in multichip parallel modules, and under SC conditions, we found that the gate voltage oscillation in IGBT modules with two parallel chips was qualitatively described using a feedback oscillator model.Our analysis also indicated that a high resistive impedance between the gates of the two chips could suppress gate voltage oscillation by limiting the electrical energy between the emitters.
We experimentally investigated two common industry methods for suppressing gate oscillation, and we found that the gate drive resistance, R g , and gate capacitance, C g , have a significant impact on the module switching characteristics.Therefore, R g and C g modification is not an ideal oscillation mitigation method.As an alternative, we proposed a simple and efficient solution involving parallel bond wires on the common emitter terminals.By placing the bond wires in parallel, we significantly reduced the parasitic inductance of the emitter and effectively suppressed the gate voltage oscillation.Furthermore, this method did not degrade the switching characteristics of the power module, highlighting the practical utility of this simple approach.

Figure 1 .
Figure 1.Automotive-grade power module and short-circuit test diagram.(a) Structural diagram of the automotive-grade power module and the internal structure of one phase.(b) Schematic diagram of the short-circuit test platform.(c) Photograph of the short-circuit test platform.

Figure 1 .
Figure 1.Automotive-grade power module and short-circuit test diagram.(a) Structural diagram of the automotive-grade power module and the internal structure of one phase.(b) Schematic diagram of the short-circuit test platform.(c) Photograph of the short-circuit test platform.

Figure 3 .
Figure 3. Short-circuit test results for Module B with Vcc = 400 V.

Figure 4 .
Figure 4. Module A gate oscillation waveforms for Vge1 and Vge2 during the short-circuit test.

Figure 3 .
Figure 3. Short-circuit test results for Module B with V cc = 400 V.
Sensors 2024, 24, x FOR PEER REVIEW 5 of 12The SC test results for Module B with Vcc = 400 V are shown in Figure3.Like Module A, Module B exhibited an increase in Vge, but unlike Module A, Vge for Module B did not oscillate.

Figure 3 .
Figure 3. Short-circuit test results for Module B with Vcc = 400 V.

Figure 4 .
Figure 4. Module A gate oscillation waveforms for Vge1 and Vge2 during the short-circuit test.

Figure 4 .
Figure 4. Module A gate oscillation waveforms for V ge1 and V ge2 during the short-circuit test.

Figure 5 .
Figure 5. Equivalent circuit model of a multi-chip automotive-grade power module considering parasitic effects.We simulated the equivalent circuit of Figure 5 in LT-spice and monitored the amplitude and phase of Vge3 with V1 applied to Q3 and Q4 and different values of Lex and Rg.The simulated Lex values were set to 5, 15, and 25 nH, and the resulting amplitude and phase of Vge3 with V1 swept from 1 MHz to 1 GHz are plotted in Figure 6.

Figure 5 .
Figure 5. Equivalent circuit model of a multi-chip automotive-grade power module considering parasitic effects.

Figure 6 .
Figure 6.Amplitude and phase of Vge3 with V1 applied to Q3 and Q4 and different values for Lex.

Figure 7 .
Figure 7. Stable and oscillation regions obtained through small-signal analysis.

Figure 6 .
Figure 6.Amplitude and phase of V ge3 with V 1 applied to Q 3 and Q 4 and different values for L ex .

Sensors 2024 , 12 Figure 6 .
Figure 6.Amplitude and phase of Vge3 with V1 applied to Q3 and Q4 and different values for Lex.

Figure 7 .
Figure 7. Stable and oscillation regions obtained through small-signal analysis.

Figure 7 .
Figure 7. Stable and oscillation regions obtained through small-signal analysis.

Figure 10 .
Figure 10.Structure diagram before and after the bond wire optimization method.(a) Initial structure.(b) Common emitter with parallel bond wires.

Figure 10 .
Figure 10.Structure diagram before and after the bond wire optimization method.(a) Initial structure.(b) Common emitter with parallel bond wires.

Figure 10 .
Figure 10.Structure diagram before and after the bond wire optimization method.(a) Initial stru ture.(b) Common emitter with parallel bond wires.

Figure 11 .
Figure 11.Short-circuit test results after adding parallel bond wires to the common emitter with bus voltages of (a) V cc = 250 V, (b) V cc = 300 V, (c) V cc = 350 V, and (d) V cc = 400 V.

Table 1 .
Short-circuit test platform experimental equipment and model numbers.

Table 1 .
Short-circuit test platform experimental equipment and model numbers.

Table 2 .
Extracted parasitic inductance of the lower bridge arm at 10 MHz.

Table 2 .
Extracted parasitic inductance of the lower bridge arm at 10 MHz.

Table 3 .
Emitter inductance of the initial structure and the optimized structure with parallel bond wires.

Table 3 .
Emitter inductance of the initial structure and the optimized structure with parallel bon wires.

Table 3 .
Emitter inductance of the initial structure and the optimized structure with parallel bond wires.