Search Results (189)

Protecting sensitive electronic interfaces is critical in industrial applications, where exposure to harsh conditions and fault events is common. This paper reviews and compares circuit techniques for the design of bidirectional protection switches, highlighting key features such as analog switching, high-voltage capability, thermal shutdown, galvanic input isolation, and adjustable current limiting. Based on this review, we propose a universal architecture that combines the most suitable building blocks identified in the literature, with a focus on options that would enable monolithic integration in high-voltage silicon-on-insulator (SOI) technology and capable of delivering up to 2 A at a maximum voltage of 200 V. The proposed architecture is intended as a design guide for realizing a universal switch, rather than a fabricated implementation. To demonstrate system-level interactions, behavioral MATLAB/Simulink (R2024b) simulations are presented using generic components, which show expected functional responses but are not tied to process-specific device models. Full article

The photoelectrochemical oxidation method was utilized to directly grow a gate oxide layer and simultaneously create gate-recessed regions for fabricating GaN-based depletion-mode metal-oxide-semiconductor high-electron mobility transistors (D-mode MOSHEMTs). The LiNbO₃ gate ferroelectric layer and stacked gate oxide layers of LiNbO₃/HfO₂/Al₂O₃ were respectively deposited on the created gate-recessed regions using the photoelectrochemical etching method to fabricate the GaN-based enhancement mode MOSHEMTs (E-mode MOSHEMTs). GaN-based complementary integrated circuits were realized by monolithically integrating the D-mode MOSHEMTs and the E-mode MOSHEMTs. The performances of the inverter circuit manufactured using the integrated GaN-based complementary MOSHEMTs were measured and analyzed. Full article

This paper introduces a compact analog configuration that concurrently realizes a mixed-mode biquadratic filter and a dual-mode quadrature oscillator (QO) by employing a single differential differencing gain amplifier (DDGA) and all-grounded passive components. The proposed design supports four fundamental operation modes—voltage-mode (VM), current-mode (CM), trans-impedance-mode (TIM), and trans-admittance-mode (TAM)—utilizing the same circuit topology without structural modifications. In filter operation, it offers low-pass, high-pass, band-pass, band-stop, and all-pass responses with orthogonal and electronic pole frequency and quality factor. In oscillator operation, it delivers simultaneous voltage and current quadrature outputs with independent tuning of oscillator frequency and condition. The grounded-component configuration simplifies layout and enhances its suitability for monolithic integration. Numerical simulations in a 0.18-μm CMOS process with ±0.9 V supply confirm theoretical predictions, demonstrating precise gain-phase characteristics, low total harmonic distortion (<7%), modest sensitivity to 5% component variations, and stable operation from −40 °C to 120 °C. These results, combined with the circuit’s low component count and integration suitability, suggest strong potential for future development in low-power IoT devices, adaptive communication front-ends, and integrated biomedical systems. Full article

The increasing complexity and cost of manufacturing monolithic chips have driven the semiconductor industry toward chiplet-based designs, where smaller, modular chiplets are integrated onto a single interposer. While chiplet architectures offer significant advantages, such as improved yields, design flexibility, and cost efficiency, they introduce new security challenges in the horizontal hardware manufacturing supply chain. These challenges include risks of hardware Trojans, cross-die side-channel and fault injection attacks, probing of chiplet interfaces, and intellectual property theft. To address these concerns, this paper presents ChipletQuake, a novel on-chiplet framework for verifying the physical security and integrity of adjacent chiplets during the post-silicon stage. By sensing the impedance of the power delivery network (PDN) of the system, ChipletQuake detects tamper events in the interposer and neighboring chiplets without requiring any direct signal interface or additional hardware components. Fully compatible with the digital resources of FPGA-based chiplets, this framework demonstrates the ability to identify the insertion of passive and subtle malicious circuits, providing an effective solution to enhance the security of chiplet-based systems. To validate our claims, we showcase how our framework detects hardware Trojans and interposer tampering. Full article

Silicon-based microcavity quantum dot lasers are attractive candidates for on-chip light sources in photonic integrated circuits due to their small size, low power consumption, and compatibility with silicon photonic platforms. However, integrating components like quantum dot lasers and photodetectors on a single chip remains challenging due to material compatibility issues and mode field mismatch problems. In this work, we have demonstrated monolithic integration of an InAs quantum dot microdisk light emitter, waveguide, and photodetector on a silicon platform using a shared epitaxial structure. The photodetector successfully monitored variations in light emitter output power, experimentally proving the feasibility of this integrated scheme. This work represents a key step toward multifunctional integrated photonic systems. Future efforts will focus on enhancing the light emitter output power, improving waveguide efficiency, and scaling up the integration density for advanced applications in optical communication. Full article

A broadband, efficient monolithic microwave integrated circuit power amplifier (MMIC PA) in OMMIC’s 0.1 μm GaN-on-Si technology for 5G millimeter-wave communication is presented. This study concentrates on the output matching design, which has an important influence on the PA’s performance. A compact one-order synthesized transformer network (STN) is adopted to match the 50 Ω load to the extracted large-signal output model of the transistor. A dual-objective strategy is developed for parameter optimization, incorporating the impedance transformation trajectory inside the predefined optimal impedance domain (OID) that satisfies the required specifications, with approximation to selected optimal load impedances. By introducing a custom adjustment factor β into the error function, coupled with an automated iterative tuning process based on S-parameter simulations, desired broadband matching results can be rapidly achieved. The proposed two-stage PA occupies a small chip area of only 1.23 mm² and demonstrates good frequency consistency over the 24–31 GHz band. Continuous-wave characterization shows a flat small-signal gain of 19.7 ± 0.5 dB; both the output power (P_out) and the power-added efficiency (PAE) at the 4 dB compression point remain smooth, ranging from 32.3 to 32.7 dBm and 35.5% to 37.8%, respectively. The peak PAE reaches up to nearly 40% at the center frequency. Full article

XSPICE models for a generic transmission line, a microstrip line, and coupled microstrips are presented. The developed models extend general-purpose circuit simulation tools using RF circuits design features. The models could be used for circuit simulation in frequency, DC, and time domains for any active or passive RF or microwave schematic (including microwave monolithic integrated circuits—MMICs) involving transmission lines. The presented models could be used with any circuit simulation backend supporting XSPICE extensions and could be integrated without patching the core simulator code. The presented XSPICE models for microstrip lines take into account the frequency dependency of characteristic impedance and dispersion. The models were designed using open-source circuit simulation software. This study provides a practical example of the low-noise RF amplifier (LNA) design with Ngspice simulation backend using the proposed models. Full article

This paper presents a 17–38 GHz wideband low-noise amplifier (LNA) designed in a 150-nm GaAs pHEMT process. The proposed amplifier adopts a cascode topology with an interstage inductor between the common-source (CS) and common-gate (CG) stages, and a series inductor at the source node of the CS stage for source degeneration. By incorporating these inductors in the amplification stage, simultaneous noise and input matching is facilitated, while achieving flat gain characteristics over a broad frequency range and ensuring stability. In addition, the amplification stage with inductors achieves input matching using only a shunt component in the DC bias path, without any series matching elements. This approach allows the amplifier to achieve simultaneous noise and input matching (SNIM), ensuring low-noise performance over a wide bandwidth. The simulation results show a flat gain of 20–23 dB and a low noise figure of 1.1–2.1 dB over the 17–38 GHz band. Full article

As CMOS technology continues to downsize to the nanometer range, the exponential growth predicted by Moore’s Law has been significantly decelerated. Doubling chip density in the two-dimensional domain will no longer be feasible without further device downsizing. Meanwhile, emerging new device technologies, which may be incompatible with the mainstream CMOS technology, offer potential performance enhancements for system integration and could be options for a More-than-Moore system. Additionally, the explosive growth of artificial intelligence (AI) demands ever-high computing power and energy-efficient computing platforms. Heterogeneous multi-chip integration, which combines diverse components or a larger number of functional blocks with different process technologies and materials into compact 3D systems, has emerged as a critical pathway to overcome the performance limitations of monolithic integrated circuits (ICs), such as limited process/material options, low yield, and multifunctional design complexity. Furthermore, it sustains Moore’s Law progression for a further smaller footprint and higher integration density, and it has become pivotal for “More-than-Moore” strategies in the next CMOS technology revolution. This approach is also crucial for sustaining computational advancements with low-power dissipation and low-latency interconnects in the coming decades. The key techniques for heterogeneous wafer-to-wafer bonding involve both copper-to-copper (Cu-Cu) and dielectric-to-dielectric bonding. This review provides a comprehensive comparison of recent advancements in Cu-Cu bonding techniques. Major issues, such as plasma treatment to activate bonding surfaces, passivation to suppress oxidation, Cu geometry, and microstructure optimization to enhance interface diffusion and regrowth, and the use of polymers as dielectrics to mitigate contamination and wafer warpage, as well as pitch size scaling, are discussed in detail. Full article

This manuscript provides insight into optimally noise-matched three-stage Low-Noise Amplifiers (LNAs) by proposing a novel chart that illustrates the relationship between the gain of a three-stage LNA and inter-stage mismatch levels. Under certain conditions, the chart also indicates the required feedback inductor values for all transistors. It is demonstrated that, under the specific assumption of optimal noise and signal matching, the LNA gain depends on the levels of two inter-stage mismatches. Contrary to common belief, the results show that the LNA gain increases as the inter-stage mismatch levels rise. This finding is supported through the discussion of two LNA designs, one with lower and one with higher inter-stage mismatch levels, achieving gains of 24 dB and 26 dB, respectively, with a Noise Figure of 1.7 dB at the center design frequency of 28 GHz. Subsequently, one LNA topology is validated in a Monolithic Microwave Integrated Circuit (MMIC) implementation using WIN Foundry’s PIH1-10 GaAs E-mode technology. The MMIC characterization aligns with the simulated behavior, accounting for the unavoidable losses in the matching networks. Full article

Using novel SiO₂ surface passivation and ultraviolet (UV) light anneal, a 12 nm thick SnO p-type FET (pFET) shows hole effective mobilities (µ_eff) of more than 100 cm²/V·s and 31.1 cm²/V·s at hole densities (Q_h) of 1 × 10¹¹ and 5 × 10¹² cm⁻², respectively. To further improve the on-current/off-current (I_ON/I_OFF), an ultra-thin 7 nm thick SnO nanosheet pFET shows a record-breaking I_ON/I_OFF of 6.9 × 10⁶ and remarkable µ_eff values of ~70 cm²/V·s and 20.7 cm²/V·s at Q_h of 1 × 10¹¹ cm⁻² and 5 × 10¹² cm⁻², respectively. This is the first report of an oxide semiconductor transistor achieving a hole effective mobility µ_eff that reaches 20% of that in single-crystal Si pFETs at an ultra-thin body thickness of 7 nm. In sharp contrast, the control SnO nanosheet pFET without surface passivation or UV anneal exhibits a small I_ON/I_OFF of 1.8 × 10⁴ and a µ_eff of only 6.1 cm²/V·s at 5 × 10¹² cm⁻² Q_h. The enhanced SnO pFET performance is attributed to reduced defects and improved quality in the SnO channel, as confirmed by decreased charges related to sub-threshold swing (SS) and threshold voltage (Vth) shift. Such a large improvement is further supported by the increased Sn²⁺ after passivation and UV anneal, as evidenced by X-ray photoelectron spectroscopy (XPS) analysis. The I_ON/I_OFF ratio exceeding six orders of magnitude, remarkably high hole µ_eff, and excellent two-month stability demonstrate that this pFET is a strong candidate for integration with SnON nFETs in next-generation ultra-high-definition displays and monolithic three-dimensional integrated circuits (3D ICs). Full article

This paper presents two cryogenic low-noise amplifiers (LNAs) based on the WIN’s 0.18 $\mathrm{\mu }$m gate length gallium arsenide (GaAs) pseudomorphic high electron mobility transistor (pHEMT) process designed for radio telescope receivers. Discrete transistors with gate peripheries spanning 50–600 $\mathrm{\mu }$m were DC-characterized at 290 K and 15 K, respectively. The LNAs underwent on-chip noise characterization under 15 K using a Y-factor measurement setup, which integrated a calibrated noise source and a noise figure analyzer. This approach directly quantified the noise temperature—critical metrics for radio telescope receiver front-ends. The top-performing LNA variant identified through on-chip characterization was packaged and evaluated in a cryogenic test-bed. This LNA, spanning a bandwidth of 0.3–15 GHz, demonstrated a gain of 26 dB and a minimum noise temperature of 6 K when operated at an ambient temperature of 15 K. In contrast, a second LNA architecture, tested solely on-chip, demonstrated a gain of 30 dB and a minimum noise temperature of 15 K across the 0.3–7 GHz range. Full article

Dual-gate metal-oxide-semiconductor transistors have attracted considerable interest due to their high threshold voltage control capability, higher drain current, and the ability to alleviate the impact of carrier surface scattering at the channel/dielectric interface. However, their applications in the monolithic integration of scaled devices encounter challenges stemming from the interaction between the pre-treated channel layer and its covering dielectric. Here, we demonstrate the successful realization of a scaled back-end-of-line (BEOL) compatible dual-gate indium–gallium–zinc oxide (IGZO) transistor with a channel length (L_ch) scaled down to 150 nm and a channel thickness (T_ch) of 4.2 nm. After precisely adjusting the metal ratio to In_0.24Ga_0.58Zn_0.18O and employing O₃ as an oxygen precursor for the deposition of Al₂O₃ as the top-gate dielectric layer, a high maximum current of 1.384 mA was attained under top-gate control, while a high current of 1.956 mA was achieved under bottom-gate control. Additionally, a high current on/off ratio (I_on/off > 10⁹) was achieved for the dual gate. Careful calculations reveal that the field-effective mobility (μ_eff) reaches 11.68 cm²V⁻¹s⁻¹ under top-gate control and 22.46 cm²V⁻¹s⁻¹ under bottom-gate control. We demonstrate excellent dual-gate low-voltage modulation performance, with a high current switch ratio of 3 × 10⁵ at L_ch = 300 nm and 2 × 10⁴ at L_ch = 150 nm achieved by only 1 V modulation voltage, accompanied by a normalized current variation higher than 10⁶. Overall, our devices show the remarkable electrical performance characteristics, highlighting their potential applications in high-performance electronic circuits. Full article

Millimeter-wave radar is emerging as a key sensor technology not only for autonomous driving but also for various industrial applications, such as vital sign monitoring and structural displacement sensing using millimeter-wave FMCW radar, which must detect extremely small displacements on the sub-micron scale. Accurate displacement measurements fundamentally rely on obtaining precise intermediate frequency (IF) phase data over slow time (i.e., chirp-to-chirp intervals or pulse repetition time) generated by the radar sensor system. In this study, we developed a millimeter-wave FMCW radar sensor for displacement sensing using a 77–81 GHz radar transceiver MMIC (Monolithic Microwave Integrated Circuit) and evaluated its accuracy and precision through a series of experiments. First, we assessed the MMIC’s phase performance under static conditions using a rigid RF waveguide, and second, we measured a vibrating target using an industrial vibration shaker as a reference. The experiments demonstrated a maximum accuracy error of +0.359 degrees (1.907 μm displacement) and a maximum 3-sigma precision of ±0.358 degrees (±1.180 μm displacement), validating the feasibility of using millimeter-wave radar to measure very small displacements. Full article