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Nanomaterials
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Integrated Circuit Research for Nanoscale Field-Effect Transistors
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Integrated Circuit Research for Nanoscale Field-Effect Transistors

A special issue of Nanomaterials (ISSN 2079-4991). This special issue belongs to the section "Nanoelectronics, Nanosensors and Devices".

Deadline for manuscript submissions: closed (14 March 2025) | Viewed by 13415

Special Issue Editor

Prof. Dr. Huiyong Hu

E-Mail Website
Guest Editor
Wide Bandgap Semiconductor Technology Disciplines State Key Laboratory, School of Microelectronics, Xidian University, Xi'an, China
Interests: optoelectronic properties of group IV devices; silicon photonics
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

As the channel size of field-effect transistors (FETs) shrinks to the nanometer scale, there is increasing demand for atomic-layer materials to minimize the effects of short channels under extreme scaling. Since the proposal of graphene, the first monolayer of graphite, many researchers have developed novel nanomaterials such as two-dimensional chalcogenides and single-element two-dimensional materials on FET devices. These FETs fabricated using nanomaterials have become a hot research topic, and researchers are committed to improving their device performance and expanding their circuit applications.

To draw more attention to this research field, this Special Issue will comprehensively introduce the progress in FET device applications. The potential topics include, but are not limited to, nanomaterials in FET devices and the preparation, circuit design, and application of nano-FET devices. We invite authors to contribute original research and review articles covering the latest developments in aspects such as nanomaterial-based devices, sub-reliability, and material stability.

There are many issues related to the design, fabrication, and application of advanced field-effect transistors. It is my pleasure to invite you to share your expertise in this Special Issue. Full papers, communications, and reviews are all welcome.

Prof. Dr. Huiyong Hu
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Nanomaterials is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • FETs
  • nanomaterials
  • nanointegrated circuits
  • nano-semiconductor device
  • channel effect
  • simulation

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Related Special Issue

Published Papers (7 papers)

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Research

Jump to: Review

15 pages, 4751 KiB  
Article
SnO Nanosheet Transistor with Remarkably High Hole Effective Mobility and More than Six Orders of Magnitude On-Current/Off-Current
by Kuan-Chieh Chen, Jiancheng Wu, Pheiroijam Pooja and Albert Chin
Nanomaterials 2025, 15(9), 640; https://doi.org/10.3390/nano15090640 - 23 Apr 2025
Viewed by 194
Abstract
Using novel SiO2 surface passivation and ultraviolet (UV) light anneal, a 12 nm thick SnO p-type FET (pFET) shows hole effective mobilities (µeff) of more than 100 cm2/V·s and 31.1 cm2/V·s at hole densities (Qh [...] Read more.
Using novel SiO2 surface passivation and ultraviolet (UV) light anneal, a 12 nm thick SnO p-type FET (pFET) shows hole effective mobilities (µeff) of more than 100 cm2/V·s and 31.1 cm2/V·s at hole densities (Qh) of 1 × 1011 and 5 × 1012 cm−2, respectively. To further improve the on-current/off-current (ION/IOFF), an ultra-thin 7 nm thick SnO nanosheet pFET shows a record-breaking ION/IOFF of 6.9 × 106 and remarkable µeff values of ~70 cm2/V·s and 20.7 cm2/V·s at Qh of 1 × 1011 cm−2 and 5 × 1012 cm−2, respectively. This is the first report of an oxide semiconductor transistor achieving a hole effective mobility µeff that reaches 20% of that in single-crystal Si pFETs at an ultra-thin body thickness of 7 nm. In sharp contrast, the control SnO nanosheet pFET without surface passivation or UV anneal exhibits a small ION/IOFF of 1.8 × 104 and a µeff of only 6.1 cm2/V·s at 5 × 1012 cm−2 Qh. The enhanced SnO pFET performance is attributed to reduced defects and improved quality in the SnO channel, as confirmed by decreased charges related to sub-threshold swing (SS) and threshold voltage (Vth) shift. Such a large improvement is further supported by the increased Sn2+ after passivation and UV anneal, as evidenced by X-ray photoelectron spectroscopy (XPS) analysis. The ION/IOFF ratio exceeding six orders of magnitude, remarkably high hole µeff, and excellent two-month stability demonstrate that this pFET is a strong candidate for integration with SnON nFETs in next-generation ultra-high-definition displays and monolithic three-dimensional integrated circuits (3D ICs). Full article
(This article belongs to the Special Issue Integrated Circuit Research for Nanoscale Field-Effect Transistors)
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14 pages, 4173 KiB  
Article
FeFET-Based Computing-in-Memory Unit Circuit and Its Application
by Xiaojing Zha and Hao Ye
Nanomaterials 2025, 15(4), 319; https://doi.org/10.3390/nano15040319 - 19 Feb 2025
Viewed by 857
Abstract
With the increasing challenges facing silicon complementary metal oxide semiconductor (CMOS) technology, emerging non-volatile memory (NVM) has received extensive attention in overcoming the bottleneck. NVM and computing-in-memory (CiM) architecture are promising in reducing energy and time consumption in data-intensive computation. The HfO2-doped ferroelectric [...] Read more.
With the increasing challenges facing silicon complementary metal oxide semiconductor (CMOS) technology, emerging non-volatile memory (NVM) has received extensive attention in overcoming the bottleneck. NVM and computing-in-memory (CiM) architecture are promising in reducing energy and time consumption in data-intensive computation. The HfO2-doped ferroelectric field-effect transistor (FeFET) is one of NVM and has been used in CiM digital circuit design. However, in the implementation of logical functions, different input forms, such as FeFET state and gate voltage, limit the logic cascade and restrict the rapid development of CiM digital circuits. To address this problem, this paper proposes a Vin–Vout CiM unit circuit with the built-in state of FeFET as a bridge. The proposed unit circuit unifies the form of logic inputs and describes the basic structure of FeFET to realize logic functions under the application of gate-source voltage. Based on the proposed unit circuit, basic logic gates are designed and used to realize CiM Full Adder (FA). The simulation results verify the feasibility of FeFET as the core of logic operations and prove the scalability of FeFET-based unit circuit, which is expected to develop more efficient CiM circuits. Full article
(This article belongs to the Special Issue Integrated Circuit Research for Nanoscale Field-Effect Transistors)
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10 pages, 7902 KiB  
Article
Enhanced On-State Current and Stability in Heterojunction ITO/ZnO Transistors: A Mechanistic Analysis
by Dengqin Xu, Tingchen Yi, Junchen Dong, Lifeng Liu, Dedong Han and Xing Zhang
Nanomaterials 2025, 15(3), 248; https://doi.org/10.3390/nano15030248 - 6 Feb 2025
Viewed by 602
Abstract
The growing demand for high-performance oxide transistors in advanced integrated circuits (ICs) underscores the need for innovative device structures, with heterojunctions emerging as a promising approach. This study presents high-performance ITO/ZnO transistors, which outperform individual ITO or ZnO transistors by achieving an on-state [...] Read more.
The growing demand for high-performance oxide transistors in advanced integrated circuits (ICs) underscores the need for innovative device structures, with heterojunctions emerging as a promising approach. This study presents high-performance ITO/ZnO transistors, which outperform individual ITO or ZnO transistors by achieving an on-state current of 19.2 μA/μm at a drain voltage of 1 V and exhibiting a minimal threshold voltage shift of −0.16 V under negative bias illumination stress. Band structure analysis reveals that the differences in the conduction band minimum and Fermi level between the ZnO and ITO films lead to the formation of a potential well at the ITO/ZnO interface. Furthermore, the increase in the on-state current is attributed to electron confinement at the ITO/ZnO interface, while the enhanced NBIS stability is ascribed to both the band structure and ZnO passivation. These findings make significant contributions to both optimizing the performance and analyzing the mechanisms of oxide devices, highlighting the potential of high-performance ITO/ZnO transistors in 3D integrated circuits, advanced memory devices, and back-end-of-line (BEOL) processes. Full article
(This article belongs to the Special Issue Integrated Circuit Research for Nanoscale Field-Effect Transistors)
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8 pages, 3216 KiB  
Communication
A Ku-Band Fully Differential Low-Power High-Input P1dB Low-Noise Amplifier
by Sang-Rok Lee, Joon-Hyung Kim, Min-Seok Baek and Choul-Young Kim
Nanomaterials 2024, 14(23), 1913; https://doi.org/10.3390/nano14231913 - 28 Nov 2024
Viewed by 1028
Abstract
This paper introduces a Ku-band fully differential low-power high-input 1 dB compression point (P1dB) low-noise amplifier (LNA). A fully differential structure is employed to enhance the input P1dB, common-mode noise rejection, and second harmonic cancellation. The first stage adopts large transistors and is [...] Read more.
This paper introduces a Ku-band fully differential low-power high-input 1 dB compression point (P1dB) low-noise amplifier (LNA). A fully differential structure is employed to enhance the input P1dB, common-mode noise rejection, and second harmonic cancellation. The first stage adopts large transistors and is optimized for power consumption and noise figure (NF). The output stage is designed with class AB bias, resulting in improved P1dB, power consumption, and linearity. The proposed two-stage fully differential common-source (CS) LNA was implemented using 65 nm bulk complementary metal oxide semiconductor (CMOS) technology. The fabricated LNA achieved a minimum NF of 2.7 dB at 13.6 GHz. Furthermore, it achieved a maximum gain of 19.92 dB at 12.2 GHz. Additionally, the LNA has an input P1dB of −7.45 dBm and an output power 1 dB compression point (OP1dB) of 10.09 dBm, both measured at 15.6 GHz. The LNA operates with a power consumption of 11 mW at a 1 V supply, and occupies a core size of 0.75 mm × 0.35 mm. Full article
(This article belongs to the Special Issue Integrated Circuit Research for Nanoscale Field-Effect Transistors)
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12 pages, 3437 KiB  
Article
Analysis of 3D Channel Current Noise in Small Nanoscale MOSFETs Using Monte Carlo Simulation
by Wenpeng Zhang, Qun Wei, Xiaofei Jia and Liang He
Nanomaterials 2024, 14(16), 1359; https://doi.org/10.3390/nano14161359 - 18 Aug 2024
Viewed by 1515
Abstract
As field effect transistors are reduced to nanometer dimensions, experimental and theoretical research has shown a gradual change in noise generation mechanisms. There are few studies on noise theory for small nanoscale transistors, and Monte Carlo (MC) simulations mainly focus on 2D devices [...] Read more.
As field effect transistors are reduced to nanometer dimensions, experimental and theoretical research has shown a gradual change in noise generation mechanisms. There are few studies on noise theory for small nanoscale transistors, and Monte Carlo (MC) simulations mainly focus on 2D devices with larger nanoscale dimensions. In this study, we employed MC simulation techniques to establish a 3D device simulation process. By setting device parameters and writing simulation programs, we simulated the raw data of channel current noise for a silicon-based metal–oxide–semiconductor field-effect transistor (MOSFET) with a 10 nm channel length and calculated the drain output current based on these data, thereby achieving static testing of the simulated device. Additionally, this study obtained a 3D potential distribution map of the device channel surface area. Based on the original data from the simulation analysis, this study further calculated the power spectral density of the channel current noise and analyzed how the channel current noise varies with gate voltage, source–drain voltage, temperature, and substrate doping density. The results indicate that under low-temperature conditions, the channel current noise of the 10 nm MOSFET is primarily composed of suppressed shot noise, with the proportion of thermal noise in the total noise slightly increasing as temperature rises. Under normal operating conditions, the channel current noise characteristics of the 10 nm MOSFET device are jointly characterized by suppressed shot noise, thermal noise, and cross-correlated noise. Among these noise components, shot noise is the main source of noise, and its suppression degree decreases as the bias voltage is reduced. These findings are consistent with experimental observations and theoretical analyses found in the existing literature. Full article
(This article belongs to the Special Issue Integrated Circuit Research for Nanoscale Field-Effect Transistors)
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Review

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23 pages, 4437 KiB  
Review
Two-Dimensional Semiconductors for State-of-the-Art Complementary Field-Effect Transistors and Integrated Circuits
by Meng Liang, Han Yan, Nasrullah Wazir, Changjian Zhou and Zichao Ma
Nanomaterials 2024, 14(17), 1408; https://doi.org/10.3390/nano14171408 - 28 Aug 2024
Cited by 1 | Viewed by 5275
Abstract
As the trajectory of transistor scaling defined by Moore’s law encounters challenges, the paradigm of ever-evolving integrated circuit technology shifts to explore unconventional materials and architectures to sustain progress. Two-dimensional (2D) semiconductors, characterized by their atomic-scale thickness and exceptional electronic properties, have emerged [...] Read more.
As the trajectory of transistor scaling defined by Moore’s law encounters challenges, the paradigm of ever-evolving integrated circuit technology shifts to explore unconventional materials and architectures to sustain progress. Two-dimensional (2D) semiconductors, characterized by their atomic-scale thickness and exceptional electronic properties, have emerged as a beacon of promise in this quest for the continued advancement of field-effect transistor (FET) technology. The energy-efficient complementary circuit integration necessitates strategic engineering of both n-channel and p-channel 2D FETs to achieve symmetrical high performance. This intricate process mandates the realization of demanding device characteristics, including low contact resistance, precisely controlled doping schemes, high mobility, and seamless incorporation of high- κ dielectrics. Furthermore, the uniform growth of wafer-scale 2D film is imperative to mitigate defect density, minimize device-to-device variation, and establish pristine interfaces within the integrated circuits. This review examines the latest breakthroughs with a focus on the preparation of 2D channel materials and device engineering in advanced FET structures. It also extensively summarizes critical aspects such as the scalability and compatibility of 2D FET devices with existing manufacturing technologies, elucidating the synergistic relationships crucial for realizing efficient and high-performance 2D FETs. These findings extend to potential integrated circuit applications in diverse functionalities. Full article
(This article belongs to the Special Issue Integrated Circuit Research for Nanoscale Field-Effect Transistors)
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22 pages, 4606 KiB  
Review
Recent Advances of VO2 in Sensors and Actuators
by Mahmoud Darwish, Yana Zhabura and László Pohl
Nanomaterials 2024, 14(7), 582; https://doi.org/10.3390/nano14070582 - 27 Mar 2024
Cited by 4 | Viewed by 2965
Abstract
Vanadium dioxide (VO2) stands out for its versatility in numerous applications, thanks to its unique reversible insulator-to-metal phase transition. This transition can be initiated by various stimuli, leading to significant alterations in the material’s characteristics, including its resistivity and optical properties. [...] Read more.
Vanadium dioxide (VO2) stands out for its versatility in numerous applications, thanks to its unique reversible insulator-to-metal phase transition. This transition can be initiated by various stimuli, leading to significant alterations in the material’s characteristics, including its resistivity and optical properties. As the interest in the material is growing year by year, the purpose of this review is to explore the trends and current state of progress on some of the applications proposed for VO2 in the field of sensors and actuators using literature review methods. Some key applications identified are resistive sensors such as strain, temperature, light, gas concentration, and thermal fluid flow sensors for microfluidics and mechanical microactuators. Several critical challenges have been recognized in the field, including the expanded investigation of VO2-based applications across multiple domains, exploring various methods to enhance device performance such as modifying the phase transition temperature, advancing the fabrication techniques for VO2 structures, and developing innovative modelling approaches. Current research in the field shows a variety of different sensors, actuators, and material combinations, leading to different sensor and actuator performance input ranges and output sensitivities. Full article
(This article belongs to the Special Issue Integrated Circuit Research for Nanoscale Field-Effect Transistors)
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