Heterogeneous Integration Technology for More Moore

Dear Colleagues,

Over the past few decades, the CMOS transistor technology has relentlessly progressed towards the realms of 3 nm and 2 nm nodes, adhering to the guiding principles of Moore's Law. However, as Moore’s Law approaches its theoretical limits amidst the burgeoning demands of applications such as AI for memory, 5G, and the Internet of Things (IoT), the pursuit of multi-functionality, high-density integration, reduced form factor, and weight, low power consumption, large bandwidth, and low latency in electronic information systems has become increasingly urgent. To propel the evolution of high-performance computing chips and diverse functional chips, the global landscape has witnessed the emergence of numerous innovative processes, novel devices, and advanced chip technologies in recent years. These include heterogeneous integration technology, Chiplet technology, 3D stacking integration technology, wide-bandgap and ultra-wide-bandgap semiconductor material devices and chips, photonic devices, hybrid optoelectronic devices, 2D material-based devices, flexible optoelectronic/microelectronic devices, quantum computing devices, neuromorphic devices, etc. Through heterogeneous integration technology, the integration of devices and chips made from diverse materials (e.g., compound semiconductor materials, 2D materials, organic materials), various dimensions, different fabrication processes nodes, and multiple functionalities onto silicon-based CMOS integrated circuit chips can take advantage of the unique strengths of each material and device, thereby maximizing the functionality and performance of the heterogeneous integrated chips. The advancement of heterogeneous integration technology would propel the overall integrated system from planar integration towards three-dimensional integration, further enabling the realization of complex and high-performance electronic information integrated systems composed of compound semiconductor devices, RF devices, power devices, MEMS sensors, and more. Also, it will bring about a new revolution in integrated circuits, microelectronics, and optoelectronics.

Follow the success of previous special issues: Abridging the CMOS Technology (https://www.mdpi.com/2079-4991/12/23/4245) and Abridging the CMOS Technology II (https://www.mdpi.com/2079-4991/14/11/897), this Special Issue focuses on the physics and technology of heterogeneous integration of advanced technology and devices with silicon technology. It serves as a forum for multidisciplinary experts to address various aspects of recent advancements in nanomaterials, nanotechnology and other novel processes that could help in the further advancements of CMOS technology. The format of articles includes full papers, communications, and reviews. Topics include, but are not limited to:

• Heterogeneous integration of nanomaterials on a silicon substrate;
• Heterogeneous integration of advanced functional micro/nano modules and devices, such as photonic chips, power devices, radio-frequency devices, 2D chips, quantum computing chips, neuromorphic chips, etc.;
• Novel heterogeneous integration technology and process for micro/nanoelectronic devices, such as heteroepitaxy, smart-cut technology, wafer-level bonding technology, die-to-wafer bonding technology, and Chiplet technology;
• Interconnects technology for heterogeneous 3D integration for micro/nanoelectronic devices: 3D stacking process technology, interconnect techniques, through silicon via (TSV) technique, silicon interpose technology, application of 2D materials for interconnect and thermal budget mitigation;
• Characterization and measurement methods for heterogeneous integrated materials, structures, and devices;
• Modelling and simulation of various aspects of heterogeneous integration technology;
• Thermal management involving heterogeneous integration technology.

Prof. Dr. Hei Wong
Dr. Jun Liu
Dr. JIeqiong Zhang
Guest Editors

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• heterogeneous integration technology
• heterogeneous 3D integration
• silicon substrate
• micro/nanoelectronic devices
• wafer bonding technology