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Article

A 17–38 GHz Cascode Low-Noise Amplifier in 150-nm GaAs Adopting Simultaneous Noise- and Input-Matched Gain Stage with Shunt-Only Input Matching

Department of Semiconductor Engineering, Seoul National University of Science and Technology, 232, Gongneung-ro, Nowon-gu, Seoul 01811, Republic of Korea
*
Author to whom correspondence should be addressed.
These authors contributed equally to this work.
Electronics 2025, 14(14), 2771; https://doi.org/10.3390/electronics14142771
Submission received: 15 June 2025 / Revised: 6 July 2025 / Accepted: 8 July 2025 / Published: 10 July 2025
(This article belongs to the Special Issue Radio Frequency/Microwave Integrated Circuits and Design Automation)

Abstract

This paper presents a 17–38 GHz wideband low-noise amplifier (LNA) designed in a 150-nm GaAs pHEMT process. The proposed amplifier adopts a cascode topology with an interstage inductor between the common-source (CS) and common-gate (CG) stages, and a series inductor at the source node of the CS stage for source degeneration. By incorporating these inductors in the amplification stage, simultaneous noise and input matching is facilitated, while achieving flat gain characteristics over a broad frequency range and ensuring stability. In addition, the amplification stage with inductors achieves input matching using only a shunt component in the DC bias path, without any series matching elements. This approach allows the amplifier to achieve simultaneous noise and input matching (SNIM), ensuring low-noise performance over a wide bandwidth. The simulation results show a flat gain of 20–23 dB and a low noise figure of 1.1–2.1 dB over the 17–38 GHz band.

1. Introduction

Broadband low-noise amplifiers (LNAs) are critical components in the front-end of modern millimeter-wave (mm-wave) communication systems, such as 5G transceivers, automotive radar sensors, and high-speed wireless links [1]. These systems require LNAs that provide wideband gain, low noise figure (NF), and high linearity while maintaining compact size and low power consumption. As systems operate at higher mm-wave frequencies, designing LNAs requires satisfying more demanding performance specifications, making their design an important challenge in front-end circuit development.
Gallium arsenide (GaAs)-based compound semiconductor technologies have emerged as strong alternatives to conventional CMOS for mm-wave LNA design [2]. GaAs pseudomorphic high-electron mobility transistors (pHEMTs) offer superior electron mobility, reduced parasitic resistance, and higher cutoff frequencies ( f t ) and maximum oscillation frequencies f m a x . These characteristics result in enhanced high-frequency gain and a reduced noise figure [2,3].
Despite the advantages offered by GaAs technologies, conventional mm-wave LNA designs still face multiple challenges when targeting broadband, low-noise operation. Recently, various techniques for GaAs LNA have been reported to enhance performance such as gain, bandwidth, and noise figure [4,5,6,7,8,9]. However, these approaches often struggle to resolve the fundamental trade-off involved in simultaneously satisfying the distinct impedance conditions required for maximum power gain and minimum noise figure. To address this fundamental trade-off, a design methodology known as simultaneous noise and input matching (SNIM) is widely employed [10,11,12,13,14,15]. Among the various methods to implement SNIM, the inductive source degeneration technique is a fundamental approach for this purpose [10,11,14,15], but it is inherently constrained in achieving wideband matching because its optimal condition can be achieved only within a narrow frequency range. To overcome this limitation and achieve wider SNIM, techniques such as feedback network [12] and interstage loading [13] have been reported. Nevertheless, these methods for broadening the matching bandwidth typically require a complex input matching network composed of multiple passive elements, which introduces additional insertion loss that degrades the overall noise figure [16,17].
To address the aforementioned challenges, this work proposes a broadband cascode LNA designed with a 150 nm GaAs pHEMT process. The proposed design incorporates an interstage inductor between the CS and CG transistors, along with a source degeneration inductor at the CS stage. These inductors collectively contribute to improved gain flatness, circuit stability, and the realization of simultaneous noise and input matching (SNIM). In particular, input matching is achieved without any series components by utilizing the CS gate bias line as a shunt-only matching circuit. This simplified matching approach eliminates the need for a dedicated input matching network and enables broadband operation with low noise [16]. The proposed amplifier achieves a flat gain, low noise figure, and robust stability over the entire 17–38 GHz band. Consistent performance under process, voltage, and temperature (PVT) variations is also verified through comprehensive Monte Carlo simulations.
The remainder of this paper is organized as follows. Section 2 reviews the limitations of conventional techniques for achieving simultaneous noise and input matching (SNIM). Section 3 presents the analysis and design methodology of the proposed cascode stage that achieves SNIM using a shunt-only input matching network. Section 4 describes the complete schematic and layout of the proposed three-stage LNA, along with comprehensive simulation results. Finally, Section 5 summarizes the key conclusions of this work.

2. Limitations of the Conventional SNIM Techniques

In LNA design, trade-offs among key performance parameters—such as power gain, noise figure (NF), and input matching—remain a significant challenge [13]. To address this issue, the simultaneous noise and input matching (SNIM) technique has been widely adopted [9,13,17], which ensures that the input impedance is matched to the optimum noise impedance for minimum NF while maintaining input matching. To satisfy the SNIM condition, the input impedance of the amplifier ( Z i n ) must be conjugately matched to the optimum noise impedance ( Z o p t ), such that Z i n * = Z o p t [18,19,20].
Figure 1 shows the schematic of the CS and cascode topologies. As illustrated in Figure 1a, the use of an inductor ( L S ) connected to the source terminal of the input transistor generates a real component in Z i n , which assists in matching it to Z o p t [21]. In addition, a series inductor connected to the gate node ( L G ) is used to cancel the residual capacitive input reactance, thereby satisfying the SNIM condition [22].
However, the parasitic resistance of L G can significantly degrade the NF, and in some cases, it becomes the dominant contributor to the overall NF [23,24,25,26]. To reduce DC power consumption, smaller-sized transistors are typically employed, which in turn decreases the gate–source capacitance ( C G S ). A smaller C G S necessitates a larger L S to satisfy the SNIM condition. However, an excessively large L S not only increases the overall chip area but may also be incompatible with the foundry’s design constraints, making implementation impractical. Furthermore, a large L S value can lead to a reduction in power gain [27].
As shown in Figure 1b, the inductor ( L D ) placed between the CS and CG stages has been widely studied in previous works [28,29,30,31]. The L D can resonate with the parasitic capacitances of both the CS and CG transistors, leading to gain peaking at higher frequencies within the target band [28]. In addition, this effect significantly reduces the noise contribution from the CG transistor, which usually has a large impact on the NF of the cascode. As a result, the CS transistor becomes the main noise source, leading to a lower overall noise figure [29,30,31]. However, as previously discussed, the limitations associated with L G and L S still remain.
In addition, the increasing demand for broadband amplifiers highlights one of the most critical drawbacks of SNIM—its limited applicability over wide frequency ranges [4,32,33]. Conventional SNIM designs typically optimize impedance matching at a single frequency, inherently resulting in a narrowband matching network [10]. This narrowband characteristic presents a significant challenge, as both the transistor’s Z o p t and Z i n are highly frequency dependent. Consequently, it becomes particularly difficult to maintain the condition that Z i n * Z o p t across a wide frequency range, resulting in degraded noise and input matching performance. For this reason, conventional SNIM techniques are often unsuitable for wideband low-noise amplifier designs without the introduction of additional complexity.

3. Proposed Simultaneous Noise- and Input-Matched Cascode Stage with Shunt-Only Input Matching Network

3.1. Two-Port Analysis of Cascode Core Cell

As the operating frequency increases, parasitic components of active and passive devices, along with unwanted coupling between adjacent elements, significantly complicate the small-signal equivalent circuit analysis. This complexity makes it difficult to accurately predict the amplifier performance at mm-wave frequencies. To address this issue, this paper proposes an optimized design methodology that models each active and passive component of the cascode core cell as a two-port network and analyzes the interconnection between these two-port networks through matrix-based numerical analysis. The proposed two-port-based design methodology offers improved accuracy in predicting amplifier performance and provides practical design guidelines, surpassing the limitations of conventional small-signal analysis techniques.
Figure 2 shows the schematic of a cascode core cell and its two-port network based modeling and analysis. The cascode core cell is composed of CS and CG transistors, along with the inductors L D and L S . In Figure 2, the active and passive components are connected in a cascade configuration. Therefore, an ABCD parameter-based analysis is adopted, as it is well-suited for characterizing the overall network configured in a cascade configuration.
To calculate the overall ABCD parameters of the cascode core cell, the circuit is analyzed by dividing it into three parts—CG transistor, L D , and CS transistor with L S . The ABCD parameters corresponding to the CG transistor, L D , and the CS transistor with L S are denoted as A B C D CG , A B C D L D , and A B C D C S _ L S , respectively. A B C D CG and A B C D C S _ L S are accurately extracted from simulations under optimum DC bias conditions across the target frequency range and expressed as
A B C D CG = A CG B CG C CG D CG ,
and
A B C D C S _ L S = A C S _ L S B C S _ L S C C S _ L S D C S _ L S .
In addition, A B C D L D can be modeled as [22]
A B C D L D = 1 j ω L D 0 1 .
By multiplying A B C D C S _ L S , A B C D L D , and A B C D CG , the overall ABCD-parameter of the cascode core cell, denoted as A B C D cascode , can be obtained and is expressed as
A B C D cascode = A B C D C S _ L S × A B C D L D × A B C D CG = A cascode B cascode C cascode D cascode ,
where the elements of A B C D cascode are given by
A cascode = A C S _ L S · ( A CG + j ω L D · C CG ) + B C S _ L S · D CG ,
B cascode = A C S _ L S · ( B CG + j ω L D · D CG ) + B C S _ L S · D CG ,
C cascode = C C S _ L S · ( A CG + j ω L D · C CG ) + D C S _ L S · C CG ,
and
D cascode = C C S _ L S · ( B CG + j ω L D · D CG ) + D C S _ L S · D CG ,
respectively.
In (4), all elements of A B C D cascode include the effects of L D and L S , which allows accurate prediction of important performance metrics of the cascode core cell such as power gain, input impedance, and stability depending on the values of L D and L S .

3.2. Effect of L D and L S on Power Gain and Stability of Cascode Core Cell

The selection of L D and L S involves a critical trade-off among gain, noise figure, and stability. While increasing L S improves noise matching by introducing a real part in the input impedance, it simultaneously reduces gain as a result of increased source degeneration. On the other hand, increasing L D enhances high-frequency gain from a peaking effect caused by resonance with parasitic capacitances, but excessive values can introduce phase shifts that degrade stability (K < 1).
Our design process first established the unconditionally stable (K > 1) region for L D and L S , as presented in Figure 3. Within this boundary, combinations were evaluated to find an optimal compromise between a high, flat Gma and the requirements for simultaneous noise and input matching (SNIM), ensuring reliable wideband performance.
To analyze the gain and stability of the previously constructed cascode core cell, A B C D cascode is converted to the S-parameter [22]. Based on the S-parameter, Rollet’s stability factor (K) is expressed as [22]
K = 1   | S 11 | 2   | S 22 | 2 + | Δ | 2 2 | S 12 S 21 | , where Δ = S 11 S 22 S 12 S 21
while maximum available gain ( G m a ) is given by [22]
G m a = | S 21 | | S 12 | K K 2 1 .
Figure 3 shows the calculated results of stability factor and G m a for L S and L D , respectively, in the range of 0 to 0.5 nH at 18, 28, and 38 GHz. The results shown in Figure 3 were obtained through analytical calculation using Equations (4)–(6). In Figure 3a,b, the cascode core cell operates within the unconditionally stable region for all swept values at 18 GHz and 28 GHz, respectively. However, as shown in Figure 3c, the stability factor K falls below 1 at a high-frequency region for certain combinations of L S and L D . To prevent such instability, the design values of L S and L D must be appropriately constrained to ensure that K > 1 is maintained over the entire frequency range, including the high-frequency region. Ensuring operation within the unconditionally stable region is critical to maintaining overall system stability. In Figure 3a–c, unconditional stability is ensured at all target frequencies (18 GHz, 28 GHz, and 38 GHz) within the ranges of 0 < L S < 0.12 nH and 0 < L D < 0.26 nH.
In addition, to enable wideband operation, a relatively flat G m a over the entire frequency band must be maintained within this range. Since it is impractical to evaluate every possible design point within the predetermined range, representative cases that exhibit relatively flat G m a with reasonably high values across the entire frequency band in Figure 3d–f are selected to characterize the overall trend. The selected design sets are ( L D = 0 nH, L S = 0.26 nH), ( L D = 0.05 nH, L S = 0 nH), and ( L D = 0.1 nH, L S = 0.1 nH).
Table 1 shows the design sets selected based on stability and G m a characteristics within the predetermined L D L S range. Set 1 is chosen to maximize the G m a while maintaining flatness over the target frequency band. In contrast, Set 2 is selected from the opposite end of the feasible design space to explore performance variation over as wide a range as possible. Meanwhile, Set 3 corresponds to a representative configuration located near the center of the design space. The final selection of the optimized design point for achieving SNIM, considering input matching in each design set, is discussed in the following section.

3.3. Characteristics of Cascode Core Cell with Shunt-Only Input Matching Network

Among the predefined design sets, the final selection must satisfy the SNIM condition across the target wideband frequency range. Figure 4 illustrates the variations in the noise matching points, each represented by noise circles corresponding to N F N F min = 0.2 dB, along with the gain matching points of the cascode core cell across the 18–38 GHz range for the three design sets. In Figure 4a,b, corresponding to Set 1 and Set 2, respectively, the gain matching points are located outside the 0.2 dB noise circles, indicating that noise and gain matching cannot be achieved simultaneously. In contrast, Figure 4c, which corresponds to Set 3, demonstrates the best condition for achieving wideband SNIM. The design set achieves gain matching across the specified frequency band, with all points remaining inside the corresponding 0.2 dB noise circles.
In addition, if SNIM is achieved using shunt-only input matching without any additional series components, input matching loss can be minimized, which is beneficial for achieving a low noise figure and facilitates wideband operation under the SNIM condition [16]. To achieve SNIM using shunt-only input matching, the gain and noise matching points must be located close to each other and, at the same time, be positioned near the unit conductance circle. When the gain and noise matching points are located on the unit conductance circle, they can be moved toward the 50 Ω matching point using only a shunt reactive component. In Figure 4c, the gain and noise matching points are closely located and remain near the unit conductance circle across the desired frequency range. Therefore, Set 3 is selected as the final design set that achieves wideband SNIM using shunt-only input matching.
Figure 5a shows the schematic of the cascode core cell with a shunt-only input matching network. Based on the analysis in Figure 4c, an inductive shunt-only input matching network is required to shift the gain and noise matching points toward the 50 Ω point. In Figure 5a, this matching network is implemented utilizing the inductor ( L B ) placed on the DC bias path without any additional matching components. In short, L B in Figure 5a serves a dual purpose, providing both DC biasing and input matching. This approach reduces the loss and noise figure associated with the input matching network, thereby enabling wideband SNIM. Although the proposed design is implemented using GaAs technology, it should be noted that the shunt-only input matching approach is not limited to GaAs. This method is fundamentally applicable to other semiconductor technologies such as CMOS and SiGe, as it is based on general passive matching theory rather than GaAs-specific properties.
Figure 5b shows the gain and noise matching points, along with 0.2 dB noise circles, for the designed cascode core cell incorporating the shunt-only input matching network. As illustrated in Figure 5b, wideband SNIM is successfully achieved. It is important to note that while the initial two-port analysis assumed ideal inductors to establish a clear theoretical insight, the final component values were optimized using electromagnetic (EM) simulations. These simulations account for all non-ideal effects, such as finite inductor Q-factor, parasitic capacitances, and coupling between adjacent components. Consequently, the values of L D and L S were slightly adjusted to 0.11 nH each, based on these practical simulation results.
Figure 6 shows the simulated G m a , S 11 , and noise figure of the designed first-stage cascode core cell with a shunt-only input matching network. As shown in Figure 6a, G m a remains relatively flat across the band, varying from 7.7 dB to 9.2 dB, while the input matching is also well maintained through the shunt-only input matching network, with the input return loss ( S 11 ) ranging from 14 dB to 10.5 dB. In Figure 6b, the noise figure shows a low value ranging from 1.0 to 1.6 dB over the target frequency band, closely approaching N F m i n , which verifies that wideband noise matching has been effectively achieved. Therefore, the proposed cascode core cell with the shunt-only matching technique enables successful realization of wideband SNIM.

4. Simulation Results

To validate the proposed design approach, a three-stage LNA is designed with a 150 nm GaAs pHEMT process. Figure 7 shows the complete schematic of the three-stage cascode LNA adopting the proposed cascode core cell with the shunt-only input matching network. An additional inductor ( L P ) is inserted at the output of the cascode core to enhance the gain in the high-frequency range [34,35]. To enhance circuit stability, a resistor ( R B ) is placed in series with the bypass capacitor, which is connected in parallel with the DC bias path [28]. The proposed cascode core cell is identically applied to both the second and third stages.
Figure 8 presents the finalized layout of the three-stage cascode LNA, incorporating the proposed cascode core cell and utilizing a shunt-only network for input matching. The total chip area including the input and output pads is 2.48 mm × 1.36 mm, corresponding to 3.37 mm2. All stages are biased with V G 1 = –0.4 V, V G 2 = 2.5 V, and V D D = 5.5 V, resulting in a total DC power consumption of 323 mW. This relatively high DC power consumption is mainly due to the cascode topology, which generally requires higher bias voltages compared to common-source amplifiers. The total DC power consumption can be reduced by lowering the gate and drain bias voltages or adopting current reuse techniques while maintaining sufficient gain and noise performance.
Figure 9 shows the simulated S-parameters, noise figure, stability factor, and output 1 dB compression point (OP1dB) of the proposed LNA. As shown in Figure 9a, the 3 dB bandwidth spans from 17 GHz to 38 GHz, resulting in an overall bandwidth of 21 GHz. Within the 3 dB bandwidth, the power gain (S21) ranges from 20 dB to 23 dB. Furthermore, S11 remains below –9.3 dB, indicating that superior wideband input matching is achieved.
Figure 9b shows that the noise figure remains between 1.1 and 2.1 dB across the target band, remaining close to NFmin. This confirms that the proposed design achieves effective wideband noise matching. Figure 9c shows the stability of the circuit. Since the K-factor remains greater than 1 and | Δ | = | S 11 S 22 S 12 S 21 | is less than 1 across the entire frequency range, the circuit is unconditionally stable. The simulated OP1dB and power-added efficiency (PAE) at input P1dB are shown in Figure 9d. The maximum values of OP1dB and PAE are 16.4 dBm and 13.5%, respectively.
Figure 10 and Figure 11 present the results of a Monte Carlo simulation with 1000 samples at a center frequency of 30 GHz, illustrating the impact of process, voltage, and temperature (PVT) variations on the S-parameters, noise figure, and Rollet’s stability factor. As demonstrated by the S11 results in Figure 10, the designed circuit exhibits strong robustness in input matching against process variations. Furthermore, as observed in Figure 11a, the variation in noise figure under PVT variations is less than 0.2 dB, indicating stable noise performance. Therefore, the Monte Carlo analysis with 1000 samples confirms the amplifier’s robustness under PVT variations, highlighting its consistent performance and reliability.
Table 2 summarizes the measured or simulated performance of previously reported LNAs implemented using GaAs processes and operating in the Ku, K, and Ka bands. In Table 2, the figure of merit (FoM) is defined as [36,37,38,39]
F o M = | S 21 , m a x |   ×   B a n d w i d t h 3 d B ( G H z ) × O P 1 d B , m a x ( m W ) ( | N F m i n | 1 ) × P D C ( m W ) .
As shown in Table 2, the proposed circuit achieves the highest FoM among previously reported designs, demonstrating its superior overall performance. In particular, the proposed LNA achieves a wide 21 GHz bandwidth (17–38 GHz) with a flat gain of 20–23 dB and a low noise figure of 1.1–2.1 dB, while maintaining unconditional stability across the entire frequency range. Furthermore, the use of the proposed cascode core cell with a shunt-only input matching network eliminates the need for series matching components, resulting in reduced matching loss and simplified circuit implementation compared to conventional designs. This unique combination of wideband simultaneous noise- and input-matched cascode cell with the shunt-only input matching network confirms the effectiveness and practicality of the proposed design approach for future mm-wave wideband LNA applications.

5. Conclusions

This paper presents a wideband low-noise amplifier (LNA) implemented in a 150 nm GaAs pHEMT process, utilizing a cascode topology with a shunt-only input matching network. To provide deeper insights into the cascode core behavior, a two-port network-based analysis is conducted to quantitatively evaluate the effects of the source ( L S ) and drain ( L D ) inductors on power gain and stability. This approach enabled a precise determination of optimal inductor values while ensuring unconditional stability across the frequency range. Furthermore, the proposed shunt-only input matching network eliminates the need for series components and enables wideband simultaneous noise and input matching (SNIM) in a compact implementation. A three-stage amplifier is implemented to validate the design methodology. Simulation results confirm a flat gain of 20–23 dB, a low noise figure of 1.1–2.1 dB, and robust stability over the 17–38 GHz band. Monte Carlo analysis further demonstrates consistent performance under PVT variations. Compared to state-of-the-art GaAs-based amplifiers, the proposed design achieves the highest figure of merit (FoM). This confirms the practicality and performance advantage of combining a shunt-only SNIM approach with a cascode topology.

Author Contributions

Conceptualization, D.-W.P.; methodology, D.K., Y.L., D.-W.P.; software, D.K., Y.L.; validation, D.K., Y.L., D.-W.P.; formal analysis, D.K., Y.L., D.-W.P.; investigation, D.K., Y.L.; resources, D.K., Y.L.; data curation, D.K., Y.L.; writing—original draft preparation, D.K., Y.L.; writing—review and editing, D.K., Y.L., D.-W.P.; visualization, D.K., Y.L.; supervision, D.K., Y.L., D.-W.P.; project administration, D.K., Y.L., D.-W.P.; funding acquisition, D.-W.P. All authors have read and agreed to the published version of the manuscript.

Funding

This research was supported by Seoul National University of Science and Technology.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Informed consent was obtained from all subjects involved in the study.

Data Availability Statement

Data are contained within this article.

Conflicts of Interest

The authors declare no conflicts of interest.

References

  1. Andrews, J.G.; Buzzi, S.; Choi, W.; Hanly, S.V.; Lozano, A.; Soong, A.C.; Zhang, J.C. What will 5G be? IEEE J. Sel. Areas Commun. 2014, 32, 1065–1082. [Google Scholar] [CrossRef]
  2. Fukui, H. Optimal noise figure of microwave GaAs MESFET’s. IEEE Trans. Electron Devices 1979, 26, 1032–1037. [Google Scholar] [CrossRef]
  3. Alessandrello, A.; Brofferio, C.; Camin, D.; Giuliani, A.; Pessina, G.; Previtali, E. On the use of GaAs MESFETs in the realization of low-frequency low-noise amplifiers for applications at cryogenic temperatures. In Proceedings of the 11th Annual Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, San Diego, CA, USA, 22–25 October 1989; pp. 223–226. [Google Scholar]
  4. Nikandish, G.; Yousefi, A.; Kalantari, M. A broadband multistage LNA with bandwidth and linearity enhancement. IEEE Microw. Wirel. Components Lett. 2016, 26, 834–836. [Google Scholar] [CrossRef]
  5. Yu, Y.H.; Hsu, W.H.; Chen, Y.J.E. A Ka-band low noise amplifier using forward combining technique. IEEE Microw. Wirel. Components Lett. 2010, 20, 672–674. [Google Scholar] [CrossRef]
  6. Yan, X.; Yu, P.; Zhang, J.; Gao, S.P.; Guo, Y. A broadband 10–43-GHz high-gain LNA MMIC using coupled-line feedback in 0.15-μm GaAs pHEMT technology. IEEE Microw. Wirel. Components Lett. 2022, 32, 1459–1462. [Google Scholar] [CrossRef]
  7. Cuadrado-Calle, D.; George, D.; Fuller, G. A GaAs Ka-band (26–36 GHz) LNA for radio astronomy. In Proceedings of the 2014 IEEE International Microwave and RF Conference (IMaRC), Bangalore, India, 15–17 December 2014; pp. 301–303. [Google Scholar]
  8. Galante-Sempere, D.; Khemchandani, S.L.; Del Pino, J. A 2-V 1.4-dB NF GaAs MMIC LNA for K-Band Applications. Sensors 2023, 23, 867. [Google Scholar] [CrossRef]
  9. Wang, T.P. Design and Analysis of Simultaneous Wideband Input/Output Matching Technique for Ultra-Wideband Amplifier. IEEE Access 2021, 9, 46800–46809. [Google Scholar] [CrossRef]
  10. Nikandish, G.; Medi, A. Transformer-feedback interstage bandwidth enhancement for MMIC multistage amplifiers. IEEE Trans. Microw. Theory Tech. 2014, 63, 441–448. [Google Scholar] [CrossRef]
  11. Wang, Z.; Hou, D.; Li, Z.; Zhou, P.; Chen, Z.; Chen, J.; Hong, W. A linearity-enhanced 18.7–36.5-GHz LNA with 1.5–2.1-dB NF for radar applications. IEEE Microw. Wirel. Components Lett. 2022, 32, 972–975. [Google Scholar] [CrossRef]
  12. Hwang, S.; Kang, D.; Lee, Y.; Park, D.W. A 13–33 GHz Wideband Low-Noise Amplifier in 150-nm GaAs Based on Simultaneous Noise-and Input-Matched Gain-Core with RLC Shunt Feedback Network. Electronics 2025, 14, 450. [Google Scholar] [CrossRef]
  13. He, D.; Cui, N.; Fan, J.; Yu, Z. Design of Multiple Feedback-Based Low-Noise Amplifier With Improved Broadband Simultaneous Noise and Impedance Matching Technique. IEEE Trans. Circuits Syst. II Express Briefs 2024, 71, 582–586. [Google Scholar] [CrossRef]
  14. Wu, P.W.; Yei, J.W.; Fu, Z.H.; Chang, Y.T.; Lin, K.Y. A Wideband GaAs pHEMT LNA Multi-band 5G mmW Communication. In Proceedings of the 2023 Asia-Pacific Microwave Conference (APMC), Taipei, Taiwan, 5–8 December 2023; pp. 348–350. [Google Scholar]
  15. Feng, J.H.; Ye, Y.F.; Wu, L.S.; Mao, J.F. A Ka-Band Broadband Low Noise Amplifier with Resistive and Inductive Feedback. In Proceedings of the 2022 IEEE 4th International Conference on Circuits and Systems (ICCS), Chengdu, China, 23–26 September 2022; pp. 160–163. [Google Scholar]
  16. Seo, M.; Jagannathan, B.; Pekarik, J.; Rodwell, M.J.W. A 150 GHz Amplifier With 8 dB Gain and +6 dBm Psat in Digital 65 nm CMOS Using Dummy-Prefilled Microstrip Lines. IEEE J. Solid-State Circuits 2009, 44, 3410–3421. [Google Scholar] [CrossRef]
  17. Yun, B.; Park, D.W.; Mahmood, H.U.; Kim, D.; Lee, S.G. A D-band high-gain and low-power LNA in 65-nm CMOS by adopting simultaneous noise-and input-matched G max-core. IEEE Trans. Microw. Theory Tech. 2021, 69, 2519–2530. [Google Scholar] [CrossRef]
  18. Voinigescu, S.P.; Maliepaard, M.C.; Showell, J.L.; Babcock, G.E.; Marchesan, D.; Schroter, M.; Schvan, P.; Harame, D.L. A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design. IEEE J. Solid-State Circuits 2002, 32, 1430–1439. [Google Scholar] [CrossRef]
  19. Cha, C.Y.; Lee, S.G. A 5.2 GHz LNA in 0.35 μm CMOS utilizing inter-stage series resonance and optimizing the substrate resistance. In Proceedings of the 28th European Solid-State Circuits Conference, Florence, Italy, 24–26 September 2002; pp. 339–342. [Google Scholar]
  20. Shaeffer, D.K.; Lee, T.H. A 1.5-V, 1.5-GHz CMOS low noise amplifier. IEEE J. Solid-State Circuits 1997, 32, 745–759. [Google Scholar] [CrossRef]
  21. Razavi, B.; Behzad, R. RF Microelectronics; Prentice Hall: New York, NY, USA, 2012; Volume 2. [Google Scholar]
  22. Pozar, D.M. Microwave Engineering: Theory and Techniques; John wiley & Sons: New York, NY, USA, 2021. [Google Scholar]
  23. Chiu, H.W.; Lu, S.S.; Lin, Y.S. A 2.17-dB NF 5-GHz-band monolithic CMOS LNA with 10-mW DC power consumption. IEEE Trans. Microw. Theory Tech. 2005, 53, 813–824. [Google Scholar] [CrossRef]
  24. Belostotski, L.; Haslett, J.W. Noise figure optimization of inductively degenerated CMOS LNAs with integrated gate inductors. IEEE Trans. Circuits Syst. I: Regul. Pap. 2006, 53, 1409–1422. [Google Scholar] [CrossRef]
  25. Sun, K.J.; Tsai, Z.M.; Lin, K.Y.; Wang, H. A noise optimization formulation for CMOS low-noise amplifiers with on-chip low-Q inductors. IEEE Trans. Microw. Theory Tech. 2006, 54, 1554–1560. [Google Scholar]
  26. Çaışkan, C.; Kalyoncu, I.; Yazici, M.; Gurbuz, Y. Sub-1-dB and Wideband SiGe BiCMOS Low-Noise Amplifiers for X-Band Applications. IEEE Trans. Circuits Syst. I: Regul. Pap. 2018, 66, 1419–1430. [Google Scholar]
  27. Goo, J.S.; Ahn, H.T.; Ladwig, D.J.; Yu, Z.; Lee, T.H.; Dutton, R.W. A noise optimization technique for integrated low-noise amplifiers. IEEE J. Solid-State Circuits 2002, 37, 994–1002. [Google Scholar]
  28. Hu, J.; Ma, K.; Mou, S.; Meng, F. A seven-octave broadband LNA MMIC using bandwidth extension techniques and improved active load. IEEE Trans. Circuits Syst. I: Regul. Pap. 2018, 65, 3150–3161. [Google Scholar] [CrossRef]
  29. Li, W.T.; Tsai, J.H.; Yang, H.Y.; Chou, W.H.; Gea, S.B.; Lu, H.C.; Huang, T.W. Parasitic-insensitive linearization methods for 60-GHz 90-nm CMOS LNAs. IEEE Trans. Microw. Theory Tech. 2012, 60, 2512–2523. [Google Scholar] [CrossRef]
  30. Samavati, H.; Rategh, H.R.; Lee, T.H. A 5-GHz CMOS wireless LAN receiver front end. IEEE J. Solid-State Circuits 2002, 35, 765–772. [Google Scholar] [CrossRef]
  31. Huang, B.J.; Lin, K.Y.; Wang, H. Millimeter-wave low power and miniature CMOS multicascode low-noise amplifiers with noise reduction topology. IEEE Trans. Microw. Theory Tech. 2009, 57, 3049–3059. [Google Scholar] [CrossRef]
  32. Yan, X.; Zhang, J.; Luo, H.; Gao, S.P.; Guo, Y. A compact 1.0–12.5-GHz LNA MMIC with 1.5-dB NF based on multiple resistive feedback in 0.15-μm GaAs pHEMT technology. IEEE Trans. Circuits Syst. I: Regul. Pap. 2023, 70, 1450–1462. [Google Scholar] [CrossRef]
  33. Sabzi, M.; Medi, A. Analysis and design of multi-stage wideband LNA using simultaneously noise and impedance matching method. Microelectron. J. 2019, 86, 97–104. [Google Scholar] [CrossRef]
  34. Chen, H.K.; Chang, D.C.; Juang, Y.Z.; Lu, S.S. A compact wideband CMOS low-noise amplifier using shunt resistive-feedback and series inductive-peaking techniques. IEEE Microw. Wirel. Components Lett. 2007, 17, 616–618. [Google Scholar] [CrossRef]
  35. Hu, J.; Ma, K. A 1–40-GHz LNA MMIC using multiple bandwidth extension techniques. IEEE Microw. Wirel. Components Lett. 2019, 29, 336–338. [Google Scholar] [CrossRef]
  36. Wang, L.; Cheng, Y.J. A 2–20-GHz Ultrawideband High-Gain Low-Noise Amplifier With Enhanced Stability. IEEE Microw. Wirel. Technol. Lett. 2024, 34, 415–418. [Google Scholar] [CrossRef]
  37. Kobayashi, K.W.; Denninghoff, D.; Miller, D. A Novel 100 MHz–45 GHz Input-Termination-Less Distributed Amplifier Design With Low-Frequency Low-Noise and High Linearity Implemented With A 6 Inch 0.15 μm GaN-SiC Wafer Process Technology. IEEE J. Solid-State Circuits 2016, 51, 2017–2026. [Google Scholar] [CrossRef]
  38. Nikandish, G.; Medi, A. Unilateralization of MMIC distributed amplifiers. IEEE Trans. Microw. Theory Tech. 2014, 62, 3041–3052. [Google Scholar] [CrossRef]
  39. Cui, B.; Long, J.R. A 1.7-dB minimum NF, 22–32-GHz low-noise feedback amplifier with multistage noise matching in 22-nm FD-SOI CMOS. IEEE J. Solid-State Circuits 2020, 55, 1239–1248. [Google Scholar] [CrossRef]
  40. Deal, W.R.; Biedenbender, M.; Liu, P.h.; Uyeda, J.; Siddiqui, M.; Lai, R. Design and analysis of broadband dual-gate balanced low-noise amplifiers. IEEE J. Solid-State Circuits 2007, 42, 2107–2115. [Google Scholar] [CrossRef]
Figure 1. Schematic of (a) CS topology with L S and L G and, (b) cascode topology with L D , L S , and L G .
Figure 1. Schematic of (a) CS topology with L S and L G and, (b) cascode topology with L D , L S , and L G .
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Figure 2. Schematic of a cascode core cell and its two-port network-based modeling and analysis.
Figure 2. Schematic of a cascode core cell and its two-port network-based modeling and analysis.
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Figure 3. Effect of L D and L S on stability and gain. Three-dimensional plots of the stability factor K at (a) 18 GHz, (b) 28 GHz, and (c) 38 GHz, and the maximum available gain G m a at (d) 18 GHz, (e) 28 GHz, and (f) 38 GHz, with respect to L D and L S .
Figure 3. Effect of L D and L S on stability and gain. Three-dimensional plots of the stability factor K at (a) 18 GHz, (b) 28 GHz, and (c) 38 GHz, and the maximum available gain G m a at (d) 18 GHz, (e) 28 GHz, and (f) 38 GHz, with respect to L D and L S .
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Figure 4. Gain and noise matching points of the cascode core cell, visualized with 0.2 dB noise circles for three design sets: (a) Set 1, (b) Set 2, (c) Set 3.
Figure 4. Gain and noise matching points of the cascode core cell, visualized with 0.2 dB noise circles for three design sets: (a) Set 1, (b) Set 2, (c) Set 3.
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Figure 5. (a) Schematic of cascode core cell with a shunt-only input matching network, and (b) gain and noise matching points along with 0.2 dB noise circles, for the designed cascode cell incorporating the shunt-only input matching network.
Figure 5. (a) Schematic of cascode core cell with a shunt-only input matching network, and (b) gain and noise matching points along with 0.2 dB noise circles, for the designed cascode cell incorporating the shunt-only input matching network.
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Figure 6. Simulated (a) G m a , S 11 , and (b) noise characteristic of the designed first stage cascode core cell with DC bias line.
Figure 6. Simulated (a) G m a , S 11 , and (b) noise characteristic of the designed first stage cascode core cell with DC bias line.
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Figure 7. Complete schematic of the proposed three-stage cascode LNA.
Figure 7. Complete schematic of the proposed three-stage cascode LNA.
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Figure 8. Complete layout of the proposed three-stage cascode LNA.
Figure 8. Complete layout of the proposed three-stage cascode LNA.
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Figure 9. Simulated (a) S-parameters, (b) noise figure, (c) stability factor K and Δ , and (d) O P 1 d B and PAE of the proposed LNA versus frequency.
Figure 9. Simulated (a) S-parameters, (b) noise figure, (c) stability factor K and Δ , and (d) O P 1 d B and PAE of the proposed LNA versus frequency.
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Figure 10. Simulated S-parameter results at the center frequency of 30 GHz from a Monte Carlo analysis with 1000 samples, evaluating the impact of process, voltage, and temperature (PVT) variations.
Figure 10. Simulated S-parameter results at the center frequency of 30 GHz from a Monte Carlo analysis with 1000 samples, evaluating the impact of process, voltage, and temperature (PVT) variations.
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Figure 11. Simulated (a) noise figure and (b) Rollet’s stability factor at the center frequency of 30 GHz, obtained from a Monte Carlo analysis with 1000 samples to evaluate the influence of PVT variations.
Figure 11. Simulated (a) noise figure and (b) Rollet’s stability factor at the center frequency of 30 GHz, obtained from a Monte Carlo analysis with 1000 samples to evaluate the influence of PVT variations.
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Table 1. Design sets selected based on stability and G m a characteristics within the predetermined L S AND L D range.
Table 1. Design sets selected based on stability and G m a characteristics within the predetermined L S AND L D range.
Set L D  (nH) L S  (nH) G ma  (dB) @18 GHz G ma  (dB) @28 GHz G ma  (dB) @38 GHz
Set 100.2615.411.213.8
Set 20.05011.810.39.2
Set 30.10.110.79.310.8
Table 2. Measured and simulated performance of GaAs-based LNAs operating in the Ku, K, and Ka bands.
Table 2. Measured and simulated performance of GaAs-based LNAs operating in the Ku, K, and Ka bands.
ProcessTopologyFrequency
(GHz)
3-dB Bandwidth
(GHz)
| S 21 |
(dB)
Noise Figure
(dB)
P DC
(mW)
Area
(mm2)
OP 1 dB
(dBm)
FoM
[4]
(measured)
GaAs 100 nm3-stage cs with
coupled line and
feedback network
18–432521.6 (avg)1.8–2.7140211.5
(@30 GHz)
59 *
[5]
(measured)
GaAs 150 nm2-stage cs with
forward combining
29–441514 (avg)2–3.3380.47--
[6]
(measured)
GaAs 150 nm3-stage cs with
coupled line and
feedback network
10–433321.6–24.62.4–31101.051.95–12.3117.2
[10]
(measured)
GaAs 100 nm3-stage cs with
transformer
feedback network
11–392823 (avg)2.1–3801.78.6
(max)
57.5 *
[11]
(measured)
GaAs 100 nm2-stage cs with
feedback network
18.7–36.517.815.9 (max)1.5–2.1660.96--
[14]
(measured)
GaAs 150 nm3-stage cs25–431823.8 (max)2.1–3.47927 * (max)28.44 *
[15]
(measured)
GaAs 150 nm3-stage cs with
feedback network
24.25-338.7519.8 (max)2.45* (min)-1.24−6 (max)-
[40]
(measured)
GaAs 100 nmCascode with
balanced
dual-gate network
20–402020 (max)2.5 (max)-8.6--
[7]
(simulated)
GaAs 100 nm4-stage cs26–3610331.5–1.8-3.64--
[8]
(simulated)
GaAs 100 nm4-stage cs23–296331.4–2118.25.9410 *59.6 *
[12]
(simulated)
GaAs 150 nm3-stage cs with
R-L-C shunt
feedback network
13–332015.6–18.61–2.8993.36 *–12.8 *126.5 *
This Work
(simulated)
GaAs 150 nm3-stage enhanced cascode17–382120–231.1–2.13233.39.7–16.4139
* Read from curves.
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MDPI and ACS Style

Kang, D.; Lee, Y.; Park, D.-W. A 17–38 GHz Cascode Low-Noise Amplifier in 150-nm GaAs Adopting Simultaneous Noise- and Input-Matched Gain Stage with Shunt-Only Input Matching. Electronics 2025, 14, 2771. https://doi.org/10.3390/electronics14142771

AMA Style

Kang D, Lee Y, Park D-W. A 17–38 GHz Cascode Low-Noise Amplifier in 150-nm GaAs Adopting Simultaneous Noise- and Input-Matched Gain Stage with Shunt-Only Input Matching. Electronics. 2025; 14(14):2771. https://doi.org/10.3390/electronics14142771

Chicago/Turabian Style

Kang, Dongwan, Yeonggeon Lee, and Dae-Woong Park. 2025. "A 17–38 GHz Cascode Low-Noise Amplifier in 150-nm GaAs Adopting Simultaneous Noise- and Input-Matched Gain Stage with Shunt-Only Input Matching" Electronics 14, no. 14: 2771. https://doi.org/10.3390/electronics14142771

APA Style

Kang, D., Lee, Y., & Park, D.-W. (2025). A 17–38 GHz Cascode Low-Noise Amplifier in 150-nm GaAs Adopting Simultaneous Noise- and Input-Matched Gain Stage with Shunt-Only Input Matching. Electronics, 14(14), 2771. https://doi.org/10.3390/electronics14142771

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