Search Results (703)

Highly integrable silicon carbide (SiC) has emerged as a promising platform for photonic integrated circuits (PICs), offering a comprehensive set of material and optical properties that are ideal for the integration of nonlinear devices and solid-state quantum defects. However, despite significant progress in nanofabrication technology, the development of SiC on an insulator (SiCOI)-based photonics faces challenges due to fabrication-induced material optical losses and complex processing steps. An alternative approach to mitigate these fabrication challenges is the direct deposition of amorphous SiC on an insulator (a-SiCOI). However, there is a lack of systematic studies aimed at producing high optical quality a-SiC thin films, and correspondingly, on evaluating and determining their optical properties in the telecom range. To this end, we have studied a single-source precursor, 1,3,5-trisilacyclohexane (TSCH, C₃H₁₂Si₃), and chemical vapor deposition (CVD) processes for the deposition of SiC thin films in a low-temperature range (650–800 °C) on a multitude of different substrates. We have successfully demonstrated the fabrication of smooth, uniform, and stoichiometric a-SiCOI thin films of 20 nm to 600 nm with a highly controlled growth rate of ~0.5 Å/s and minimal surface roughness of ~5 Å. Spectroscopic ellipsometry and resonant micro-photoluminescence excitation spectroscopy and mapping reveal a high index of refraction (~2.7) and a minimal absorption coefficient (<200 cm⁻¹) in the telecom C-band, demonstrating the high optical quality of the films. These findings establish a strong foundation for scalable production of high-quality a-SiCOI thin films, enabling their application in advanced chip-scale telecom PIC technologies. Full article

Silicon-based microcavity quantum dot lasers are attractive candidates for on-chip light sources in photonic integrated circuits due to their small size, low power consumption, and compatibility with silicon photonic platforms. However, integrating components like quantum dot lasers and photodetectors on a single chip remains challenging due to material compatibility issues and mode field mismatch problems. In this work, we have demonstrated monolithic integration of an InAs quantum dot microdisk light emitter, waveguide, and photodetector on a silicon platform using a shared epitaxial structure. The photodetector successfully monitored variations in light emitter output power, experimentally proving the feasibility of this integrated scheme. This work represents a key step toward multifunctional integrated photonic systems. Future efforts will focus on enhancing the light emitter output power, improving waveguide efficiency, and scaling up the integration density for advanced applications in optical communication. Full article

A broadband, efficient monolithic microwave integrated circuit power amplifier (MMIC PA) in OMMIC’s 0.1 μm GaN-on-Si technology for 5G millimeter-wave communication is presented. This study concentrates on the output matching design, which has an important influence on the PA’s performance. A compact one-order synthesized transformer network (STN) is adopted to match the 50 Ω load to the extracted large-signal output model of the transistor. A dual-objective strategy is developed for parameter optimization, incorporating the impedance transformation trajectory inside the predefined optimal impedance domain (OID) that satisfies the required specifications, with approximation to selected optimal load impedances. By introducing a custom adjustment factor β into the error function, coupled with an automated iterative tuning process based on S-parameter simulations, desired broadband matching results can be rapidly achieved. The proposed two-stage PA occupies a small chip area of only 1.23 mm² and demonstrates good frequency consistency over the 24–31 GHz band. Continuous-wave characterization shows a flat small-signal gain of 19.7 ± 0.5 dB; both the output power (P_out) and the power-added efficiency (PAE) at the 4 dB compression point remain smooth, ranging from 32.3 to 32.7 dBm and 35.5% to 37.8%, respectively. The peak PAE reaches up to nearly 40% at the center frequency. Full article

With continuous advancements in semiconductor technology, mastering efficient designs of high-quality and advanced chips has become an important part of science and technology education. Chip performances will determine the futures of various aspects of societies. However, novice students often encounter difficulties in learning digital chip designs using Verilog programming, a common hardware design language. An efficient self-study system for supporting them that can offer various exercise problems, such that any answer is marked automatically, is in strong demand. In this paper, we design and implement a web-based Verilog programming learning assistant system (VPLAS), based on our previous works on software programming. Using a heuristic and guided learning method, VPLAS leads students to learn the basic circuit syntax step by step, until they acquire high-quality digital integrated circuit design abilities through self-study. For evaluation, we assign the proposal to 50 undergraduate students at the National Taipei University of Technology, Taiwan, who are taking the introductory chip-design course, and confirm that their learning outcomes using VPLAS together are far better than those obtained when following a traditional method. In our final statistics, students achieved an average initial accuracy rate of over 70% on their first attempts at answering questions after learning through our website’s tutorials. With the help of the system’s instant automated grading and rapid feedback, their average accuracy rate eventually exceeded 99%. This clearly demonstrates that our system effectively enables students to independently master Verilog circuit knowledge through self-directed learning. Full article

The increasing demand for high-speed, energy-efficient computing has propelled the development of integrated photonic logic gates, which utilize the speed of light to surpass the limitations of traditional electronic circuits. These gates enable ultrafast, parallel data processing with minimal power consumption, making them ideal for next-generation computing, telecommunications, and quantum applications. Recent advancements in nanofabrication, nonlinear optics, and phase-change materials have facilitated the seamless integration of all-optical logic gates onto compact photonic chips, significantly enhancing performance and scalability. This paper explores the latest breakthroughs in photonic logic gate design, key material innovations, and their transformative applications. While challenges such as fabrication precision and electronic–photonic integration remain, integrated photonic logic gates hold immense promise for revolutionizing optical computing, artificial intelligence, and secure communication. Full article

Stealthy chip-level tamper attacks, such as hardware Trojan insertions or security-critical circuit modifications, can threaten modern microelectronic systems’ security. While traditional inspection and side-channel methods offer potential for tamper detection, they may not reliably detect all forms of attacks and often face practical limitations in terms of scalability, accuracy, or applicability. This work introduces a non-invasive, contactless tamper detection method employing a complementary split-ring resonator (CSRR). CSRRs, which are typically deployed for non-destructive material characterization, can be placed on the surface of the chip’s package to detect subtle variations in the impedance of the chip’s power delivery network (PDN) caused by tampering. The changes in the PDN’s impedance profile perturb the local electric near field and consequently affect the sensor’s impedance. These changes manifest as measurable variations in the sensor’s scattering parameters. By monitoring these variations, our approach enables robust and cost-effective physical integrity verification requiring neither physical contact with the chips or printed circuit board (PCB) nor activation of the underlying malicious circuits. To validate our claims, we demonstrate the detection of various chip-level tamper events on an FPGA manufactured with 28 nm technology. Full article

For data-intensive applications like edge AI and image processing, we present a new reconfigurable 8T SRAM-based in-memory computing (IMC) macro designed for high-performance and energy-efficient operation. This architecture mitigates von Neumann limitations through numerous major breakthroughs. We built a new architecture with an adjustable capacitance array to substantially increase the multiply-and-accumulate (MAC) engine’s accuracy. It achieves 10–20 TOPS/W and >95% accuracy for 4–10-bit operations and is robust across PVT changes. By supporting binary and ternary neural networks (BNN/TNN) with XNOR-and-accumulate logic, a dual-mode inference engine further expands capabilities. With sub-5 ns mode switching, it can achieve up to 30 TOPS/W efficiency and >97% accuracy. In-memory Hamming error correction is implemented directly using integrated XOR circuitry. This technique eliminates off-chip ECC with >99% error correction and >98% MAC accuracy. Machine learning-aided co-optimization ensures sense amplifier dependability. To ensure CMOS compatibility, the macro may perform Boolean logic operations using normal 8T SRAM cells. Comparative circuit-level simulations show a 31.54% energy efficiency boost and a 74.81% delay reduction over other SRAM-based IMC solutions. These improvements make our macro ideal for real-time AI acceleration, cryptography, and next-generation edge computing, enabling advanced compute-in-memory systems. Full article

Next-generation smart sensing devices necessitate on-chip integration of power-efficient reference circuits. The latters are required to provide other circuit blocks with highly reliable bias signals, even in the presence of temperature shifts and supply voltage disturbances, while draining a small fraction of the overall power budget. In particular, it is especially challenging to design current references with enhanced robustness and efficiency; hence, thorough exploration of novel architectures and design approaches is needed for this type of circuits. In this work, we propose a novel CMOS-only current reference, achieving temperature compensation by exploiting geometry dependences of the threshold voltage (specifically, the reverse short-channel effect and the narrow-channel effect). This allows reaching first-order temperature compensation within a single current reference core. Implemented in 0.18 µm CMOS, a version of the proposed current reference designed to deliver 141 nA (with 377 nW of total power consumption) achieved an average temperature coefficient equal to 194 ppm/°C (from −20 °C to 80 °C) and an average line sensitivity of −0.017%/V across post-layout statistical Monte Carlo simulations. Based on such findings, the newly proposed design methodology stands out as a noteworthy solution to design robust current references for power-constrained mixed-signal systems-on-chip. Full article

In recent years, micro-combs, due to their compact structure and high efficiency, have proven to be a practical solution for optical sources. In this paper, an approach to flexibly modulating micro-combs is proposed, and a simulation platform based on ${\mathrm{Si}}_3{\mathrm{N}}_4$ micro-combs with highly integrated, tunable, and reconfigurable features is built. By means of the Lugiato–Lefever equation model, the dynamic evolution process of micro-combs is analyzed, and a micro-ring resonator is designed with a free spectral range of 7.24 nm, an effective mode area of $1.0829{\mu \mathrm{m}}^2$, and coherent comb lines spanning over 125 THz. Cascaded silicon nitride micro-ring filters are utilized to obtain reconfigurable modulation effects for Kerr-frequency micro-combs. Due to the significance of flexibly controlled optical sources with high-repetition rates and multiple channels for system-on-chip, our proposal has potential in photonic integrated circuit systems, such as high-density photonic computing and large-capacity optical communications, in the future. Full article

This paper presents the first demonstration and comparison of two identical oscillator circuits employing piezoelectric zinc oxide (ZnO) microelectromechanical systems (MEMS) resonators, implemented on conventional printed-circuit-board (PCB) and three-dimensional (3D)-printed acrylonitrile butadiene styrene (ABS) substrates. Both oscillators operate simultaneously at dual frequencies (260 MHz and 437 MHz) without the need for additional circuitry. The MEMS resonators, fabricated on silicon-on-insulator (SOI) wafers, exhibit high-quality factors (Q), ensuring superior phase noise performance. Experimental results indicate that the oscillator packaged using 3D-printed chip-carrier assembly achieves a 2–3 dB improvement in phase noise compared to the PCB-based oscillator, attributed to the ABS substrate’s lower dielectric loss and reduced parasitic effects at radio frequency (RF). Specifically, phase noise values between −84 and −77 dBc/Hz at 1 kHz offset and a noise floor of −163 dBc/Hz at far-from-carrier offset were achieved. Additionally, the 3D-printed ABS-based oscillator delivers notably higher output power (4.575 dBm at 260 MHz and 0.147 dBm at 437 MHz). To facilitate modular characterization, advanced packaging techniques leveraging precise 3D-printed encapsulation with sub-100 μm lateral interconnects were employed. These ensured robust packaging integrity without compromising oscillator performance. Furthermore, a comparison between two transistor technologies—a silicon germanium (SiGe) heterojunction bipolar transistor (HBT) and an enhancement-mode pseudomorphic high-electron-mobility transistor (E-pHEMT)—demonstrated that SiGe HBT transistors provide superior phase noise characteristics at close-to-carrier offset frequencies, with a significant 11 dB improvement observed at 1 kHz offset. These results highlight the promising potential of 3D-printed chip-carrier packaging techniques in high-performance MEMS oscillator applications. Full article

This paper presents a CMOS-based optoelectronic receiver integrated circuit (CORIC) realized in a standard 180 nm CMOS technology for the applications of short-distance optical interconnects. The CORIC comprises a spatially modulated P⁺/N-well on-chip avalanche photodiode (P⁺/NW APD) for optical-to-electrical conversion, a dummy APD at the differential input for enhanced common-mode noise rejection, a cross-coupled differential transimpedance amplifier (CCD-TIA) for current-to-voltage conversion, a 3-bit continuous-time linear equalizer (CTLE) for adaptive equalization by using NMOS registers, and a $f_T$-doubler output buffer (OB). The CTLE and $f_T$-doubler OB combination not only compensates the frequency-dependent signal loss, but also provides symmetric differential output signals. Post-layout simulations of the proposed CORIC reveal a transimpedance gain of 53.2 dBΩ, a bandwidth of 4.83 GHz even with a 490 fF parasitic capacitance from the on-chip P⁺/NW APD, a dynamic range of 60 dB that handles the input photocurrents from 1 μA_pp to 1 mA_pp, and a DC power consumption of 33.7 mW from a 1.8 V supply. The CORIC chip core occupies an area of 260 × 101 μm². Full article

This paper presents a 2-stage GaN Doherty power amplifier module (DPAM) on a compact $7\times 7$ quad flat no-lead (QFN) package, designed for the needs of 5G massive MIMO base transceiver systems. The interstage and input matching networks employ high-quality factor integrated passive devices (IPDs) to achieve a small form factor. This multi-chip module consists of three GaN-HEMT bare dies used for the driver stage, carrier amplifier, and peaking amplifier. Additionally, two IPD dies are included for the interstage and input matching networks. The external load network is developed using a printed circuit board (PCB). Utilizing a 5G NR signal of 100 MHz bandwidth and a 9.3 dB PAPR within the 3.4–3.8 GHz band, the developed DPAM demonstrated a power gain exceeding 26.8 dB and a power-added efficiency (PAE) greater than 37.8% at a 39 dBm average output power. Full article

Embedded differential temperature sensors can be utilized to monitor the power consumption of circuits, taking advantage of the inherent on-chip electrothermal coupling. Potential applications range from hardware security to linearity, gain/bandwidth calibration, defect-oriented testing, and compensation for circuit aging effects. This paper introduces the use of on-chip differential temperature sensors as part of a wireless Internet of Things system. A new low-power differential temperature sensor circuit with chopped cascode transistors and switched-capacitor integration is described. This design approach leverages chopper stabilization in combination with a switched-capacitor integrator that acts as a low-pass filter such that the circuit provides offset and low-frequency noise mitigation. Simulation results of the proposed differential temperature sensor in a 65 nm complementary metal-oxide-semiconductor (CMOS) process show a sensitivity of $33.18\mathrm{V}{/}^{°}\mathrm{C}$ within a linear range of $\pm 36.5{\mathrm{m}}^{°}\mathrm{C}$ and an integrated output noise of $0.862{\mathrm{mV}}_{\mathrm{rms}}$ (from 1 to 441.7 Hz) with an overall power consumption of $0.187\mathrm{mW}$. Considering a figure of merit that involves sensitivity, linear range, noise, and power, the new temperature sensor topology demonstrates a significant improvement compared to state-of-the-art differential temperature sensors for on-chip monitoring of power dissipation. Full article

Compact, broadband, multi-channel RF chips with low loss and high integration are required for high-performance phased-array systems. Presented in this paper is a four-channel, multifunction RF chip operating in the 5–18 GHz frequency range that integrates broadband phase shifting, amplitude control, power amplification, and switching functions. The chip is designed to have flip-chip bonding and stacked gold bumps to enable the compact 3D integration of the GaAs pHEMT and Si-CMOS. To ensure high-density interconnects with minimal parasitic effects, a fan-in redistribution process is implemented. The RF front-end part of this chip, fabricated through a 0.15 µm GaAs pHEMT process, integrates 6-bit digital phase shifters, 6-bit digital attenuators, low-noise amplifiers (LNAs), power amplifiers (PAs), and single-pole double-throw (SPDT) switches. To enhance multi-channel isolation and reduce crosstalk between RF chips and digital circuits, high isolation techniques, including a ground-coupled shield layer in the fan-in process and on-chip shield cavities, are utilized, which achieve isolation levels greater than 41 dB between adjacent RF channels. The measurement results demonstrate a reception gain of 0 dB with ±0.6 dB flatness, an NF below 11 dB, and transmit gain of more than 10 dB, with a VSWR of below 1.6 over the entire 5–18 GHz frequency band. The 6-bit phase shifter achieves a root mean square (RMS) phase error below 2.5° with an amplitude variation of less than 0.8 dB, while the 6-bit attenuator exhibits an RMS attenuation error of below 0.5 dB and a phase variation of less than 7°. The RF and digital chips are heterogeneously integrated using flip-chip and fan-in technology, resulting in a compact chip size of 6.2 × 6.2 × 0.33 mm³. These results validate that this is a compact, high-performance solution for advanced phased-array radar applications. Full article

This paper presents a highly linear two-stage InGaP/GaAs power amplifier integrated circuit (PAIC) using a dynamic predistorter for 5G small-cell applications. The proposed predistorter, based on a diode-connected transistor, utilizes a supply voltage to accurately control the linearization characteristics by adjusting its dc current. It is connected in parallel with an inter-stage of the two-stage PAIC through a series configuration of a resistor and an inductor, and features a shunt capacitor at the base of the transistor. These passive components have been optimized to enhance the linearization performance by managing the RF signal’s coupling to the diode. Using these optimized components, the AM−AM and AM−PM nonlinearities arising from the nonlinear resistance and capacitance in the diode can be effectively used to significantly flatten the AM−AM and AM−PM characteristics of the PAIC. The proposed predistorter was applied to the 2.6 GHz two-stage InGaP/GaAs HBT PAIC. The IC was tested using a 5 × 5 mm² module package based on a four-layer laminate. The load network was implemented off-chip on the laminate. By employing a continuous-wave (CW) signal, the AM−AM and AM−PM characteristics at 2.55–2.65 GHz were improved by approximately 0.05 dB and 3°, respectively. When utilizing the new radio (NR) signal, based on OFDM cyclic prefix (CP) with a signal bandwidth of 100 MHz and a peak-to-average power ratio (PAPR) of 9.7 dB, the power-added efficiency (PAE) reached at least 11.8%, and the average output power was no less than 24 dBm, achieving an adjacent channel leakage power ratio (ACLR) of −40.0 dBc. Full article