A Low-Power Differential Temperature Sensor with Chopped Cascode Transistors and Switched-Capacitor Integration

Abstract

Embedded differential temperature sensors can be utilized to monitor the power consumption of circuits, taking advantage of the inherent on-chip electrothermal coupling. Potential applications range from hardware security to linearity, gain/bandwidth calibration, defect-oriented testing, and compensation for circuit aging effects. This paper introduces the use of on-chip differential temperature sensors as part of a wireless Internet of Things system. A new low-power differential temperature sensor circuit with chopped cascode transistors and switched-capacitor integration is described. This design approach leverages chopper stabilization in combination with a switched-capacitor integrator that acts as a low-pass filter such that the circuit provides offset and low-frequency noise mitigation. Simulation results of the proposed differential temperature sensor in a 65 nm complementary metal-oxide-semiconductor (CMOS) process show a sensitivity of $33.18\mathrm{V}{/}^{°}\mathrm{C}$ within a linear range of $\pm 36.5{\mathrm{m}}^{°}\mathrm{C}$ and an integrated output noise of $0.862{\mathrm{mV}}_{\mathrm{rms}}$ (from 1 to 441.7 Hz) with an overall power consumption of $0.187\mathrm{mW}$. Considering a figure of merit that involves sensitivity, linear range, noise, and power, the new temperature sensor topology demonstrates a significant improvement compared to state-of-the-art differential temperature sensors for on-chip monitoring of power dissipation.

1. Introduction

Electrothermal coupling is a natural phenomenon that occurs due to the power dissipation of circuits on a die surface. It occurs when there is a transfer of heat between the circuit and the semiconductor substrate due to the circuit’s power consumption ($\mathrm{Power}=\mathrm{Voltage}\times \mathrm{Current}$) and the Joule effect [1,2]. This physical phenomenon generates a temperature change relative to the ambient chip temperature in the vicinity of the circuit. As part of the electrothermal coupling, there is a multiplication of voltages and currents within on-chip devices, which in turn creates power/temperature components at DC and various other frequencies. As experimentally validated in [3], thermal coupling has low-pass filtering characteristics, and measurements are usually performed up to 10 kHz. Furthermore, various approaches have been proposed to model and simulate electrothermal coupling effects using standard circuit simulators, such as in [1,4,5]. In these approaches, the silicon substrate is typically modeled with a thermal resistor–capacitor (RC) network for joint electrothermal coupling simulations with the electrical circuits under evaluation. As a result, the thermal profile of a fabricated integrated circuit (IC) can be a valuable source of information in monitoring the operation states and the performance of on-chip devices [1,2]. To monitor the slowly varying temperature gradients, on-chip differential temperature sensors can be employed, which are often found in applications such as tracking and compensating for the aging effects of power amplifiers [6], defect-oriented circuit testing [7], measuring the center frequency and 3 dB bandwidth of amplifiers [8,9], monitoring radio frequency (RF) circuit power and linearity [10], and on-chip hardware Trojan detection [11,12,13]. In the above-mentioned applications, the differential temperature sensors utilize bipolar junction transistors (BJTs) in order to sense the temperature gradients on-chip. Nevertheless, metal-oxide-semiconductor field-effect transistor (MOSFETs) also naturally have temperature-dependent parameters [14], such as their threshold voltage (${\mathrm{V}}_{\mathrm{TH}}$) and electron mobility ($\mu$), and they can be utilized as the sensing elements for differential temperature sensors [15,16,17]. Compared with conventional thermal/power profile extraction approaches that require the use of either infrared imaging of the exposed die surface [18] or active power-path current measurements [19], on-chip differential temperature sensors provide a non-invasive monitoring solution that does not require any electrical connections to the circuit under test (CUT), thereby avoiding the connection of any devices or switches along the signal path [12]. Furthermore, there is no need for any additional off-chip connections, which eases integration into SoCs. Since the information of interest is located at low frequencies, flicker noise and DC offsets are the key sources of errors, which require additional design considerations. One more important aspect to note is that in differential temperature sensors, the temperature difference is amplified with a high gain due to the differential operation, whereas the ambient chip temperature is suppressed because it appears as a common-mode signal [1].

The proposed two-stage fully differential temperature sensor is shown in Figure 1. The power dissipated from the CUT activities leads to a temperature change (${\mathrm{T}}_{\mathrm{s}}$), relative to the ambient chip temperature, within its adjacent area, which modulates the base-emitter ($∆{\mathrm{V}}_{\mathrm{BE}}$) voltage of the sensing bipolar junction transistor (BJT) [1,10] labeled as ${\mathrm{Q}}_1$ in Figure 1. In the first stage, a differential current ($∆{\mathrm{I}}_{\mathrm{in}}={\mathrm{i}}_{\mathrm{IN}+}-{\mathrm{i}}_{\mathrm{IN}-}$) is generated due to the temperature imbalance of ${\mathrm{Q}}_1$ and ${\mathrm{Q}}_2$ (${\mathrm{Q}}_1$ and ${\mathrm{Q}}_2$ are at different locations on the die), which is further amplified by the cascode differential amplifier with chopper stabilization (i.e., stage 1). In contrast to previous designs [10,11,12,13], the proposed circuit generates an output voltage by means of a cascode amplifier structure instead of using feedback resistors, which avoids the noise generated by the feedback resistors while achieving high sensitivity with low power and noise. Furthermore, in this design, the flicker noise of the cascode load is reduced significantly with the help of chopper stabilization. The second stage consists of a switched-capacitor integrator that suppresses the up-converted low-frequency noise.

This paper is organized as follows: In Section 2, a target application for the proposed differential temperature sensor is described as an example of the emerging opportunities for non-invasive power-based monitoring. In Section 3, the proposed differential temperature sensor is analyzed, and a discussion of key insights and design considerations is provided. To validate the circuit’s performance, simulation results are presented in Section 4. Section 5 provides the concluding remarks.

2. Target Application

Figure 2 depicts a potential application for the aforementioned differential temperature sensing approach, which is a system under development. This envisioned system incorporates a resilient, spectrum-agile low-power Internet of Things (IoT) System-on-Chip (SoC) with RF spectrum sensing at the sensor node, together with coordinated optimization and enhanced security at the edge device. On the wireless IoT sensor node side, the temperature change of the CUT is monitored for potential anomalous behavior with the help of multiple sensing BJT devices that are placed across the die and multiplexed to a single sensor circuit core as in [13]. In this approach, only one sensing BJT is selected at a time using analog multiplexers and decoders as in [12,13], which implies that the sensing BJTs are time-sharing one sensor core. The measured temperature gradients are wirelessly transmitted to the edge device where a machine learning (ML) algorithm, running on a Field-Programmable Gate Array (FPGA), processes the data to identify potential undesirable behaviors. More specifically, it was established in prior work [20] that an Autoencoder-based ML algorithm can identify the presence and potential location of HTs with 90% accuracy when the Trojan power consumption is as low as 2.5% of the CUT. In addition, besides its possible utilization for hardware Trojan detection in the discussed SoC, the differential temperature sensing approach can also be used as part of a broader anomaly detection system to monitor different RF circuit performance metrics such as the aging effects of power amplifiers [6], potential defects in low-noise amplifiers (LNAs) [7], the linearity of amplifiers [10], and the center frequency and 3 dB bandwidth of power amplifiers [8,9]. In such applications and in the envisioned SoC, the on-chip temperature sensors allow the detection of local differential temperature variations through electrothermal coupling due to the power dissipation in nearby devices, thereby serving as power detectors.

With regard to the capabilities of spectrum sensing in the envisioned system, it was demonstrated in [21] that by leveraging an on-chip analog spectrum sensor and a deep learning (DL) algorithm, empty spectrum can be identified in less than 1 $\mu$s to opportunistically initiate communication in available frequency bands. Additionally, fine-grained signal detection among channels in the $0.4\sim 6$ GHz range can be achieved for a number of different modulation signals. In IoT applications, a variety of different transceiver architectures have been reported with a wide range of power consumption (e.g., from 80 $\mu$W to 7 mW in [22,23,24,25]). It is envisioned that the measurements with the sensors will be performed periodically instead of continuously in many applications in order to save power.

The block diagram of the anticipated sensor signal processing path for the agile low-power SoC is displayed in Figure 3. It includes the proposed differential temperature sensor (i.e., stage 1 and stage 2 in Figure 1), an analog-to-digital converter (ADC), and a radio frequency transmitter (RF-TX). The differential signal generated in stage 1 by the BJT-based differential amplifier with cascode gain stage is further amplified by the integrator gain in stage 2. Implementing stage 2 of the differential temperature sensor with a switched-capacitor integrator enables the ability to reuse the clock signal of the ADC by deriving the switching and reset frequencies with on-chip digital dividers. In practice, an RF-TX can be employed to transmit the sensed data to the edge device in Figure 2 for the detection of hardware Trojans and, potentially, other anomalies.

3. Differential Temperature Sensor Design

3.1. BJT-Based Cascode Differential Amplifier

Figure 4a depicts the schematic of the proposed BJT-based cascode differential amplifier, consisting of ${\mathrm{M}}_1$, ${\mathrm{M}}_2$, ${\mathrm{M}}_3$, and two vertical N⁺ diffusion/Pwell/deep-Nwell (NPN) BJTs that are available in standard 65 nm CMOS processes. In addition, there are two calibration current sources: ${\mathrm{I}}_{\mathrm{CAL}+}$ and ${\mathrm{I}}_{\mathrm{CAL}-}$. Sensing device ${\mathrm{Q}}_1$ is located close to the CUT, while ${\mathrm{Q}}_2$, which is identical to ${\mathrm{Q}}_1$, is placed at a reference location with a steady ambient chip temperature. More specifically, as with other differential temperature sensors [1,10,13], ${\mathrm{Q}}_2$ should be placed at least $150 \mu$m away from digital circuits with high switching activity and from analog circuits with high dynamic power levels. Thermal coupling effects from the CUT lead to a temperature change (${\mathrm{T}}_{\mathrm{s}}$) at the sensor location in the adjacent area of the CUT. To mimic such temperature change using a standard electrical simulator [26], an ideal voltage-controlled voltage source with a gain of $\mathrm{k}=-1.4\mathrm{mV}/\mathrm{K}$ is employed to model the temperature-dependent base-emitter voltage (${\mathrm{V}}_{\mathrm{BE}}$) of the BJTs [1].

The sensing and reference BJTs form a differential pair in the first amplification stage, where the temperature difference is the effective input signal as it leads to changes of the base-emitter voltages that ultimately change the differential collector currents. The collector currents flow through the high output impedance (${\mathit{R}}_{\mathit{out}}$) of the amplifier that is approximated by Equation (1), thus generating a differential output voltage. The temperature-to-voltage gain (${\mathit{A}}_{\mathit{v}1}$) of this structure is given by Equation (2), where ${\mathit{g}}_{\mathit{m}1}$, ${\mathit{g}}_{\mathit{m}2}$, ${\mathit{g}}_{\mathit{m}3}$, ${\mathit{g}}_{\mathit{mQ}}$, ${\mathit{r}}_{\mathit{ds}1}$, ${\mathit{r}}_{\mathit{ds}2}$, ${\mathit{r}}_{\mathit{ds}3}$, and ${\mathit{r}}_{\mathit{ce}}$ are the transconductances and output resistances (drain-to-source or collector-to-emitter) of MOSFETs and BJTs, respectively.

$$R_{out}\approx (g_{m2}{r}_{ds2}{r}_{ds1}//g_{m3}{r}_{ds3}{r}_{ce})$$

(1)

$$A_{v1}\approx {\displaystyle \frac{V_{out}}{T_s}}\approx k·g_{mQ}·R_{out}$$

(2)

A common-mode feedback (CMFB) circuit similar to [10] was designed to regulate the output common-mode voltage of the sensor by controlling the gate voltages of the transistors labeled ${\mathrm{M}}_1$. Various approaches have been reported for robust process–voltage–temperature (PVT)-insensitive generation of a stable power supply (${\mathrm{V}}_{\mathrm{DD}}$), bias voltages, and bias currents over wide temperature ranges [27,28,29,30,31,32]. These voltage/current references cover a temperature range from $-{20 }^{°}\mathrm{C}$ all the way to ${100 }^{°}\mathrm{C}$ with a temperature coefficient of less than $100\mathrm{ppm}{/}^{°}\mathrm{C}$, both with and without trimming. For this reason, the bias currents and voltages in this design are assumed constant during the temperature measurement. Furthermore, as can be observed from the simulation results in Section 4, any differential DC offsets from bias variations are suppressed by the calibration prior to the measurement.

3.2. Noise Analysis of the BJT-Based Cascode Differential Amplifier

The drain-to-source current-referred thermal and flicker noise contributions of ${\mathrm{M}}_1$ ($\overline{{\mathit{i}}_{\mathit{n},\mathit{M}\mathit{1}}^{\mathit{2}}}=\mathit{4}{\mathit{k}}_{\mathit{B}}\mathit{T}\gamma {\mathit{g}}_{\mathit{m}\mathit{1}}+{\displaystyle \frac{{\mathit{K}}_{\mathit{p}}{\mathit{g}}_{\mathit{m}\mathit{1}}^{\mathit{2}}}{{\mathit{W}}_{\mathit{1}}{\mathit{L}}_{\mathit{1}}{\mathit{C}}_{\mathit{ox}}\mathit{f}}}$), when referred to the output of the BJT-based cascode differential amplifier, can be expressed by Equations (3) and (4), where ${\mathit{k}}_{\mathit{B}}$ is the Boltzmann’s constant, $\mathit{T}$ is the absolute temperature in Kelvin, $\gamma$ is the noise coefficient of ${\mathrm{M}}_1$, ${\mathit{W}}_{\mathit{1}}$ and ${\mathit{L}}_{\mathit{1}}$ are the width and length of ${\mathrm{M}}_1$, ${\mathit{K}}_{\mathit{p}}$ is a manufacturing process-dependent constant, ${\mathit{C}}_{\mathit{ox}}$ is the gate oxide capacitance per unit area, and $\mathit{f}$ stands for frequency. The noise contributions of ${\mathrm{M}}_2$ and ${\mathrm{M}}_3$ can be ignored because they are cascode transistors with high drain-to-source resistance and as such have negligible impact on the overall output noise [33]. The noise contributions of the calibrations currents can be modeled as $\overline{{\mathit{i}}_{\mathit{n},\mathit{CAL}}^{\mathit{2}}}$, which when referred to the output of stage 1, can be described by Equation (5).

The collector-referred noise current density of ${\mathrm{Q}}_{1,2}$ ($\overline{{\mathit{i}}_{\mathit{n},\mathit{Q}\mathit{1},\mathit{2}}^{\mathit{2}}}$) can be expressed by Equation (6) based on [34]. ${\mathit{I}}_{\mathit{B}}$ and ${\mathit{I}}_{\mathit{C}}$ are the base and collector currents, respectively. K is a manufacturing process-dependent constant, and $\beta$ is the common-emitter current gain. In this design, ${\mathit{I}}_{\mathit{B}}={\mathit{I}}_{\mathit{core}}/2=10$$\mu \mathrm{A}$ and $\beta$ = 6.2. The BJT noise current flows into the output impedance of the proposed amplifier to generate the output-referred noise contribution of ${\mathrm{Q}}_{1,2}$ that is estimated using Equation (7).

$$\overline{V_{M_1,thermal}^2}\approx 8k_{B}T\gamma g_{m1}·{(g_{m2}{r}_{ds2}{r}_{ds1}//g_{m3}{r}_{ds3}{r}_{ce})}^2$$

(3)

$$\overline{V_{M_1,flicker}^2}\approx {\displaystyle \frac{2K_p{g}_{m1}^2}{W_1{L}_1{C}_{ox}f}}·{(g_{m2}{r}_{ds2}{r}_{ds1}//g_{m3}{r}_{ds3}{r}_{ce})}^2$$

(4)

$$\overline{V_{n,CAL}^2}\approx \overline{i_{n,CAL}^2}·{(g_{m2}{r}_{ds2}{r}_{ds1}//g_{m3}{r}_{ds3}{r}_{ce})}^2$$

(5)

$$\overline{I_{n,Q_{1,2}}^2}\approx 2q{I}_B{\beta }^2+{\displaystyle \frac{K{I}_B}{f}}{\beta }^2+2q{I}_C$$

(6)

$$\overline{V_{n,Q_{1,2}}^2}\approx \overline{I_{n,Q_{1,2}}^2}·{(g_{m2}{r}_{ds2}{r}_{ds1}//g_{m3}{r}_{ds3}{r}_{ce})}^2$$

(7)

Based on simulations, the flicker noise (i.e., Equation (4)) from ${\mathrm{M}}_1$ is the dominant noise source of the BJT-based cascode differential amplifier. To reduce the noise generated by ${\mathrm{M}}_1$, a chopper stabilization technique is applied [35]. In Figure 4, ${\mathrm{M}}_{3\mathrm{A}}$ and ${\mathrm{M}}_{3\mathrm{B}}$ are identical to ${\mathrm{M}}_3$, and they replace ${\mathrm{M}}_3$ in the first amplifier stage. These cascode transistors (${\mathrm{M}}_{3\mathrm{A}}$ and ${\mathrm{M}}_{3\mathrm{B}}$) are activated in an alternating fashion with a chopping frequency of ${\mathit{f}}_{\mathit{chop}}$ and thus form the chopped cascode transistors. Therefore, the chopped cascode transistors act as a modulator that up-converts the signal generated by ${\mathrm{Q}}_1$ and ${\mathrm{Q}}_2$ and the calibration currents (${\mathrm{I}}_{\mathrm{CAL}+}$, ${\mathrm{I}}_{\mathrm{CAL}-}$) to the frequency band around ${\mathit{f}}_{\mathit{chop}}$. The gate voltages of ${\mathrm{M}}_{3\mathrm{A}}$ and ${\mathrm{M}}_{3\mathrm{B}}$ are alternately biased between ${\mathrm{V}}_{\mathrm{b}2}$ (900 $\mathrm{mV}$) and 0 V, driven by the non-overlapping clock signals, ${\mathit{f}}_{\mathit{chop}}$ and $\overline{{\mathit{f}}_{\mathit{chop}}}$. More specifically, as can be seen in Figure 4b, $V_{GA}=0\mathrm{V}$ and $V_{GB}=900\mathrm{mV}$, which implies that ${\mathrm{M}}_{3\mathrm{B}}$ transistors are activated while ${\mathrm{M}}_{3\mathrm{A}}$ transistors are disabled. In Figure 4c, $V_{GA}=900\mathrm{mV}$ and $V_{GB}=0\mathrm{V}$ such that ${\mathrm{M}}_{3\mathrm{A}}$ transistors are activated while ${\mathrm{M}}_{3\mathrm{B}}$ transistors are disabled. Note that when the cascode transistors are activated, they have the same operating point (biased in the saturation region) as regular cascode transistors instead of operating in the triode region as would be the case with standard switches used for chopping. On the other hand, the control switches, ${\mathrm{S}}_1$ and ${\mathrm{S}}_2$, alternate between cutoff and triode regions of operation. Switches labeled ${\mathrm{S}}_1$ are implemented with PMOS transistors, and switches labeled ${\mathrm{S}}_2$ are realized with NMOS transistors. Conventionally, the up-converting chopper modulator would be located in series with the cascode transistors (${\mathrm{M}}_3$) [36,37,38]. However, typical switching transistors tend to be large in size to achieve acceptable series resistance. For example, in this design, transistors in a conventional up-converting chopper modulator would require a 20 times larger $\mathrm{W}/\mathrm{L}$ ratio than the cascode transistors (${\mathrm{M}}_3$) to maintain a voltage drop of less than 10 mV across the chopper modulator. In contrast, reusing ${\mathrm{M}}_{3\mathrm{A}}$ and ${\mathrm{M}}_{3\mathrm{B}}$ as chopped cascode transistors to form the up-converting chopper modulator excludes the resistance of the conventional chopper modulator from the signal path to save area and voltage headroom. The output chopper modulator is placed at the drain of the ${\mathrm{M}}_2$ transistors in Figure 4 in order to down-convert the temperature information. Since the flicker noise in Equation (4) of ${\mathrm{M}}_1$ is only modulated by the down-converting chopper modulator, its equivalent output-referred noise is converted to odd harmonics of ${\mathit{f}}_{\mathit{chop}}$ and hence can be filtered out by the switched capacitor integrator in stage 2. According to [39], the output noise of stage 1 can be estimated as

$$\begin{array}{c}\hfill \overline{V_{n,out,st1}^2}\approx {\displaystyle \frac{8}{{\pi }^2}}(\overline{V_{M_1,flicker}^2}+\overline{V_{M_1,thermal}^2})·(1+{\displaystyle \frac{f_c}{f_{chop}}})+\overline{V_{Q_{1,2},BJT}^2}+\overline{V_{n,CAL}^2}\end{array}$$

(8)

where ${\mathit{f}}_{\mathit{c}}$ is the corner frequency of the flicker noise of ${\mathrm{M}}_1$, and $f_{chop}=10$ kHz in this design.

3.3. On-Chip Calibration Circuit

Mismatch due to process variation and on-chip thermal gradient can generate signal offsets, which in turn can saturate the high gain differential temperature sensor. Thus, prior to each temperature measurement, an on-chip calibration circuit is utilized to compensate for stage 1 mismatch.

The calibration circuit with its control signals is depicted in Figure 5. The calibration circuit consists of the following three components: three sets of switches labeled ${\mathrm{SW}}_1$, ${\mathrm{SW}}_2$ and ${\mathrm{SW}}_3$ to activate and deactivate the calibration circuits; two pairs of transistors (${\mathrm{M}}_{\mathrm{CAL}1}$ and ${\mathrm{M}}_{\mathrm{CAL}2}$) that inject calibration currents (in Figure 4: ${\mathrm{I}}_{\mathrm{CAL}+}={\mathrm{I}}_{\mathrm{CAL}1+}+{\mathrm{I}}_{\mathrm{CAL}2+}$, and ${\mathrm{I}}_{\mathrm{CAL}-}={\mathrm{I}}_{\mathrm{CAL}1-}+{\mathrm{I}}_{\mathrm{CAL}2-}$) into the BJT-based cascode differential amplifier; and a two-stage calibration amplifier that senses the differential signal from the first stage and generates two pairs of differential gate control voltages (${\mathrm{V}}_{\mathrm{CAL}1}$ and ${\mathrm{V}}_{\mathrm{CAL}2}$) for ${\mathrm{M}}_{\mathrm{CAL}1}$ and ${\mathrm{M}}_{\mathrm{CAL}2}$ in Figure 5, along with a pair of holding capacitors (${\mathrm{C}}_{\mathrm{HOLD}}$) to maintain ${\mathrm{V}}_{\mathrm{CAL}}$ during regular operation of the differential temperature sensor.

As shown in Figure 5, three main control signals define the four phases of the calibration. In the reset phase, ${\mathrm{I}}_{\mathrm{CAL}1}$ and ${\mathrm{I}}_{\mathrm{CAL}2}$ are reset to 0 A. During this phase, ${\varphi }_{RST}$ is high, while ${\varphi }_1$ and ${\varphi }_2$ are low, which closes ${\mathrm{SW}}_{\mathrm{R}}$ and opens ${\mathrm{SW}}_1$ and ${\mathrm{SW}}_2$. In this phase, ${\mathrm{C}}_{\mathrm{HOLD}}$ is connected to ${\mathrm{V}}_{\mathrm{CM}}$. Next, in calibration phase 1, the offset contributions of the chopped PMOS cascode load devices are suppressed. During this phase, ${\varphi }_1$ is high, while ${\varphi }_{RST}$ and ${\varphi }_2$ are low, which closes ${\mathrm{SW}}_1$ and opens ${\mathrm{SW}}_{\mathrm{R}}$ and ${\mathrm{SW}}_2$. The calibration amplifier is connected to ${\mathrm{V}}_{\mathrm{X}}$ = ${\mathrm{V}}_{\mathrm{X}+}-{\mathrm{V}}_{\mathrm{X}-}$ in Figure 4. The amplifier generates a calibration voltage ${\mathrm{V}}_{\mathrm{CAL}1}$; hence, ${\mathrm{M}}_{\mathrm{CAL}1}$ inject a calibration current ${\mathrm{I}}_{\mathrm{CAL}1}$ into stage 1. A down-converting chopper modulator is placed in series with ${\mathrm{M}}_{\mathrm{CAL}1}$ transistors in order to modulate ${\mathrm{I}}_{\mathrm{CAL}1}$ with the same chopping frequency ${\mathit{f}}_{\mathit{chop}}$ as in the main amplifier. In calibration phase 2, the electrical offset contributions of the BJT devices and any sensed on-chip thermal gradients are reduced through the calibration without chopping. During this phase, ${\varphi }_2$ is high, while ${\varphi }_{RST}$ and ${\varphi }_1$ are low, which closes ${\mathrm{SW}}_2$ and opens ${\mathrm{SW}}_{\mathrm{R}}$ and ${\mathrm{SW}}_1$. The calibration amplifier is connected to the output of stage 1, sensing the down-converted signal after the modulator. The amplifier generates a calibration voltage ${\mathrm{V}}_{\mathrm{CAL}2}$. Consequently, ${\mathrm{I}}_{\mathrm{Cal}2}$ is produced by ${\mathrm{M}}_{\mathrm{CAL}2}$ and injected into stage 1. In the hold phase, ${\varphi }_{RST}$, ${\varphi }_1$, and ${\varphi }_2$ are low, which opens ${\mathrm{SW}}_{\mathrm{R}}$, ${\mathrm{SW}}_1$, and ${\mathrm{SW}}_2$. The calibration amplifier is disconnected as well, and the holding capacitors (${\mathrm{C}}_{\mathrm{HOLD}}$) retain the gate control voltages (${\mathrm{V}}_{\mathrm{CAL}1}$ and ${\mathrm{V}}_{\mathrm{CAL}2}$). In this phase, the differential temperature sensor is activated for temperature-sensing measurements.

This calibration loop is similar to the one of the prototype chips measured in [13] but is designed specifically for this new sensor circuit. The calibration amplifier is a two-stage amplifier (Figure 6) similar to [13], with a common-mode feedback circuit such as the one in [10]. The amplifier has a simulated gain of 78.46 dB with a −3 dB frequency of 13.08 kHz and a unity-gain frequency of 18.88 MHz. The calibration loop exhibits an 84.2 dB gain with a unity-gain frequency of 1.26 kHz and a phase margin of ${47.6}^{°}$. The switches ${\mathrm{SW}}_{\mathrm{R}}$, ${\mathrm{SW}}_1$, and ${\mathrm{SW}}_2$ are implemented using transmission gates. The holding capacitors (${\mathrm{C}}_{\mathrm{HOLD}}$) are realized with 40 pF metal–insulator–metal (MIM) capacitors, which correspond to a layout area of $70\times 70\mu {\mathrm{m}}^2$ for each capacitor. A pair of 4 pF feedback capacitors (${\mathrm{C}}_{\mathrm{STAB}}$ in Figure 5) is employed across the calibration amplifier to generate a dominant pole at the output of stage 1 during the calibration phase.

3.4. Switched-Capacitor Integrator with Reset

Traditionally, chopper stabilization requires low-pass filtering after the down-converting chopper modulator in order to filter out the up-converted low-frequency noise and offsets [35,39]. More specifically, a switched-capacitor integrator with reset is able to provide low-pass filtering as its transfer function is mathematically equivalent to the sinc function [40,41,42]. Note that the notches of the sinc function appear at integer multiples of the reset frequency, and that the $-3$ dB bandwidth of the integrator is approximately equal to $0.44/$${\mathit{T}}_{\mathit{reset}}$[41], where ${\mathit{T}}_{\mathit{reset}}$ is the period of the reset signal. As displayed in Figure 7, a switched-capacitor integrator [43,44,45] with reset is proposed in lieu of continuous-time passive/active filters or integrators. This integrator is driven by the non-overlapping clock signals ${\varphi }_1$ and ${\varphi }_2$ with frequency $f_s=1/T_s$ and a reset signal ${\varphi }_{reset}$ with frequency $f_{reset}=1/T_{reset}$.

$$A_{v2}={\displaystyle \frac{f_s}{f_{reset}}}·{\displaystyle \frac{C_S}{C_F}}·\left|{\displaystyle \frac{sin\left(\pi f{T}_{reset}\right)}{\pi f{T}_{reset}}}\right|$$

(9)

Compared to conventional switched-capacitor amplifiers where sampling and reset share a single clock frequency, the gain of the integrator in this approach is defined not only by the ratio of the sampling and feedback capacitors (i.e., ${\mathit{C}}_{\mathit{S}}$ and ${\mathit{C}}_{\mathit{F}}$) but also by the ratio of the sampling/reset frequencies (i.e., ${\mathit{f}}_{\mathit{s}}$ and ${\mathit{f}}_{\mathit{reset}}$). Such a distinction allows for an extra degree of freedom when it comes to setting the gain of the integrator. More precisely, the frequency response of the integrator can be described by Equation (9), which preserves the shaping by the sinc function [40,41,42].

It should be noted that for integration to take place, it is necessary that ${\mathit{f}}_{\mathit{s}}>{\mathit{f}}_{\mathit{reset}}$. The larger the ratio $\mathit{N}={\mathit{f}}_{\mathit{s}}/{\mathit{f}}_{\mathit{reset}}$, the more samples will be added together before each reset, which translates to a higher gain. In this design, ${\mathit{f}}_{\mathit{s}}=100\mathrm{kHz}$ and ${\mathit{f}}_{\mathit{reset}}=1\mathrm{kHz}$. Metal–insulator–metal (MIM) capacitors are selected for ${\mathit{C}}_{\mathit{S}}$ and ${\mathit{C}}_{\mathit{F}}$ with a ratio of 0.1, where ${\mathit{C}}_{\mathit{S}}=0.2\mathrm{pF}$ and ${\mathit{C}}_{\mathit{F}}=2\mathrm{pF}$. Overall, this implies that, based on Equation (9), the low-frequency gain of the switched-capacitor integrator is 10. In addition, as evident in Figure 7, a correlated double sampling (CDS) technique such as the one in [46,47,48] was implemented to mitigate the effects of finite offsets in the operational transconductance amplifier (OTA) of the integrator. With this approach, the offset of the OTA is sampled in the first phase and then subtracted in the second phase. The value of the correlated double sampling MIM capacitor (${\mathrm{C}}_{\mathrm{CDS}}$ in Figure 7) is 1 pF. It is also important to mention that the reset takes place when the integrator is in its sampling phase (i.e., ${\varphi }_1$ is high to close the sampling switches). A differential folded cascode amplifier [49] is selected as the OTA of choice for this integrator, which is displayed in Figure 8. Node ${\mathrm{V}}_{\mathrm{CMFB}}$ is regulated through a common-mode feedback control loop [49]. The simulated low-frequency gain and 3 dB bandwidth of this OTA are 53 dB and 37 kHz, respectively, while the power consumption is 40 $\mu \mathrm{W}$ from a 1.2 V voltage supply.

Finally, the temperature-to-voltage gain (${\mathit{A}}_{\mathit{v}}$) of the proposed two-stage differential temperature sensor circuit can be expressed as in Equation (10).

$$A_v=A_{v1}·A_{v2}\approx k·g_{mQ}·R_{out}·{\displaystyle \frac{f_s}{f_{reset}}}·{\displaystyle \frac{C_s}{C_F}}·\left|{\displaystyle \frac{sin\left(\pi f{T}_{reset}\right)}{\pi f{T}_{reset}}}\right|$$

(10)

4. Simulation Results

4.1. Evaluation of Stage 1

Schematic simulations were conducted using the Cadence Spectre circuit simulator and foundry-supplied device models for a 65 nm CMOS process. The circuits were designed with a supply voltage of 1.2 V. Figure 9 shows the simulated frequency response of the first stage with chopping enabled, revealing a temperature-to-voltage gain of 9.99 dB with a cutoff frequency at 62.14 kHz, which is in agreement with Equation (2).

4.2. Frequency Response of the Differential Temperature Sensor

The overall frequency response of the proposed differential temperature sensor is displayed in Figure 10, which was obtained with the help of periodic AC (PAC) simulation. As discussed in Section 3.4, the transfer function of the integrator is equivalent to the sinc function, which is also evident in Figure 10. The simulated temperature-to-voltage gain in the passband is 30.64 dB, which follows Equation (10). The $-3$ dB frequency of the sensor is 441.7 Hz, which is approximately equal to $0.44/{\mathit{T}}_{\mathit{reset}}$, as discussed in Section 3.4 [41]. Moreover, as expected, the frequency response is colored by the sinc function of the integrator with notches at integer multiples of the reset frequency (${\mathit{f}}_{\mathit{reset}}=1\mathrm{kHz}$).

4.3. Noise Assessment

The simulation result with chopping (red solid curve) in Figure 11 indicates that the total output-referred noise of the complete temperature sensor circuit is reduced significantly with the help of chopper stabilization, especially compared to the result of the same sensor circuit but without chopping (green dashed curve). Within the 3 dB bandwidth (441.7 Hz) of the proposed differential temperature sensor, the integrated output noise was reduced by a factor of 7.12 thanks to chopping.

4.4. Sensitivity and Linear Range of the Proposed Differential Temperature Sensor

As can be seen in Figure 12, the output voltage and linear range of the proposed two-stage differential temperature sensor were evaluated under process variations with three process corners: SS (Slow–Slow), TT (Typical–Typical), and FF (Fast–Fast). Here, the linear range is defined as the range of the differential temperature over which the output voltage follows a linear relationship. The correlation between the simulated temperature sensitivity in the TT corner and the line of best fit is 0.995 for a range of $\pm 36.5{\mathrm{m}}^{°}\mathrm{C}$. The maximum differential temperature measurements error is $\pm 2.17{\mathrm{m}}^{°}\mathrm{C}$ in the range of $\pm 36.5{\mathrm{m}}^{°}\mathrm{C}$ and $\pm 0.64{\mathrm{m}}^{°}\mathrm{C}$ in the range of $\pm 30{\mathrm{m}}^{°}\mathrm{C}$.

The sensitivity vs. temperature change characteristics in Figure 13 were obtained by taking the derivative of the simulated output voltage curve in Figure 12 with respect to the relative temperature change between the sensing and reference BJTs. In the TT corner, the sensitivity around $0{\mathrm{m}}^{°}\mathrm{C}$ is $33.18\mathrm{V}{/}^{°}\mathrm{C}$. The sensitivity in the other process corners (SS and FF) varies from $31.33\mathrm{V}{/}^{°}\mathrm{C}$ to $33.13\mathrm{V}{/}^{°}\mathrm{C}$, which decreased by $-5.6\%$ (SS) and increased by $+0.15\%$ (FF) compared to the TT corner.

4.5. Monte Carlo Simulations

Monte Carlo simulations were performed to evaluate the effectiveness of the proposed calibration circuit for stage 1 and of the correlated double sampling method for stage 2. The histograms of the output offset voltages of stage 1 and of the complete two-stage differential temperature sensor are displayed in Figure 14 and Figure 15, respectively, which were obtained with transient simulations using statistical device models in the process design kit provided by the foundry. The stage 1 output offset was captured 3 ms after the start of the hold phase. With calibration, the stage 1 output offset after 100 Monte Carlo runs exhibits a mean of $-41.4\mu \mathrm{V}$ with a standard deviation of $347.37\mu \mathrm{V}$. The final two-stage differential temperature sensor output offset has a mean of −284 $\mu$V with a standard deviation of 5.22 mV. Considering that the gain of the two-stage differential temperature sensor is $33.18\mathrm{V}{/}^{°}\mathrm{C}$, the input-referred offset has a mean of −8.6 $\mu$°C with a standard deviation of 158.3 $\mu$°C.

The sensitivity of the complete two-stage differential temperature sensor around ${\mathrm{T}}_{\mathrm{S}}$ = 0 was also simulated in the presence of device mismatches. The sensitivity exhibits a mean of $32.8\mathrm{V}{/}^{°}\mathrm{C}$ with a standard deviation of $0.459\mathrm{V}{/}^{°}\mathrm{C}$ after 100 Monte Carlo simulations with activated calibration. Figure 16 shows the histogram from the simulations.

4.6. Discussion and Comparison with Other Works

Table 1. Comparison with other differential temperature sensors for which simulation results are reported.

Parameter	This Work	[9]	[11]	[12]
Technology (nm)	65	65	130	130
Sensitivity ($\mathrm{V}{/}^{°}\mathrm{C}$)	33.18	0.6	2.09	840
Linear Range (${\mathrm{m}}^{°}\mathrm{C}$)	±36.5	±600	±210	±1
Integrated Output Noise [1–${\mathrm{f}}_{\mathrm{c}}$ Hz] (${\mathrm{mV}}_{\mathrm{rms}}$)	0.862	n/a	0.38	60
Power Consumption (mW)	0.187	0.1368	1.08	1.452
${\mathrm{FoM}}_1$ (1/mW)	7513	n/a	1069	9.64
${\mathrm{FoM}}_2$ (V/mW)	6.476	2.632	0.406	0.579

${\mathrm{f}}_{\mathrm{c}}$ is the cutoff frequency of the temperature sensors. n/a: not reported or not applicable. ${\mathrm{FoM}}_1$ = ${\displaystyle \frac{\mathrm{Sensitivity}\times \mathrm{Linear}\mathrm{Range}}{\mathrm{Power}\times \mathrm{Integrated}\mathrm{Output}\mathrm{Noise}}}$ (1/mW); ${\mathrm{FoM}}_2$ = ${\displaystyle \frac{\mathrm{Sensitivity}\times \mathrm{Linear}\mathrm{Range}}{\mathrm{Power}}}$ (V/mW).

summarizes the simulated performance specifications of this work in comparison with other on-chip differential temperature sensors for which the simulated sensitivity (in $\mathrm{V}{/}^{°}\mathrm{C}$) is reported. Two figures of merit (FoMs) are introduced for comparison between different architectures. In contrast to differential temperature sensors that utilize transimpedance amplifiers [11,12], this work consumes less power while maintaining moderate sensitivity, linear range, and noise. When compared with [9], this work achieves higher sensitivity with similar power consumption. Overall, the simulation results indicate that this work has the highest FoMs compared with other differential temperature sensors for on-chip power monitoring. Therefore, the proposed two-stage differential temperature sensor can provide high performance in a broad range of future application scenarios.

5. Conclusions

A two-stage differential temperature sensor was introduced in this paper alongside its potential utilization in emerging wireless IoT systems for anomaly detection. In the first stage, a cascode structure provides high gain with a significant reduction in power consumption compared to previous high-sensitivity sensors. Furthermore, chopper stabilization was included to mitigate the effects of offsets and low-frequency noise. The discussed design approach involves a chopped cascode transistor technique, which reuses cascode transistors to act as the up-converting chopper modulator without affecting the overall performance of the sensor. This also circumvented a voltage drop in the signal path by avoiding a conventional chopper modulator in series with the cascode transistor. A two-phase calibration circuit was designed to compensate mismatches in the first stage. The second stage of this design consists of a switched-capacitor integrator with correlated double sampling. Due to its transfer function being equivalent to a sinc function, the integrator can provide the necessary low-pass filtering for the up-converted low-frequency noise from chopping while enabling more control of the gain through the use of different reset and sampling frequencies in addition to feedback capacitor values. The proposed design was evaluated with simulations, which indicate a sensitivity of $33.18\mathrm{V}{/}^{°}\mathrm{C}$ with a linear range of $\pm 36.5{\mathrm{m}}^{°}\mathrm{C}$, an integrated (from 1 to 441.7 Hz) output noise of $0.862{\mathrm{mV}}_{\mathrm{rms}}$, and an overall power consumption of $0.187\mathrm{mW}$. When compared to other differential temperature sensors for on-chip power monitoring, the proposed temperature sensor topology shows a notable performance improvement when considering a figure of merit that takes into account sensitivity, linear range, noise, and power consumption.