Search Results (466)

The unique properties of graphene have allowed for the development of graphene-based field-effect transistors (GFETs) for applications in biosensors and chemical devices. However, the modeling and optimization of GFET performance exhibit great challenges. Herein, we propose a quantum transport simulation model for graphene-based field-effect transistors (GFETs) implemented in the open-source Octave programming language. The proposed simulation model (named SimQ) combines the Landauer–Büttiker formalism with self-consistent Schrödinger–Poisson solutions, enabling reliable simulations of transport phenomena. Our approach agrees well with established models, achieving Landauer–Büttiker transmission and tunneling transmission of 0.28 and 0.92, respectively, which are validated against experimental data. The model can predict key GFET characteristics, including carrier mobilities (500–4000 cm²/V·s), quantum capacitance effects, and high-frequency operation (80–100 GHz). SimQ offers detailed insights into charge distribution and wave function evolution, achieving an enhanced computational efficiency through optimized algorithms. Our work contributes to the modeling of graphene-based field-effect transistors, providing a flexible and accessible simulation platform for designing and optimizing GFETs with potential applications in the next generation of electronic devices. Full article

AlGaN-based high-electron-mobility transistors are critical for next-generation power electronics and radio-frequency applications, yet achieving stable enhancement-mode operation with a high threshold voltage remains a key challenge. In this work, we designed p-AlGaN superlattices with different structures and performed energy band structure simulations using the device simulation software Silvaco. The results demonstrate that thin barrier structures lead to reduced acceptor incorporation, thereby decreasing the number of ionized acceptors, while facilitating vertical hole transport. Superlattice samples with varying periodic thicknesses were grown via metal-organic chemical vapor deposition, and their crystalline quality and electrical properties were characterized. The findings reveal that although gradient-thickness barriers contribute to enhancing hole concentration, the presence of thick barrier layers restricts hole tunneling and induces stronger scattering, ultimately increasing resistivity. In addition, we simulated the structure of the enhancement-mode HEMT with p-AlGaN as the under-gate material. Analysis of its energy band structure and channel carrier concentration indicates that adopting p-AlGaN superlattices as the under-gate material facilitates achieving a higher threshold voltage in enhancement-mode HEMT devices, which is crucial for improving device reliability and reducing power loss in practical applications such as electric vehicles. Full article

With their superior switching speed, GaN high-electron-mobility transistors (HEMTs) enable high power density, reduce energy losses, and increase power efficiency in a wide range of applications, such as power electronics, due to their high breakdown voltage. GaN-HEMT devices are subject to long-term reliability due to the self-heating effect and lattice mismatch between the SiC substrate and the GaN. Depletion-mode GaN HEMTs are utilized for radio frequency applications, and this work investigates three wide-bandgap (WBG) GaN HEMT fixed-frequency oscillators with output buffers. The first GaN-on-SiC HEMT oscillator consists of an HEMT amplifier with an LC feedback network. With the supply voltage of 0.8 V, the single-ended GaN oscillator can generate a signal at 8.85 GHz, and it also supplies output power of 2.4 dBm with a buffer supply of 3.0 V. At 1 MHz frequency offset from the carrier, the phase noise is −124.8 dBc/Hz, and the figure of merit (FOM) of the oscillator is −199.8 dBc/Hz. After the previous study, the hot-carrier stressed RF performance of the GaN oscillator is studied, and the oscillator was subject to a drain supply of 8 V for a stressing step time equal to 30 min and measured at the supply voltage of 0.8 V after the step operation for performance benchmark. Stress study indicates the power oscillator with buffer is a good structure for a reliable structure by operating the oscillator core at low supply and the buffer at high supply. The second balanced oscillator can generate a differential signal. The feedback filter consists of a left-handed transmission-line LC network by cascading three unit cells. At a 1 MHz frequency offset from the carrier of 3.818 GHz, the phase noise is −131.73 dBc/Hz, and the FOM of the 2nd oscillator is −188.4 dBc/Hz. High supply voltage operation shows phase noise degradation. The third GaN cross-coupled VCO uses 8-shaped inductors. The VCO uses a pair of drain inductors to improve the Q-factor of the LC tank, and it uses 8-shaped inductors for magnetic coupling noise suppression. At the VCO-core supply of 1.3 V and high buffer supply, the FOM at 6.397 GHz is −190.09 dBc/Hz. This work enhances the design techniques for reliable GaN HEMT oscillators and knowledge to design high-performance circuits. Full article

As transistor dimensions continue to scale below 10 nm, traditional MOSFET architectures face increasing limitations from short-channel effects, gate leakage, and variability. FinFETs, especially junctionless FinFETs on silicon-on-insulator (SOI) substrates, offer improved electrostatic control and simplified fabrication, making them attractive for deeply scaled nodes. In this work, we propose a novel Stepped-Spacer Structured FinFET (S³-FinFET) that incorporates a three-layer HfO₂/Si₃N₄/HfO₂ spacer configuration designed to enhance electrostatics and suppress parasitic effects. Using 2D TCAD simulations, the S³-FinFET is evaluated in terms of key performance metrics, including transfer/output characteristics, ON/OFF current ratio, subthreshold swing (SS), drain-induced barrier lowering (DIBL), gate capacitance, and cut-off frequency. The results show significant improvements in leakage control and high-frequency behavior. These enhancements make the S³-FinFET particularly well-suited for Field-Programmable Gate Arrays (FPGAs), where power efficiency, speed, and signal integrity are critical to performance in reconfigurable logic environments. Full article

High-frequency (h. f.) harmonic distortion (HD) of advanced SiGe heterojunction bipolar transistor (HBT)-based power cells (PwCs), featuring optimized metallization interconnections between individual HBTs, was investigated. Single tone input power (P_in) excitations at 1, 2, 5, and 10 GHz frequencies were employed. The output power (P_out) of the fundamental tone and its harmonics were analyzed in both the frequency and time domains. A rapid increase in the third harmonic of P_out was observed at input powers exceeding −8 dBm for a fundamental frequency of 10 GHz in two different PwC technologies. This increase in the third harmonic was analyzed in terms of nonlinear current waveforms, the nonlinearity of the HBT p-n junction diffusion capacitances, substrate current behavior versus P_in, and avalanche multiplication current. To assess the RF power performance of the PwCs, scalar and vectorial load-pull (LP) measurements were conducted and analyzed. Under matched conditions, the SiGe PwCs demonstrated good linearity, particularly at high frequencies. The key power performance of the PwCs was measured and simulated as follows: input power 1 dB compression point (P_{in_1dB}) of −3 dBm, transducer power gain (G_T) of 15 dB, and power added efficiency (PAE) of 50% at 30 GHz. All measured data were corroborated with simulations using the compact model HiCuM L2. Full article

This study presents a photoresist-free patterning method for solution-processed indium zinc oxide (IZO) thin films using two photochemical exposure techniques, namely pulsed ultraviolet (UV) light and UV-ozone, and a plasma-based method using oxygen (O₂) plasma. Pulsed UV light delivers short, high-intensity flashes of light that induce localised photochemical reactions with minimal thermal damage, whereas UV-ozone enables smooth and uniform surface oxidation through continuous low-pressure UV irradiation combined with in situ ozone generation. By contrast, O₂ plasma generates ionised oxygen species via radio frequency (RF) discharge, allowing rapid surface activation, although surface damage may occur because of energetic ion bombardment. All three approaches enabled pattern formation without the use of conventional photolithography or chemical developers, and the UV-ozone method produced the most uniform and clearly defined patterns. The patterned IZO films were applied as active layers in bottom-gate top-contact thin-film transistors, all of which exhibited functional operation, with the UV-ozone-patterned devices exhibiting the most favourable electrical performance. This comparative study demonstrates the potential of photochemical and plasma-assisted approaches as eco-friendly and scalable strategies for next-generation IZO patterning in electronic device applications. Full article

Aiming at the problems of low withstand voltage and poor RF performance of traditional HEMT devices, a new AlGaN/GaN high electron mobility transistor device with a π-gate (NπGS HEMT) is designed in this paper. The new structure incorporates a π-gate design along with a PN-junction field plate and an AlGaN back-barrier layer. The device is modeled and simulated in Silvaco TCAD 2015 software and compared with traditional t-gate HEMT devices. The results show that the NπGS HEMT has a significant improvement in various characteristics. The new structure has a higher peak transconductance of 336 mS·mm⁻¹, which is 13% higher than that of the traditional HEMT structure. In terms of output characteristics, the new structure has a higher saturation drain current of 0.188 A/mm. The new structure improves the RF performance of the device with a higher maximum cutoff frequency of about 839 GHz. The device also has a better performance in terms of voltage withstand, exhibiting a higher breakdown voltage of 1817 V. These results show that the proposed new structure could be useful for future research on high voltage withstand and high RF HEMT devices. Full article

Gallium nitride (GaN) enhancement-mode high-electron-mobility transistors ( E-HEMTs) deliver superior performance compared to traditional silicon (Si) and silicon carbide (SiC) counterparts. Their faster switching speeds, lower on-state resistances, and higher operating frequencies enable more efficient and compact power converters. However, their integration into high-power applications is limited by critical reliability concerns, particularly regarding their short-circuit (SC) withstand capability and overvoltage (OV) resilience. GaN devices typically exhibit SC withstand times of only a few hundred nanoseconds, needing ultrafast protection circuits, which conventional desaturation (DESAT) methods cannot adequately provide. Furthermore, their high switching transients increase the risk of false activation events. The lack of avalanche capability and the dynamic nature of GaN breakdown voltage exacerbate issues related to OV stress during fault conditions. Although SC-related behaviour in GaN devices has been previously studied, a focused and comprehensive review of protection strategies tailored to GaN technology remains lacking. This paper fills that gap by providing an in-depth analysis of SC and OV failure phenomena, coupled with a critical evaluation of current and next-generation protection schemes suitable for GaN-based high-power converters. Full article

The advancement of Internet of Things (IoT) technology has enabled battery-powered devices to be deployed across a wide range of applications; however, it also introduces challenges such as high energy consumption and security vulnerabilities. To address these issues, adiabatic logic circuits offer a promising solution for achieving energy efficiency and enhancing the security of IoT devices. Adiabatic logic circuits are well suited for energy harvesting systems, especially in applications such as sensor nodes, RFID tags, and other IoT implementations. In these systems, the harvested bipolar sinusoidal RF power is directly used as the power supply for the adiabatic logic circuit. However, adiabatic circuits require a peak detector to provide bulk biasing for pMOS transistors. To meet this requirement, a diode-connected MOS transistor-based voltage doubler circuit is used to convert the sinusoidal input into a usable DC signal. In this paper, we propose a novel adiabatic logic design that maintains low power consumption while optimizing energy and current fluctuations across various input transitions. By ensuring uniform and complementary current flow in each transition within the logic circuit’s functional blocks, the design reduces energy variation and enhances resistance against power analysis attacks. Evaluation under different clock frequencies and load capacitances demonstrates that the proposed adiabatic logic circuit exhibits lower fluctuation and improved security, particularly at load capacitances of 50 fF and 100 fF. The results show that the proposed circuit achieves lower power dissipation compared to conventional designs. As an application example, we implemented an ultrasonic transmitter circuit within a LoRaWAN network at the end-node sensor level, which serves as both a communication protocol and system architecture for long-range communication systems. Full article

Titanium dioxide (TiO₂) is a wide-bandgap semiconductor material with broad application potential, known for its excellent photocatalytic performance, high chemical stability, low cost, and non-toxicity. These properties make it highly attractive for applications in photovoltaic energy, environmental remediation, and optoelectronic devices. For instance, TiO₂ is widely used as a photocatalyst for hydrogen production via water splitting and for degrading organic pollutants, thanks to its efficient photo-generated electron–hole separation. Additionally, TiO₂ exhibits remarkable performance in dye-sensitized solar cells and photodetectors, providing critical support for advancements in green energy and photoelectric conversion technologies. Boron-doped diamond (BDD) is renowned for its exceptional electrical conductivity, high hardness, wide electrochemical window, and outstanding chemical inertness. These unique characteristics enable its extensive use in fields such as electrochemical analysis, electrocatalysis, sensors, and biomedicine. For example, BDD electrodes exhibit high sensitivity and stability in detecting trace chemicals and pollutants, while also demonstrating excellent performance in electrocatalytic water splitting and industrial wastewater treatment. Its chemical stability and biocompatibility make it an ideal material for biosensors and implantable devices. Research indicates that the combination of TiO₂ nanostructures and BDD into heterostructures can exhibit unexpected optical and electrical performance and transport behavior, opening up new possibilities for photoluminescence and rectifier diode devices. However, applications based on this heterostructure still face challenges, particularly in terms of photodetector, photoelectric emitter, optical modulator, and optical fiber devices under high-temperature conditions. This article explores the potential and prospects of their combined heterostructures in the field of optoelectronic devices such as photodetector, light emitting diode (LED), memory, field effect transistor (FET) and sensing. TiO₂/BDD heterojunction can enhance photoresponsivity and extend the spectral detection range which enables stability in high-temperature and harsh environments due to BDD’s thermal conductivity. This article proposes future research directions and prospects to facilitate the development of TiO₂ nanostructured materials and BDD-based heterostructures, providing a foundation for enhancing photoresponsivity and extending the spectral detection range enables stability in high-temperature and high-frequency optoelectronic devices field. Further research and exploration of optoelectronic devices based on TiO₂-BDD heterostructures hold significant importance, offering new breakthroughs and innovations for the future development of optoelectronic technology. Full article

This paper presents the first demonstration and comparison of two identical oscillator circuits employing piezoelectric zinc oxide (ZnO) microelectromechanical systems (MEMS) resonators, implemented on conventional printed-circuit-board (PCB) and three-dimensional (3D)-printed acrylonitrile butadiene styrene (ABS) substrates. Both oscillators operate simultaneously at dual frequencies (260 MHz and 437 MHz) without the need for additional circuitry. The MEMS resonators, fabricated on silicon-on-insulator (SOI) wafers, exhibit high-quality factors (Q), ensuring superior phase noise performance. Experimental results indicate that the oscillator packaged using 3D-printed chip-carrier assembly achieves a 2–3 dB improvement in phase noise compared to the PCB-based oscillator, attributed to the ABS substrate’s lower dielectric loss and reduced parasitic effects at radio frequency (RF). Specifically, phase noise values between −84 and −77 dBc/Hz at 1 kHz offset and a noise floor of −163 dBc/Hz at far-from-carrier offset were achieved. Additionally, the 3D-printed ABS-based oscillator delivers notably higher output power (4.575 dBm at 260 MHz and 0.147 dBm at 437 MHz). To facilitate modular characterization, advanced packaging techniques leveraging precise 3D-printed encapsulation with sub-100 μm lateral interconnects were employed. These ensured robust packaging integrity without compromising oscillator performance. Furthermore, a comparison between two transistor technologies—a silicon germanium (SiGe) heterojunction bipolar transistor (HBT) and an enhancement-mode pseudomorphic high-electron-mobility transistor (E-pHEMT)—demonstrated that SiGe HBT transistors provide superior phase noise characteristics at close-to-carrier offset frequencies, with a significant 11 dB improvement observed at 1 kHz offset. These results highlight the promising potential of 3D-printed chip-carrier packaging techniques in high-performance MEMS oscillator applications. Full article

This paper presents an optimized 868 MHz low-noise amplifier (LNA) based on a bipolar junction transistor (BJT), specifically designed for wake-up receivers operating in the sub-GHz band. The proposed LNA achieves low noise, high gain, and good impedance matching while consuming only $3.2$ mA from a $3.3$ V supply, resulting in a total power consumption of $10.56$ mW. Designing efficient sub-GHz LNAs for low-power applications involves a careful balance between multiple performance metrics. Higher gain typically requires increased biasing current, which can raise power consumption, while achieving a low noise figure often conflicts with input-matching constraints. The presented design addresses these trade-offs by leveraging the BFP740 BJT and employing a stub-based microstrip matching network to simultaneously optimize the gain, noise figure, and input–output matching. Simulation results, using both external lumped elements and microstrip techniques, show a forward gain ($S_{21}$) of $15.2$ dB at 868 MHz, with an input reflection coefficient ($S_{11}$) of $-6.9$ dB and an output reflection coefficient ($S_{22}$) of $-6.3$ dB. The amplifier achieves a minimum noise figure of approximately $1.77$ dB, which is notably low for this frequency band. These results demonstrate that the proposed LNA offers a compact, energy-efficient, and cost-effective solution, ideally suited for always-on, low-power wireless applications such as Internet of Things (IoT) devices and wireless sensor networks. Full article

This paper introduces a high-efficiency buck converter designed for a wide load range, targeting low-power applications in medical devices, smart homes, wearables, IoT, and technology utilizing WiFi and Bluetooth. To achieve high efficiency across varying loads, the proposed converter employs a low-power adaptive on-time (AOT) controller that ensures output voltage stability and seamless mode transitions. An adaptive comparator (ACP) with variable output impedance is introduced, offering a variable DC gain and bandwidth to be suitable for different load conditions. A negative-level shifter (NLS) circuit, with its swing ranging from −0.5 V to the battery voltage (V_BAT), is proposed to control the smaller power p-MOS transistors. By using an NLS, the chip area, which is mostly occupied by power CMOS transistors, is reduced while the power efficiency is improved, particularly under a heavy load. A status time detector (STD) block which provides control signals to the ACP and NLS for optimized power consumption is added to identify load conditions (heavy, light, ultra-light). By employing a 180 nm CMOS technology, the active chip area occupies about 0.31 mm². With an input voltage range of 2.8–3.3 V, the controller’s current consumption ranges from 1.2 μA to 16 μA, corresponding to the output load current varying from 12 μA to 120 mA. Although the output load can vary, the output voltage is regulated at 1.2 V with a ripple between 3 and 12 mV. The proposed design achieves a peak efficiency of 96.2% under a heavy load with a switching frequency of 1.3 MHz. Full article

This paper presents a comprehensive review of High-Voltage Direct-Current (HVDC) systems, focusing on their technological evolution, fault characteristics, and advanced signal processing techniques for fault detection. The paper traces the development of HVDC links globally, highlighting the transition from mercury-arc valves to Insulated Gate Bipolar Transistor (IGBT)-based converters and showcasing operational projects in technologically advanced countries. A detailed comparison of converter technologies including line-commutated converters (LCCs), Voltage-Source Converters (VSCs), and Modular Multilevel Converters (MMCs) and pole configurations (monopolar, bipolar, homopolar, and MMC) is provided. The paper categorizes HVDC faults into AC, converter, and DC types, focusing on their primary locations and fault characteristics. Signal processing methods, including time-domain, frequency-domain, and time–frequency-domain approaches, are systematically compared, supported by relevant case studies. The review identifies critical research gaps in enhancing the reliability of fault detection, classification, and protection under diverse fault conditions, offering insights into future advancements in HVDC system resilience. Full article

A dual Al₂O₃ MIS gate structure is proposed to enhance the DC and RF performance of enhancement-mode GaN high-electron mobility transistors (HEMTs). As a result, the proposed MOS-HEMT with a dual recessed MIS gate structure offers 84% improvements in cutoff frequency (f_T) and 92% improvements in maximum oscillation frequency (f_max) compared to conventional HEMTs (from 7.1 GHz to 13.1 GHz and 17.5 GHz to 33.6 GHz, respectively). As for direct-current characteristics, a remarkable reduction in off-state gate leakage current and a 26% enhancement in the maximum saturation drain current (from 519 mA·mm⁻¹ to 658 A·mm⁻¹) are manifested in HEMTs with new structures. The maximum transconductance (g_m) is also raised from 209 mS·mm⁻¹ to 246 mS·mm⁻¹. Correspondingly, almost unchanged gate–source capacitance curves and gate–drain capacitance curves are also discussed to explain the electrical characteristic mechanism. These results indicate the superiority of using a dual Al₂O₃ MIS gate structure in GaN-based HEMTs to promote the RF and DC performance, providing a reference for further development in a miniwatt antenna amplifier and sub-6G frequencies of operation. Full article