A Low-Power 868 MHz BJT-Based LNA with Microstrip Matching for Wake-Up Receivers in IoT Applications

Abstract

This paper presents an optimized 868 MHz low-noise amplifier (LNA) based on a bipolar junction transistor (BJT), specifically designed for wake-up receivers operating in the sub-GHz band. The proposed LNA achieves low noise, high gain, and good impedance matching while consuming only $3.2$ mA from a $3.3$ V supply, resulting in a total power consumption of $10.56$ mW. Designing efficient sub-GHz LNAs for low-power applications involves a careful balance between multiple performance metrics. Higher gain typically requires increased biasing current, which can raise power consumption, while achieving a low noise figure often conflicts with input-matching constraints. The presented design addresses these trade-offs by leveraging the BFP740 BJT and employing a stub-based microstrip matching network to simultaneously optimize the gain, noise figure, and input–output matching. Simulation results, using both external lumped elements and microstrip techniques, show a forward gain ($S_{21}$) of $15.2$ dB at 868 MHz, with an input reflection coefficient ($S_{11}$) of $-6.9$ dB and an output reflection coefficient ($S_{22}$) of $-6.3$ dB. The amplifier achieves a minimum noise figure of approximately $1.77$ dB, which is notably low for this frequency band. These results demonstrate that the proposed LNA offers a compact, energy-efficient, and cost-effective solution, ideally suited for always-on, low-power wireless applications such as Internet of Things (IoT) devices and wireless sensor networks.

1. Introduction

In any wireless communication system, the transmit power, receiver sensitivity, and frequency band are highly important. Energy efficiency also plays a critical role in internet of things (IoT) devices such as wireless sensor networks (WSN). Batteries are often used to power the hardware of current-generation nodes. Due to the compact device size and constrained energy sources, minimizing power consumption remains a critical design challenge [1]. Ensuring the highest possible level of efficiency in order to provide reliable services is becoming a complex undertaking. Minimal end-to-end latency, extensive wireless coverage, and consistent and resilient performance robustness are critical elements in optimizing wireless communication efficiency [2].

Building an accurate energy consumption model involves managing various trade-offs, including the complex interplay between sensing, data processing, and radio-related functions (transmission, reception, and idle). This process presents significant challenges, as it is highly dependent on the specifics of the given application context.

Therefore, in order to effectively reduce energy waste, it is critical to minimize the amount of time that the communication module is in its active state (idle mode, receive mode, or transmit mode). This technique can be applied comprehensively across the entire node, or it can be selectively applied to specific components, with a focus on the most power-hungry elements [3].

Energy-efficient techniques involve keeping the radio of the node in a deep sleep state when there is no radio frequency (RF) traffic. These techniques can be divided into two categories: software-based solutions that use low-duty MAC protocols, and hardware-based methods that use specialized wake-up modules, both of which significantly reduce the power consumption of sensor nodes while keeping them in an “asleep-yet-awake” state [4]. This work belongs to the second approach. A representative example of such hardware-based solutions is presented in [5], where the authors design an ultra-low power wake-up receiver with integrated baseband logic and a gated oscillator-based clock and data recovery circuit. Their system supports continuous data reception with nanowatt-level power consumption, demonstrating the effectiveness of hardware-level techniques for energy-efficient communication in wireless sensor networks.

In wireless communication systems, the placement of antennas or radios can play a significant role in mitigating obstacles [6]. However, it is important to note that in many situations, system designers have limited control over the building materials that signals must penetrate. Consequently, the parameters of transmit power, receive sensitivity, and antenna gain become the primary factors that designers can manipulate to optimize system performance. By carefully selecting and tuning these parameters, designers can effectively overcome the challenges posed by various transmitting environments, enabling them to achieve optimal signal transmission and reception.

In environments where communication robustness is a primary concern, the selection of a radio receiver architecture that incorporates a low-noise amplifier (LNA) becomes crucial. Integrating an LNA into the receiver architecture allows system designers to set performance expectations early in the design phase. The LNA plays a critical role in enhancing the overall system sensitivity and improving the signal-to-noise ratio, enabling reliable reception even in challenging environments. By carefully considering and integrating an LNA in the receiver design, system designers can proactively address and minimize the impact of noise, interference, and weak signals, ultimately ensuring the desired level of performance and robustness in wireless communication systems [7].

Amplifier applications often necessitate the optimization of various performance factors, such as minimum noise, maximum gain, maximum power output, impedance matching, stability under varying loads, wide bandwidth, and the ability to cascade with other circuits [8]. In the realm of radio receiver systems, the LNA plays a crucial role, as it is widely employed to amplify weak signals across high-frequency applications. These applications span a range of fields, including optical communication, multi-mode transceivers, and measuring instruments. However, it is important to realize that LNAs faces certain limitations when subjected to high-performance conditions. Maintaining essential characteristics, such as input–output matching, minimal power consumption, low noise figure, and linearity, can prove challenging for typical LNAs.

A design proposal for an LNA has been developed, which has the potential to overcome these limitations and significantly improve performance. This design is notable, in that it eliminates the exclusive use of lumped DC-blocking capacitors and incorporates microstrips to improve stability and matching performance. By employing these improved techniques, the proposed LNA exhibits enhanced characteristics and addresses some of the drawbacks typically associated with previous LNAs, ensuring better overall performance in challenging low-noise amplifier applications [9].

This article presents a comprehensive study on the design of an LNA adapted for the front end of a wake-up receiver system. Theoretical foundations, design specifications, and requirements are explored to ensure optimal performance and energy efficiency. The proposed LNA design is rigorously simulated to validate its functionality and performance. The printed circuit board (PCB) hardware design, along with practical implementation and measurement results, further demonstrates the effectiveness of the proposed approach. S-parameter simulations and measured results are compared to assess the actual LNA performance against the theoretical predictions, providing valuable insights into its real-world capabilities. This study establishes a foundation for improved wake-up receiver (WuRx) systems that offers improved sensitivity and reliable wake-up functionality in power-constrained applications.

2. Theoretical Background and State of Research on LNA Design for Wake-Up Receiver Front-End

The interaction of electromagnetic waves in the air often results in considerable noise, posing a major obstacle to effective signal reception. To mitigate this issue, LNA is essential, as it boosts the weak incoming signal while adding as little distortion as possible to the receiver input [10]. Nevertheless, it must be recognized that the LNA also amplifies any existing noise at its input, highlighting the importance of minimizing all sources of additional noise to preserve signal integrity. To optimize power consumption and minimize network idle listening, duty-cycling nodes employ a technique where they periodically alternate between turning on and off their internal radios. However, this approach introduces certain limitations. In a duty cycling regulated system, a node can only “wake up” at predetermined intervals, which results in increased system latency. Additionally, nodes must continuously execute a procedure to ensure that the radio initializes at the designated time interval, leading to higher “sleep” current consumption [11].

To address these challenges, the deployment of an on-demand wake-up radio (Wur) for long-range nodes can significantly mitigate both energy consumption and delay. Nodes can be selectively activated as needed to reduce overall idle power consumption by integrating a WuRx with the main node. This approach enables more efficient energy usage and significantly lowers system latency, thereby enhancing the performance of duty-cycling-based wireless networks.

In the front end of the WuRx, the LNA is strategically positioned after a bandpass filter. This placement serves two primary purposes. First, it enhances the selectivity of the reception by allowing only signals within the desired frequency range to pass through while suppressing parasitic signals outside the desired frequency [12]. This improves the overall performance and accuracy of the system by reducing interference from unwanted signals. Figure 1 illustrates the placement of the LNA in the front-end antenna, highlighting its critical role in signal reception and noise suppression. The primary function of the LNA is to amplify the amplitude of the incoming weak signal in preparation for further processing by the subsequent blocks. The amplified signal is then fed into the envelope detector (ED), which extracts the envelope or magnitude of the signal. The remaining blocks of the receiver can then utilize this processed signal. To ensure reliable data transmission, it is crucial to have a high-performance LNA that exhibits characteristics such as low noise figure, high gain, and excellent input–output matching. This enables the LNA to amplify the weak signal accurately and reliably, maintaining signal integrity and minimizing distortion. The reliability of the data transmission greatly depends on the quality and performance of the LNA, as it serves as a critical component in the receiver chain.

In the literature, LNA finds extensive application in various fields [13]. In addition to the well-documented applications of LNAs in IoT and wireless sensor networks, significant advancements have also been made in the medical field, where high-performance LNAs plays a critical role in improving diagnostic accuracy and signal fidelity.

For instance, in 100 MHz ultrasound imaging systems, LNAs are essential for amplifying weak echo signals without introducing significant noise, especially when employing coded excitations to enhance signal-to-noise ratios and penetration depth [14]. Moreover, dual-frequency intravascular ultrasound (IVUS) systems, used for the high-resolution imaging of arterial walls, rely on broadband LNAs that can effectively handle signals in both low- and high-frequency bands to enable simultaneous structural and functional imaging [15]. LNAs are also critical in WuRx used in indoor localization systems, where energy efficiency and sensitivity are paramount for accurate positioning and extended battery life in wireless sensor networks [16]. These applications demand LNAs with ultra-low noise figures, wide bandwidths, and high linearity, demonstrating the importance of the continued research and optimization of LNA designs across domains.

The performance of an LNA depends on several key parameters, including the choice of transistors, the number of cascaded stages, and the matching circuit, which play a significant role in determining the type of LNA design. Other important factors that impact the performance of LNAs include the operating frequency, gain, power consumption, settling time, and noise figure. These parameters need to be carefully considered and optimized to achieve the desired performance and reliability in a specific application.

The

Table 1. Comparative overview of low-noise amplifier designs with microstrip line matching networks.

Reference	Frequency Band (GHz)	Topology	Matching Network	Gain (dB)	Noise Figure (dB)	Power (mW)	Notable Features
[17]	2.4–2.5	Two-stage	Microstrip with single stub	∼22	7.548	18	Stub matching minimizes parasitic effects.
[18]	1.9–2.8	Single stage	CRLH-TLR * + SRR ***	15.28	1.51	21	Broadband design with composite microstrip structures.
[19]	L-band	Single stage	Lumped + Microstrip	NA **	0.35	25	simulation layout using lumped and distributed elements.
[20]	3.0	Single stage	Microstrip	13.32	NA	20	Theoretical + CAD modeling for S-band operation.
[21]	0.8–2.7	Single stage	Microstrip	15	3.85	12	compact microstrip bandpass filter integrated with an LNA.

* CRLH-TLR: composite right/left-handed transmission line resonators. *** SRR: Split ring resonator. ** NA: Not Available.

presents a comparative overview of the state-of-the-art of LNA designs using microstrip-based matching networks, each exhibiting trade-offs in performance. Maruddani et al. [17] utilize a two-stage design with single-stub microstrip matching to achieve high gain (22 dB) but at the cost of a high noise figure (7.55 dB) and elevated power consumption (18 mW). El Hardouzi et al. [18] implement a modern, metamaterial-inspired architecture with CRLH transmission lines and split-ring resonators (SRRs), offering a low noise figure (1.51 dB) and broadband operation (1.9–2.8 GHz), though it still consumes 21 mW, indicating substantial power draw. Similarly, Zhang et al. [19] report an impressive noise figure of 0.35 dB using a hybrid of lumped and microstrip components but with the highest power consumption in the table (25 mW) and no gain reported. Rahimian et al. [20] apply a classical microstrip approach targeting 3 GHz with moderate gain (13.32 dB) and 20 mW power use, reflecting older design priorities. In contrast, Chavana et al. [21] integrate a compact microstrip bandpass filter and achieve a more efficient design at 12 mW, making it the lowest power consumer in the comparison. Overall, while recent designs enhance bandwidth and noise performance using advanced techniques, most still suffer from relatively high power consumption, limiting their suitability for ultra-low-power or battery-operated applications.

In the proposed design, the focus is on achieving the lowest possible power consumption while maintaining high sensitivity, an essential requirement for energy-constrained IoT applications. This involves carefully balancing trade-offs, such as selecting a transistor that provides high voltage gain with minimal current draw. Unlike many state of the art (SoA) LNAs that remain at the simulation level, our design represents a practical hardware solution that is well-suited for real-world implementation. By leveraging a tailored impedance matching strategy, an appropriate transistor selection, and a specific topology optimized for sub-GHz operation, the proposed LNA achieves competitive gain and noise performance while maintaining ultra-low power consumption. This makes it a compelling option for always-on wake-up receivers in compact, battery-powered wireless sensor nodes, where both energy efficiency and RF performance are critical.

3. Target Specifications and Design Requirements for Low-Noise Amplifier Implementation

In the design procedure of an LNA, it is crucial to consider several underlying principles that form a fundamental understanding. These principles aid in achieving optimal LNA performance. Some of these principles include parameters of scattering, the noise factor, reflection, and impedance transformation.

3.1. Transistor Selection Criteria for Low-Noise Amplifier Design

Selecting the appropriate transistor technology for an LNA depends on various factors, including the target frequency of operation, required gain, noise figure, required voltage, current, simplicity of implementation, and cost. Designers need to strike a balance between these factors to achieve the best performance for a specific application. Overall, the choice of the transistor type and technology is critical in designing a high-performance LNA to enhance the sensitivity and overall performance of the radio receiver.

In the context of wake-up receiver (WuRx) applications, the design often prioritizes low power consumption, simplicity, and cost effectiveness—factors that make the use of commercial off-the-shelf (COTS) components particularly attractive. Among the available transistor types, NPN and PNP bipolar junction transistors bipolar junction transistors (BJTs) stand out as viable candidates for LNA implementation due to their low noise performance and consistent behavior across various radio frequency bands. Their ability to provide sufficient gain at the input stage effectively reduces the noise contribution of subsequent receiver blocks, thereby improving the overall signal-to-noise ratio signal-to-noise ratio (SNR).

Compared to other LNA technologies used in WuRx systems—such as Metal–Oxide–Semiconductor Field-Effect Transistors (MOSFETs)-based designs, which offer lower power dissipation, or GaAs HEMT and SiGe heterojunction bipolar transistor (HBT) solutions, which are optimized for ultra-high frequency performance—BJT-based LNAs strike a practical balance between performance and accessibility. While HEMT and HBT devices may offer superior noise figures and high-frequency gains, they typically involve higher costs, require custom fabrication processes, and are less readily available as COTS components. Conversely, BJTs are widely available, affordable, and well-supported by the existing design tools and literature, making them particularly suited for prototyping and deployment in cost-sensitive WuRx applications.

In summary, the use of BJTs in LNAs for WuRx front-ends is especially compelling when leveraging COTS components, offering a favorable trade-off between noise performance, availability, and ease of integration, thereby supporting efficient and scalable wake-up receiver designs.

3.2. Gain Metrics in RF Front-End Design: Implications for WuRx Sensitivity

In RF front-end design, one of the most critical challenges is the amplification of weak signals received at the antenna without degrading their quality. To accomplish this, the LNA) is employed as the first active component in the signal chain, ensuring that the signal is amplified with minimal additional noise. This is particularly important in wake-up receiver (WuRx) systems, where signal levels are extremely low and sensitivity is a key performance metric. Gain, a fundamental parameter of the LNA, reflects its ability to increase signal strength, and accurate power gain calculation depends on source and load impedances. More practical measures are often used in decibels, such as the power gain presented in Equation (1):

$$G_{\mathrm{dB}}=10{log}_{10}\left({\displaystyle \frac{P_{\mathrm{out}}}{P_{\mathrm{in}}}}\right)$$

(1)

The available power gain is the ratio of the maximum available average power at the load to the maximum available average power from the source, presented in Equation (2):

$$G_A={\displaystyle \frac{\left(P_{source}\right)}{\left(P_{available}\right)}}$$

(2)

In summary, the LNA gain characteristics are essential in wake-up receivers, where enhancing weak input signals while preserving a low noise profile directly impacts the receiver sensitivity and overall system efficiency.

3.3. Stability Considerations in LNA Circuit Design

RF circuit stability is most conveniently evaluated at individual frequencies, based on small-signal two-port S-parameters. Such an approach is sufficient only for linear, small-signal circuit applications. Oscillation can occur when any load and source termination induces a negative real component of the input and output impedance. This scenario has three major causes: internal feedback, external feedback, and excessive out-of-band frequency gain.

The effects of the stability improvements can also be analyzed by comparing the stability factor, or K-factor, of the transistor with and without the stability improvements. The K-factor is calculated with the formula below in Equations (3) and (4):

$$K={\displaystyle \frac{1-{\left|S_{11}\right|}^2-{\left|S_{22}\right|}^2+{\left|\Delta \right|}^2}{2\left|S_{12}{S}_{21}\right|}}$$

(3)

$$\Delta =S_{11}{S}_{22}-S_{12}{S}_{21}$$

(4)

If K is less than one, then the transistor design is potentially unstable, dependent on the impedance of the source and load-matching networks. If the design is stable with a K value of less than one, then it is defined as conditionally stable. When $K>1$ and $\left|\Delta \right|<1$, the LNA is said to be unconditionally stable, it means the design could theoretically use any source and load-matching networks and still be stable. The magnitude of K corresponds to how much of the stability circle’s unstable region is occupied by the Smith chart. The $\mu$-factor is very useful to compare the relative stability of devices and is presented in Equation (5):

$$\mu 1={\displaystyle \frac{1-{\left|S_{22}\right|}^2}{\left|S_{11}-\Delta \left(S_{22}\right)\right|+\left|S_{21}{S}_{12}\right|}}$$

(5)

The $\mu$-factor also makes it easy to compare the stability of different transistors. For example, if we have five devices with known S-parameters, we simply compute the $\mu$-factor of each and rank devices in the order of their $\mu$-factors. The transistor with the highest $\mu$-factor is the most stable one.

3.4. Circuit Noise Figure

The fundamental noise performance parameter is the noise factor (F), which is defined as the ratio of the total output noise power to the output noise due to the input source. If the noise factor is expressed in decibels, it is called the noise figure (NF) presented in Equation (6):

$$NF=10log\left(F\right)$$

(6)

The noise factor is equivalent to the ratio of the SNR at the input and that at the output of the LNA presented in Equation (7):

$$F={\displaystyle \frac{\left(SN{R}_{in}\right)}{\left(SN{R}_{out}\right)}}$$

(7)

Another related and often talked about parameter in RF applications is the SNR, which is the ratio of the signal power and the noise power presented in Equation (8):

$$SNR={\displaystyle \frac{\left(P_{signal}\right)}{\left(P_{noise}\right)}}$$

(8)

3.5. Optimizing Gain and Noise Through Bilateral Matching in LNAs

In LNA design, the use of a bilateral approach is critical for accurately modeling and optimizing the amplifier’s behavior. Unlike the unilateral assumption, where the reverse transmission coefficient $S_{12}$ is considered negligible, the bilateral model fully accounts for feedback between the input and output, which significantly affects the input matching, gain, and noise performance [22]. This interdependence becomes especially important at high frequencies or in technologies where $S_{12}$ is not small, as ignoring it can lead to suboptimal or unstable designs [23]. Consequently, before initiating the design of the matching network, it is essential to determine the source and load impedances $Z_{source}$ and $Z_{load}$, respectively. In bilateral design, the matching conditions at the input and output, characterized by ${\Gamma }_{MS}$ (matching source) and ${\Gamma }_{ML}$ (matching load), are not independent but mutually influence each other through the device’s scattering parameters. Design typically begins from the input side, evaluating whether the device can achieve the desired gain while maintaining a low noise figure. This is often visualized by plotting constant noise and gain circles on the Smith chart to investigate trade-offs between performance metrics [24]. Once an appropriate source reflection coefficient ${\Gamma }_S$ is selected, an input-matching network is designed to present this impedance to the device. The resulting output reflection coefficient, taking into account the influence of ${\Gamma }_S$ through feedback, is calculated using Equation (9):

$${\Gamma }_{out}=S_{22}+{\displaystyle \frac{S_{21}{S}_{12}{\Gamma }_s}{1-S_{11}{\Gamma }_s}}$$

(9)

Following this, an output-matching network is created to transform the system load into the complex conjugate of ${\Gamma }_{out}$, a necessary condition to achieve maximum available gain. Finally, the transistor is placed between the two matched terminations, ${\Gamma }_S$ and ${\Gamma }_L$, enabling the LNA to deliver the intended gain performance with a perfectly matched output port. Amplifiers designed using this bilateral, gain-optimized method often feature a matched output and a potentially compromised input match, depending on the noise and gain trade-offs prioritized during design.

3.6. Impedance Matching Techniques and Trade-Offs in Low Noise Amplifier Design

After selecting a suitable transistor or gain block for a given RF design, it becomes essential to implement an efficient impedance matching network. To achieve maximum power transfer, the load impedance must be matched to the source impedance. This is typically accomplished by inserting passive components, such as inductors and capacitors, between the source and load. These configurations are known as matching networks. In RF circuit design, matching networks not only ensure optimal power transfer but also help minimize noise, improve linearity across the frequency band, and enhance power-handling capabilities. In essence, a matching network performs an impedance transformation to convert a given impedance into a more suitable value for the desired operation.

Common matching network topologies include L-section, T-section, and Pi-section configurations, each composed of two or three passive elements arranged in specific ways. Tools like the Smith chart are often used to simplify the initial design of these networks. However, real-world factors, such as environmental signal interference and parasitic effects, can degrade the performance of the network, making practical implementation more challenging than theoretical design.

In addition to lumped-element networks, transmission line structures such as microstrip lines are increasingly used in modern RF designs, especially at higher frequencies. Microstrip-based matching networks offer advantages in terms of compactness, low parasitic effects, and better integration with PCB. They allow for controlled impedance and can be precisely modeled and fabricated, making them ideal for implementing high-frequency matching solutions in compact, low-power RF systems [25].

Striplines and microstrips are types of PCB transmission lines in a circuit board layout. It is quick and low cost to manufacture and easily integrated with passive and active devices [26]. The geometry of the microstrip line is shown in Figure 2, where W is the width of the line, d is the thickness of the dielectric, and ${ϵ}_r$ is the relative permittivity of the dielectric.

Microstrip and stripline traces in RF designs are capable of carrying signals across a wide frequency range, from DC to high-speed RF. A fundamental step in their design is determining whether a specific characteristic impedance is required. In most single-ended RF applications, including the proposed design, a target impedance of 50 $\Omega$ is typical. Achieving this involves calculating the appropriate trace width based on the PCB stack-up and dielectric properties to ensure consistent impedance along the transmission path.

For wideband LNA designs, precise impedance matching is essential. At higher frequencies, the parasitic effects of discrete lumped components can compromise performance, making them less suitable on their own. As a result, distributed matching techniques offer a more effective alternative for achieving wideband impedance transformation.

Some stub and microstrip structures are shown in the first column of Figure 3. The second column shows the open-wire equivalent circuit for these structures. The third column shows a lumped-element approximation, assuming the impedance transformers are $\lambda /4$ transformers [27].

A stub is a section of line positioned in parallel to the primary circuit. It is terminated either by a short circuit or by an open circuit. It can be placed at the end of the line (in parallel) with the load or at a certain distance from it. Two stubs in parallel can also allow an adaptation. The choice will be fixed according to the specifications of the total space requirement and the possible value of the characteristic impedances of the matching lines.

Short-circuited and open-circuited stubs are fundamental elements in RF matching networks, allowing designers to implement reactive components using transmission lines instead of discrete inductors or capacitors. The electrical behavior of these stubs depends on their physical length relative to the signal wavelength. A short-circuited stub can emulate either inductive or capacitive behavior based on whether its electrical length causes the current to lead or lag the voltage. Similarly, an open-circuited stub also alternates between capacitive and inductive behavior depending on its length. By carefully selecting the stub length and operating frequency, these structures can be tuned to match specific reactive characteristics. This flexibility makes them ideal for compact and integrable impedance-matching solutions in high-frequency PCB designs, particularly in low-power RF circuits such as LNAs.

4. The Proposed LNA Design and Simulation Results

The LNA specifications are derived from the stringent requirements of the radio front-end in our WuRx architecture. To ensure reliable performance in low-power, always-on applications, the LNA must provide high gain, excellent stability, and a low noise figure, all while operating under minimal power consumption. Additionally, low input and output return losses are essential to maximize signal transfer and minimize reflection. Achieving these targets involves navigating complex trade-offs—improving one parameter often comes at the expense of another. For WuRx designs, where energy efficiency and sensitivity are critical, the LNA must be carefully optimized to balance these constraints while maintaining robust and efficient RF performance.

4.1. Common Emitter Single-Stage Transistor-Based LNA Topology

Figure 4 displays the proposed schematic. The LNA is implemented based on a common emitter (CE) topology. The CE architecture offers a higher gain with a lower noise figure for a smaller bandwidth. The presented circuit is a high-frequency RF amplifier utilizing a BFP740 which is a Silicon Germanium Carbon (SiGe:C) NPN Heterojunction wideband Bipolar RF Transistor (HBT) from (Infineon Technologies AG, Neubiberg, Germany) configured in a common-emitter topology, designed for broadband or narrowband amplification. The input signal enters through RF port J1 and is AC-coupled via capacitor C1, which blocks DC while allowing RF to pass. The inductor L3 provides impedance transformation and acts as part of the input-matching network. Biasing is established through a voltage divider formed by resistors R2 and R3, setting the base voltage, while R1 delivers collector current via inductor L1, which serves as an RF choke to isolate the DC supply from RF signals. L2 further aids in output matching or resonance tuning.

The amplified signal is AC-coupled through capacitor C2, with resistor R4 assisting in output matching or stabilization. The microstrip sections following R4 include both series and shunt/parallel stubs, which form a distributed impedance matching network optimized for RF power transfer at port J2. Series stubs provide inductive impedance transformation, while shunt stubs introduce reactive compensation depending on their termination. An open-circuited stub behaves capacitively if it is shorter than a quarter-wavelength and becomes a parallel resonator at $\lambda /4$, whereas a short-circuited stub behaves inductively when short, and becomes a parallel open circuit at $\lambda /4$. These effects enable precise tuning and broadband matching. Ground integrity is enhanced by a wide microstrip under the transistor’s emitter, which minimizes parasitic inductance and ensures a low-impedance RF return path, critical for stability and performance at microwave frequencies. Further details and specifications of the circuit components are provided in

Table 2. Component and layout specifications for the BFP740-Based LNA designed for 868 MHz.

Element	Value/Description	Tolerance	Function/Selection Criteria
C1	47  nF	±5%	AC coupling (input): Blocks DC and passes RF. Chosen for stability, low Equivalent Series Resistance (ESR), and high-frequency performance.
C2	1 nF	±5%	AC coupling (output): Ensures DC isolation of output while passing RF; maintains low insertion loss.
L1	10 uH	±5%	RF choke: Provides DC bias to collector while isolating RF. Selected to have Self Resonant Frequency(SRF) > 868 MHz.
L2	10 uH	±5%	Output matching or resonance tuning: Optimized for S22 and gain flatness near 868 MHz.
L3	15–16 nH	±5%	Input matching: Forms part of the matching network to transform source impedance to optimal noise/gain impedance.
L4	5.6 nH	±5%	Input matching: Forms part of the matching network to transform source impedance to optimal noise/gain impedance.
R1	560 $\Omega$	±5%	Collector bias: Supplies collector current via L1. Low noise and tight tolerance ensure consistent DC bias.
R2	47 kΩ	±5%	Bias divider (upper leg): Together with R3, sets base voltage. Chosen for thermal stability.
R3	30 $\Omega$	±5%	Bias divider (lower leg): Determines base bias voltage along with R2. Ensures proper VBE.
R4	10 $\Omega$	±5%	Output stabilization: Provides broadband damping and helps prevent high-frequency oscillations.
Microstrip Matching Network	stubs ($\lambda /4$ at 868 MHz)	N/A	Series stubs (inductive) and shunt stubs (capacitive or resonant): Enable broadband impedance matching. Designed using ${\epsilon }_{\mathrm{eff}}\approx 2.75$ for FR-4 (${\epsilon }_r=4.5$).
Emitter Ground Plane	Wide copper pour under emitter	N/A	Ensures low-impedance RF return path and minimizes parasitic inductance. Vital for gain stability and noise figure at microwave frequencies.

.

4.2. Simulation Results

The design and simulation of LNA were carried out using Agilent Advanced Design System (ADS) version 2020 for circuit simulation and Altium Designer version 2021 for PCB layout. Component values were carefully tuned through iterative simulations to optimize performance and balance design trade-offs. ADS tools, including the BJT curve tracer, were used to determine the optimal bias point and evaluate power consumption. Scattering parameters (S-parameters), measured using a Vector Network Analyzer (VNA), are essential for characterizing the RF behavior of the circuit. These include $S_{11}$ (input reflection), $S_{21}$ (forward gain), $S_{12}$ (reverse isolation), and $S_{22}$ (output reflection), all of which are critical for ensuring impedance matching and overall low-noise amplifier performance. The entire design is divided into two steps: schematic-level design and layout-level design. The schematic-level design includes schematic capture, choosing a simulation type (DC, S-parameters, etc.), and evaluation of the simulation setup. Once the schematic is verified through simulation, the design of the PCB can be started.

4.2.1. Circuit Biasing and Stability Analysis

The design of the proposed LNA began with the characterization of the Infineon BFP740 transistor, chosen for its low noise, high gain, and low power operation. The target was an NF below 2 dB, a gain above 15 dB, and operation from a 3 V to 3.3 V supply with a current below 5 mA. The use of OOK modulation reduced linearity demands, eliminating the need for a high $O{P}_{1\mathrm{dB}}$ and enabling a lower quiescent current. The manufacturer’s S2P file, containing S-parameters and NF data, was imported into ADS to model and simulate the device accurately. Simulations established an optimal operating point at 3 mA and $V_{CE}$ of 3.3 V, providing a basis for matching network design. The magnitude plot of the BFP740’s S-parameters without matching is shown in Figure 5.

The initial phase of this transistor design involved implementing enhancements to ensure stability. This was aimed at enabling the transistor to achieve its peak bilateral transducer power gain while operating in a state of conditional stability. This enhancement was achieved by introducing resistors in the load segment. Numerous configurations were feasible, but the selected arrangement was the one that yielded a K value greater than 1 and the highest achievable gain. Figure 6 shows the stability factor plots after the stability improvements, where K = 2.061 and ${\mu }_1$ = 1.412.

The effects of the stability improvements can also be analyzed by comparing the stability factor, or K-factor, of the transistor with and without the stability improvements. If K is less than one, then the transistor design is potentially unstable, dependent on the impedance of the source and load-matching networks. If K is greater than one, the design theoretically possesses the flexibility to employ various source and load-matching networks while maintaining stability.

4.2.2. Impedance Matching Design Using Complex Reflection Coefficients with Smith Chart and Stub Tuning

ADS provides a comprehensive design guide that greatly facilitates the LNA design process by enabling the plotting of gain and noise circles on the Smith chart. These visual tools allow the designer to assess the trade-off between gain and NF, which is essential in achieving an optimized low-noise amplifier for wake-up receiver applications. By analyzing these circles, the tool helps identify the ideal source and load reflection coefficients ${\Gamma }_S$ and ${\Gamma }_L$ that correspond to the desired performance targets.

As illustrated in Figure 7, the source impedance is fixed at 50 $\Omega$, which is the standard characteristic impedance of most RF systems and provides a well-matched interface with the preceding circuit stages. On the other hand, the load impedance is chosen to match the transistor’s optimal impedance ($Z_{\mathrm{opt}}$), which corresponds to the point that minimizes the noise figure (NF_min). This balance is crucial because maximum gain and minimum noise rarely occur at the same impedance point. Therefore, ${\Gamma }_S$ and ${\Gamma }_L$ are selected as a compromise, prioritizing noise reduction while maintaining acceptable gain levels.

These reflection coefficients are then used as targets in the matching network design, guiding the layout of microstrip or lumped-element networks to ensure the transistor operates under the specified impedance conditions.

In the first terminal, the impedance is fixed at 50 $\Omega$, which is the characteristic impedance at the source. In the other terminal, the optimal impedance ($Z_{\mathrm{opt}}$) is chosen for achieving the minimum noise figure (NF_min) as depicted in Figure 7.

The Smith chart tool is employed to design the input-matching network (IMN) as illustrated in Figure 8. A key challenge during this stage is selecting an appropriate implementation technology for the matching network. In this design, microstrip technology is chosen due to its favorable RF performance, which effectively minimizes oscillations and improves the $S_{11}$ and $S_{22}$ parameters, ensuring better matching at both the input and output ports.

To implement the desired impedance transformation, a combination of open-circuit stubs and shunt elements is used. These elements are carefully tuned to match the source impedance to the optimal input impedance of the transistor, thus maximizing the power transfer and minimizing signal reflection. At the output side, a similar approach is applied using the Smith chart to design the output-matching network (OMN), targeting the load impedance that ensures maximum gain while preserving stability.

The final IMN and OMN designs reflect a balanced trade-off between noise performance, gain, and return loss. Their layouts are realized using distributed microstrip structures, chosen for their low parasitics and ease of integration in PCB-based designs. This approach not only enhances RF performance but also aligns with the compact and low-power constraints typical of wake-up receiver systems.

4.2.3. Full-Circuit Simulation and Layout Validation

The transistor was biased with the exact current and voltage values previously extracted from the S2P file, using lumped components. A current divider network was implemented to deliver the required current accurately to both the collector load and the base. Input- and output-matching networks were incorporated into the schematic to ensure maximum power transfer. If any performance metric fell short of the design specifications, optimization with fine-tuning was performed at the schematic level to enhance the circuit behavior.Figure 9 presents the complete schematic of the LNA based on the BFP740 transistor, incorporating the lumped biasing network and impedance matching sections.

The complete LNA circuit, including all layout-defined elements, was simulated in ADS to estimate its performance prior to fabrication. This layout-aware simulation takes into account the geometrical structure of the transmission lines and component placements, providing a more accurate prediction compared to schematic-level simulation. While this approach reflects the physical arrangement of the circuit and offers insights into gain, noise figure, and impedance matching, it does not fully capture all real-world parasitic effects or electromagnetic interference that may arise in the fabricated PCB.

As shown in Figure 10, the simulation results confirm the effectiveness of the proposed design. The forward gain $S_{21}$ reaches $15.21$ dB, with input and output return losses of $S_{11}=-13.71$ dB and $S_{22}=-10.77$ dB, respectively, indicating solid impedance matching. The Rollett stability factor is $K=4.195$, which confirms unconditional stability across the frequency band. Moreover, the simulated noise figure is approximately $0.658$ dB, making the design highly suitable for low-noise, high-sensitivity wake-up receiver applications.

However, during real-world implementation, slight deviations from the simulated results may occur due to environmental factors such as electromagnetic interference, component tolerances, PCB substrate variability, and connector losses. These practical influences can cause frequency shifts or degrade matching and noise performance compared to the simulated expectations, underscoring the importance of careful layout design and post-fabrication validation.

5. Hardware Implementation and Real Measurement Results

The PCB design is a critical phase in the development of the LNA, as it directly affects circuit performance, signal integrity, and manufacturability. The process involves strict adherence to design specifications while accounting for fabrication constraints. It begins with an evaluation of the PCB manufacturer’s capabilities using tools such as ADS and Altium Designer to select a compatible stack-up and substrate, ensuring compliance with design rules.

5.1. Hardware Design and PCB Layout Design General Considerations

Key RF routing structures, including Microstrip-T-Junctions (MTEEs) and Transmission Lines (TLINs), are incorporated early to support accurate simulation and layout integration. As the design transitions from schematic to physical layout, symbolic components are replaced with pad-based footprints, and custom footprints are developed for critical parts such as RF transistors and SMA connectors. The final layout is completed with precise attention to trace routing, component placement, and ground plane design to meet both the electrical and fabrication requirements.

In high-frequency PCB design—particularly for low-noise applications—parameters such as trace width, controlled impedance, and routing topology are essential. The trace width must be selected to minimize crosstalk and ensure proper current handling, while controlled impedance is critical for high-frequency signals, defined by the PCB’s stack-up and target impedance. The routing topology must be optimized to reduce signal reflection and interference. For this design, FR-4 was used as the microstrip substrate with fixed parameters: a thickness of 1.6 mm, a relative dielectric constant (${\epsilon }_r=4.5$), copper thickness of 35 µm, and an operating frequency centered at 868 MHz, covering the sub-GHz band.

By carefully applying these considerations, the PCB layout was designed to ensure the reliable and efficient operation of the LNA, with robust signal performance at the intended frequency.

5.2. Measurement Setup and Performance Results

The transitional stage between simulation and emulation of the implemented PCB is typically hardware testing. Figure 11, for instance, depicts a single-stage installed stub LNA during the initial implementation phase.

Testing is required for the LNA design to make sure that each circuit component behaves adequately and meets the intended requirements. For small-signal S-parameter measurements, a Vector Network Analyzer (VNA) covering a frequency spectrum of (100 MHz to 1 GHz) was used. The designed circuits were probed using the SMA connector with 50 $\Omega$ impedance. One external DC source was used to correctly bias the circuits. The measurements were performed with different settings, and data were collected as CSV and S2P files for post-processing. The measured and simulated results reported here were obtained with a supply voltage of 3.3 V, and the current consumption was around 3.2 mA.

The S-parameter results were measured using an VNA as shown in Figure 11. The measurement findings are illustrated separately for better observation of the behavior beyond the large sub-GHz frequency band spectrum.

Figure 12 shows the $S_{21}$ results. At 868 MHz, $S_{21}$ = $15.2$ dB, reaching 20 dB at lower frequencies (400 MHz). The most important gain behavior is that it is greater than 15 dB for the whole frequency band, which easily enhances the implementation of the second stage at any required frequency point.

Figure 13 shows the results of input $S_{11}$ and output $S_{22}$ matching networks. At 868 MHz, S11 was about $-7$ dB, which is acceptable and had no impact on the performance of the other parameters. The envelope detector, which will be installed after the LNA in the WuRx design, can transfer a maximum amount of power due to the output port $S_{22}$ return loss of $-6.3$ dB.

Figure 14 shows the measurement stability behavior over the whole frequency band. The behavior of the designed LNA ensures good stability and no attention to oscillation during the integration to other WuRx Blocks or the implementation of the second-stage amplification.

5.3. S-Parameters Simulated and Measured Results Comparison

The significant difference between simulating and physically implementing RF PCB designs arises from the complexities of real-world conditions and limitations. While simulation provides a valuable tool for modeling and predicting performance, it often does not account for all the nuances of actual hardware. A comparison between the simulated and measured results is demonstrated in the following Figure 15.

Simulations are essential for early design stages and the understanding of general behavior, but later the RF PCB design process necessitates careful consideration of the real-world factors and limitations that can significantly influence the final performance of the hardware. The measured and simulated results of $S_{11}$, $S_{22}$, $S_{21}$, and $S_{12}$ for the designed LNA exhibit a significant level of agreement as summarized in

Table 3. Comparison between the aimed specification and the measured and simulated results.

Parameters	Specifications	Simulation	Measured Results
Vcc (V)	3.3	3.3	3.3
Icc (mA)	<5	3.2	3.2
Frequency Band (GHz)	0.1–1	0.1–1	0.1–1
Gain $S_{21}$ (dB)	>15	15.21	15.20
Input Port Reflection $S_{11}$ (dB)	<−10	−13.71	−6.9
Output Port Reflection $S_{22}$ (dB)	<−10	−10.77	−6.29
Reverse Isolation $S_{12}$ (dB)	<−20	<−32	<−28
Noise Figure (dB)	<2	0.65	1.77

, signifying the accuracy and reliability of the simulation model in predicting the LNA behavior. This comparability between the measured and simulated data is an encouraging validation of the design and simulation processes, instilling confidence in the functionality of the LNA.

The hardware specifications of the components used in the LNA, such as transistors, resistors, capacitors, and inductors, may deviate slightly from their idealized values due to manufacturing tolerances and variations. Such differences in component characteristics can lead to slight deviations between the simulated and measured results, especially at specific frequency points or critical regions where the circuit’s behavior is particularly sensitive to component variations.

The degradation from the simulated $S_{11}$/$S_{22}$ values (below −10 dB) to the measured results (−6.9 dB and −6.3 dB) can be attributed to several practical factors, including PCB parasitics, layout inaccuracies, connector losses, and component tolerances. Parasitic effects introduced by bias, trace transitions, and unmodeled solder joints can detune the impedance match. Inconsistencies between the simulated layout and fabricated PCB, along with variations in component placement and routing, can further contribute to performance degradation.

Additionally, environmental factors present during the lab tests can also influence the LNA performance. Temperature fluctuations, stray capacitance, electromagnetic interference, and other external influences can introduce subtle discrepancies between the simulated and measured data. While every effort is made to create controlled and stable testing conditions, it is challenging to completely eliminate all external factors that may impact the response of LNA during testing.

To address these issues in future iterations, we plan to employ EM/circuit co-simulation to more accurately capture layout parasitics. Additionally, we aim to use tighter-tolerance and high-Q components to enhance predictability and reduce losses. Careful design with controlled-impedance stackups will also be implemented to minimize mismatches. Furthermore, we intend to apply de-embedding techniques to better isolate the intrinsic performance of the circuit from measurement-related artifacts.

Despite these disparities, the overall agreement between the measured and simulated results reinforces the reliability of LNA and confirms that it fulfills its intended purpose as designed. The understanding of these differences, attributed to hardware and environmental factors, is crucial for further refining the performance of LNA and for optimizing its operation under real-world conditions.

Moving forward, additional iterations of testing and simulation, along with careful consideration of component tolerances and environmental effects, will enable us to fine-tune the performance of LNA and bridge the remaining gaps between the measured and simulated results. This continual improvement process will lead to a more robust and dependable system LNA, better suited to meet the demands of its intended application.

Compared to recent microstrip-based LNA designs, the proposed LNA stands out for its exceptionally low power consumption and competitive noise figure in the sub-GHz band compared to the literature. The gain performance is acceptable, especially considering that the design employs a single-stage topology. While a dual-stage implementation could potentially improve the overall gain, it must be carefully designed to avoid degrading the noise figure due to additive noise contributions from the second stage. The current design’s use of microstrip matching and low-voltage operation reinforces its suitability for energy-constrained applications such as wake-up radios and IoT sensors.

5.3.1. Performances of Gain with the Variation of Input Power

With a given supply voltage of 3.3 V, the gain characteristic with input power variation was investigated. Testing the sensitivity of the front end using a frequency generator as input enhances testing with extremely low input power. This validates that the gain is constant when the incoming power is changing. Moreover, the system’s stability and linearity within a reduced power range are determined by this measurement arrangement.

Investigating the amplifier’s linearity leads to conventionally analyzing its gain compression and intermodulation distortions against different signal input powers. Characterizing the former is essential in order to determine the input power where compression begins and distortions will occur. A 1 dB compression point, P1dB, is where the gain falls by 1 dB at a certain input power, Pin. Figure 16 shows the change of gain and output power Pout against Pin for LNA. A theoretical linear curve of the output power is meant to measure P1dB with reference to $P_{in}$.

To maintain a linear and undistorted response, the LNA must be operated at input power levels below the compression point. This ensures that the gain remains constant and linear across the desired frequency range, minimizing distortion and preserving signal fidelity.

Operating the LNA below the compression point is essential to avoid signal distortion. When the input signal exceeds this point, the LNA gain is no longer linear, and the output signal becomes distorted. Non-linear behavior leads to the generation of unwanted frequencies known as distortion products. These distortion products are spaced from the desired frequency and can interfere with nearby frequency channels, causing interference and signal degradation.

The input-referred compression point of the LNA is a critical parameter that defines the point at which the LNA gain starts to saturate, causing non-linear behavior in the output signal. In this case, the compression point is specified as $I{P}_{1dB}$ = −23 dBm for the fundamental tone at 868 MHz.

An $I{P}_{1dB}$ of −23 dBm is significantly higher than typical signal levels in IoT environments. This suggests that under normal conditions, the LNA operates well within its linear region. However, simulations show that distortion begins at input powers above the −23 dBm $I{P}_{1dB}$ point, indicating early signs of non-linearity. In strong interference scenarios, such as near high-power transmitters, this non-linearity could distort the signal. Fortunately, in the tuned RF (TRF) architecture used here, the envelope detector (ED) follows the LNA and removes phase and frequency information, meaning that LNA-induced distortions do not compromise the OOK data integrity. Therefore, while the LNA linearity might limit performance under severe interference, it is unlikely to hinder wake-up signal detection in typical IoT settings. Additionally, placing a narrow-band filter before the LNA helps block strong out-of-band interferers, reducing the impact of LNA non-linearity. As a result, the linearity metrics like IP1dB and IP3 are less critical for wake-up signal detection and do not significantly limit the WuRx dynamic range.

5.3.2. Noise Measurement Analysis

In a typical noise measurement setup involving a calibrated noise source, the device under test (DUT)—such as an LNA or radio front-end—is characterized by measuring how much noise it adds to a known input signal. The noise source generates a broadband noise signal with a specified excess noise ratio (ENR), which is fed into the DUT through a coaxial RF connection. In this setup, the R&S®FS-SNS 18 noise source (Rohde & Schwarz GmbH & Co. KG, Munich, Germany) was used to ensure accurate and consistent noise generation. The DUT output is connected to a VNA equipped with noise figure analysis capabilities, enabling precise measurement of the output noise power across the desired frequency range as presented in Figure 17. Measurements are taken with the noise source switched “on” (hot) and “off” (cold), allowing the NF to be calculated using the Y-factor method. A bias tee is typically included to provide DC power to active devices without interrupting RF signal flow. To reduce measurement errors caused by reflections and electromagnetic interference, the entire setup was conducted inside a shielded environment cabinet. Additional components such as attenuators and calibration kits were used to ensure measurement accuracy and repeatability. This method enables precise evaluation of the noise contribution of the DUT, referenced to its input.

Around 868 MHz, the plot Figure 18 shows a relatively stable and moderate noise level of approximately 1.77 dB, indicating a low-noise environment suitable for wireless communication. Compared to the rising noise levels observed below 600 MHz and the slight fluctuations seen in higher frequencies, the 868 MHz region offers a favorable signal-to-noise ratio, which supports reliable data transmission.

The observed discrepancy between the simulated (0.65 dB) and measured (1.77 dB) noise figures can be attributed to several practical factors inherent to hardware implementation that are not fully captured in the simulation.

In simulation, typically only the active device, especially the transistor, is modeled with detailed noise parameters. Passive components like resistors, transmission lines, and connectors are either considered ideal or have simplified models that do not account for all real-world noise contributions.

However, in actual hardware measurements, the total noise figure includes not only the intrinsic noise of the transistor but also the cumulative effects of PCB layout parasitics (such as trace resistance and coupling), losses and thermal noise from passive components (resistors, inductors, and capacitors), noise introduced by connectors, solder joints, and interconnects, as well as external electromagnetic interference (EMI) and potential impedance mismatches or discontinuities. These additional sources collectively contribute to the higher measured noise figure.

The observed increase in noise figure between 600 MHz and 800 MHz, as shown in Figure 18, is primarily attributed to slight impedance mismatch and layout-related parasitic effects in the PCB. At these frequencies, even small discontinuities in the transmission lines or component placement can result in increased reflection losses, which degrade the noise performance.

Additionally, the noise contribution from passive components becomes more prominent in this band, particularly due to the frequency-dependent losses in inductors and capacitors. This effect is not fully captured in simulation models, which often assume ideal or simplified behavior for these components.

The measurement setup, including connectors and cables, may also introduce slight frequency-dependent variations that contribute to the noise figure jump. This behavior is consistent across multiple measurement runs, indicating that it stems from systematic implementation characteristics rather than random fluctuations.

Future design iterations will aim to minimize these effects through improved impedance matching and more careful PCB layout optimization.

6. Conclusions

This paper presented the design and optimization of an LNA intended for sub-GHz applications, with a particular focus on its future integration into WuRx systems for ultra-low-power wireless sensor networks. The proposed design addresses the key performance trade-offs between gain, noise figure, power consumption, impedance matching, and stability.

A common emitter topology using a silicon-based BJT (BFP740) was chosen for its high gain and favorable noise performance at low bias currents. The selection of this transistor technology was critical to achieving the target specifications, as it outperforms alternatives under similar power constraints in the 868 MHz frequency band. The impedance-matching networks were carefully developed using a combination of lumped components and microstrip lines, supported by Smith chart analysis and layout-aware simulations.

The final LNA design achieves a gain greater than 15 dB, a noise figure of approximately 1.77 dB, and demonstrates unconditional stability with a stability factor $K>1$. These results were obtained while operating at a current consumption of only $3.2$ $\mathrm{m}$$\mathrm{A}$ from a $3.3$ $\mathrm{V}$ supply. The design also includes considerations for real-world implementation, such as matching network layout and measurement validation in a shielded environment using professional RF instrumentation.

The proposed LNA is highly suitable for WuRx integration due to its low-power design, fast start-up, and strong noise performance, which are crucial for energy-efficient and responsive wake-up systems. When incorporated, a dual-stage of the proposed LNA reaching more than 30 dB gain and a power consumption around 6.4 mA, into our WuRx architecture, it contributes to a significant improvement in sensitivity and responsiveness while maintaining a low-power footprint. During the active phase, the total current consumption of the WuRx rises to 6400 mA; while in sleep mode, all components except the microcontroller are deactivated to conserve energy. By employing a duty-cycling approach with a peek time of 50 µs and a sleep time of 100 ms, the system achieves an average current consumption of just 4.14 µA, corresponding to an average power of 13.67 µW. Although the measured power is slightly higher due to occasional extensions of the peak period caused by interference, the overall design remains highly efficient. The low quiescent current and rapid wake-up capabilities of LNA make it ideal for such a duty-cycled WuRx system, allowing the receiver to stay in an always-on listening mode with minimal impact on the total wake-up power budget and without compromising the wake-up latency.

Although the current work focuses on standalone LNA performance, its characteristics position it well for future integration into duty-cycled WuRx systems. In such systems, especially in smart indoor environments where sub-GHz communication is common, low power consumption and high sensitivity are essential requirements. The proposed LNA demonstrates the potential to meet sensitivity levels down to $-70$ dBm, when it incorporates a dual-stage architecture into the WuRx, making it a strong candidate for next-generation, energy-autonomous wireless sensing platforms.

In summary, this work highlights the critical role of careful transistor selection, topology, and impedance matching in achieving high-performance, low-power RF front-end components. The results validate the proposed LNA as an efficient, compact, and noise-optimized solution ready for future integration into ultra-low-power wireless applications.