Search Results (104)

Indium oxide (In₂O₃) has recently emerged as a promising semiconductor for advanced electronics due to its high electron mobility and wide bandgap. In this article, the lateral scaling characteristics of top-gate In₂O₃ thin-film transistors (TFTs) featuring a 1.5 nm thick channel and a 7 nm thick HfO₂ gate dielectric are investigated by two-dimensional device simulation. The analysis covers short-channel effects, DC characteristics, transconductance behavior, and small-signal radio frequency (RF) metrics across a gate-length (L_G) range of 20 nm to 700 nm. Simulation results identify a critical gate length near 100 nm for the transition from long-channel to short-channel behavior. For L_G ≤ 100 nm, pronounced short-channel effects emerge, featuring a significant negative V_TH shift and a drain-induced barrier lowering (DIBL) coefficient up to ~130 mV/V. A non-classical gm scaling behavior is observed, where g_{m_max} initially increases with L_G, then remains within a narrow range and eventually evolves toward the conventional long-channel trend. Further analysis of the lateral electric field distribution, field-dependent mobility, and transconductance efficiency indicates that this behavior originates from a crossover between short-channel field-assisted transport and gate-controlled channel modulation. The devices show strong RF potential, with f_T and f_max reaching 124.32 GHz and 157.64 GHz, respectively, at L_G = 20 nm. The high-mobility In₂O₃ channel leads to a less distinct f_T scaling transition from the classical 1/L²_G dependence to the short-channel 1/L_G dependence, while f_max scaling evolves through different regimes governed by capacitance-related limitations, intrinsic transport enhancement, and short-channel non-idealities. This work provides physical insight into the lateral scaling behavior of ultrathin top-gate In₂O₃ TFTs and highlights their potential for high-frequency and power-dense applications. Full article

Reconfigurable logic is crucial for future adaptive computing, but is challenging to realize with conventional complementary metal-oxide-semiconductor technology due to the limited field-effect characteristics of the fundamental silicon devices. Two-dimensional materials offer a promising platform, yet enhancing their functional versatility requires novel operational mechanisms. Here, we demonstrate a single WSe₂/h-BN/graphene heterojunction capable of dynamically switching between distinct logic functions—XNOR and IMP (implication gate or “IF-THEN” gate)—simply by modulating the drain-source voltage. At a low bias of 0.3 V, the carrier distribution is governed by capacitive coupling, realizing an XNOR gate. Increasing the bias to 3 V activates Fowler–Nordheim tunneling between the graphene floating gate and the drain, enabling IMP logic operation. The interplay and voltage-induced transition between these two physical mechanisms underpin the device’s multifunctional capability. This work introduces a novel operational strategy for two-dimensional material-based reconfigurable logic, providing a pathway toward compact, adaptive hardware for post-CMOS computing. Full article

This study introduces an air gap gate with AlN passivation to enhance the radio frequency (RF) performance of AlGaN/GaN high-electron-mobility transistors (HEMTs) while addressing thermal challenges. The air gap gate improves RF performance by reducing gate capacitance, resulting in a 23.9% increase in cutoff frequency (35.82 GHz) and enhancing saturation drain current and maximum transconductance by 3.7% and 10.27%, respectively, compared to a 0.15 μm planar gate baseline. However, reduced heat dissipation degrades thermal performance, as reflected in higher thermal resistance and temperature gradients. Incorporating high thermal conductivity AlN passivation mitigates these drawbacks, lowering operating temperatures and improving heat distribution, while maintaining a 17.5% cutoff frequency improvement over the baseline. These results demonstrate that the air gap gate with AlN passivation provides an effective strategy for achieving reliable, high-performance AlGaN/GaN HEMTs under high-frequency and high-power operations. Full article

4H-SiC has been studied and applied in power semiconductor devices due to its wider band gap and higher thermal conductivity than those of Si and hence has great potential for power devices operating at high powers and high temperatures. The introduction of the superjunction (SJ) structure for the power MOSFETs enables further reduction in the ON resistance while maintaining the breakdown voltage. In this work, we examined the dc and ac performance of the 1.2 kV 4H-SiC SJ double-implanted MOSFET (DMOSFET) with different configurations of pillars by the Atlas device simulator. The simulation results suggest the step-shape SJ DMOSFET can further reduce the specific ON resistance and the gate-drain capacitance while maintaining the breakdown voltage compared with the optimized conventional SJ DMOSFET. In addition, that the multi-pillar SJ DMOSFET demonstrates better performance than that of the optimized conventional SJ DMOSFET was also verified in this work. Full article

A Q-enhanced notch filter for interference-rejection LNAs is proposed in this brief. The active capacitance is introduced into the notch filter to improve the quality factor by the negative resistance effect. The designed notch filter achieves excellent performance with a narrow attenuation bandwidth from 5.75 GHz to 5.95 GHz, which can be applied to suppress interference from the IEEE 802.11a. To validate the feasibility of the proposed trap filter in both GaAs process technology and principle, a 3–15 GHz ultra-wideband low-noise amplifier was designed and fabricated using a 0.15-micron gallium arsenide pseudomorphs field-effect transistor process. The frequency-dependent feedback loops are employed between gate and drain stages for wideband input matching and gain flatness. The notch filter is inserted between two stages of the LNA. The measurement results show that the interference-rejection LNA achieves a maximum gain of 24.5 dB and a minimum noise figure of 1.8 dB in the operating band. The notch filter has a maximum interference-rejection ratio of 35.2 dB at 5.8 GHz with almost no effect on the desired gain of the LNA. The LNA has a power consumption of 168 mW, including the notch filter with a size of 1.93 × 0.72 mm². Full article

This work investigates the impact of load-dump stress on p-GaN HEMTs under floating gate condition. The experiments show that preconditioning the device with a small load-dump stress (150 V, @t_d = 100 ms and t_r = 8 ms) enhances its robustness against a larger stress (190 V, @t_d = 100 ms and t_r = 8 ms). If a large load-dump stress (≥160 V, @t_d = 100 ms and t_r = 8 ms) is applied directly to the device’s drain, the device will burn out. This occurs because the rapidly changing drain voltage during a load-dump event can generate a capacitive coupling current, leading to transient positive charge accumulation in the gate region. Consequently, the channel under the gate is turned on, allowing a large current to flow through it. The coexistence of high current and high voltage leads to substantial Joule heating within the device, resulting in eventual burnout. When a small load-dump stress is initially applied, the resulting charging of electron traps in the gate region increases the threshold voltage. As a result, the device can withstand a larger load-dump stress before the channel turns on, which explains the device’s enhanced robustness. This work clarifies the failure threshold of p-GaN HEMTs under the load-dump stress, providing key support for improving the devices’ reliability in the practical applications. It can provide a basis for adding necessary protective measures in device circuit design, and clarify the triggering voltage threshold of protective measures to ensure that they can effectively avoid device damage due to the load-dump stress. Full article

A Gate Stack GAA FET using SiGe with a 2 nm gate underlap encapsulating a high-k spacer has been created, explored, and evaluated for improved performance in radio frequency applications. The chip shows significant improvements in electrical and radio frequency analog performance because of the use of wrapped underlaps of high-k, which suppress parasitic capacitance and fringing field effects, to achieve a 192.52% boost in drain current and 98% reduction in I_OFF current, translating into better performance. This new device, as proposed, has demonstrated improved switching behavior with the ability to reduce subthreshold swing by about 11.24% and results in a better Ion/Ioff ratio over existing devices, while also maintaining efficient control over other SCEs, with it being well-suited for the implementation of high-performance and low-power CMOS circuits. In addition, linearity parameters like VIP2, VIP3, and IIP3 reflect improvements, with the device having lesser harmonic distortions (IMD3 and THD), therefore making it more appropriate for RF and analog circuit uses. These results point to the prospect of SiGe-based Gate Stack GAA FETs with a 2 nm gate underlap encircling a high-k spacer for low-power, high-speed applications in IoT and 5G/6G technologies toward building environmentally friendly and sustainable electronic solutions. Full article

Wide-Bandgap (WBG) semiconductors—silicon carbide (SiC) and gallium nitride (GaN)— enable high-power-density conversion, but performance is limited by where heat is generated and how it is removed. This review links device-level loss mechanisms (conduction and switching, including output-capacitance hysteresis and dynamic on-resistance) to structure-driven hot spots within the ultra-thin (tens of nanometers) two-dimensional electron gas (2DEG) channel of GaN HEMTs and to thermal boundary resistance at layer interfaces. We compare wire-bondless package concepts—double-sided cooling, embedded packaging, and interleaved planar layouts—and survey system-level cooling that shortens the conduction path and raises heat-transfer coefficients. The impact on reliability is discussed using temperature-sensitive electrical parameters (e.g., on-state VDS, threshold voltage, drain leakage, di/dt, and gate current) for real-time junction-temperature estimation and compact electro-thermal RC models for remaining-useful-life prediction. Evidence from recent literature points to interface resistance in GaN-on-SiC as a primary bottleneck, while near-junction cooling and advanced packages are effective mitigations. We argue for integrated co-design—devices, packaging, electromagnetic interference (EMI)-aware layout, and cooling—together with interface engineering and health monitoring to deliver reliable, high-density WBG systems. Full article

Three-dimensional bulk fin-type field-effect transistors (FinFETs) have been the dominant devices since the sub-22 nm technology node. Electrical characteristics of scaled devices suffer from different process variation effects. Owing to the trapping and de-trapping of charge carriers, random interface traps (RITs) degrade device characteristics, and, to study this effect, this work investigates the impact of RITs on the DC/AC/RF characteristic fluctuations of FinFETs. Under high gate bias, the device screening effect suppresses large fluctuations induced by RITs. In relation to different densities of interface traps (D_it), fluctuations of short-channel effects, including potential barriers and current densities, are analyzed. Bulk FinFETs exhibit entirely different variability, despite having the same number of RITs. Potential barriers are significantly altered when devices with RITs are located near the source end. An analysis and a discussion of RIT-fluctuated gate capacitances, transconductances, cut-off, and 3-dB frequencies are provided. Under high D_it conditions, we observe ~146% variation in off-state current, ~26% in threshold voltage, and large fluctuations of ~107% and ~131% in gain and cut-off frequency, respectively. The effects of the random position of RITs on both AC and RF characteristic fluctuations are also discussed and designed in three different scenarios. Across all densities of interface traps, the device with RITs near the drain end exhibits relatively minimal fluctuations in gate capacitance, voltage gain, cut-off, and 3-dB frequencies. Full article

In this study, AlGaN/GaN heterostructure field-effect transistors (HFETs) with an AlN cap layer and a GaN cap layer were fabricated. The devices were of different sizes. Capacitance–voltage (C-V) and current–voltage (I-V) curves were measured. Based on two-dimensional (2D) scattering theory, electron mobility corresponding to polarization Coulomb field (PCF) scattering and other primary scattering mechanisms was quantitatively determined. The influence of the AlN cap layer on PCF scattering in AlGaN/GaN HFETs was studied. It was found that the AlN cap layer suppresses the inverse piezoelectric effect (IPE) in the AlGaN barrier layer because of its greater polarization and larger Young’s modulus, thereby reducing the generation of additional polarization charge (APC) under the gate. In addition, the 2D electron gas (2DEG) density (n_2DEG) under the gate of the samples with an AlN cap layer is higher. Both factors help reduce PCF scattering intensity. Moreover, mobility analysis of samples with different gate–drain spacings (L_GD) showed that PCF scattering is less affected by L_GD variations in devices with AlN cap layers. This study offers new insights into the structural optimization of AlGaN/GaN HFETs. Full article

This study examines the performance of a GaN HEMT with a 150 nm gate length, fabricated on silicon carbide, across various operational modes, including direct current (DC), radio frequency (RF), and small-signal parameters. The evaluation of DC, RF, and small-signal performance under diverse bias conditions remains a relatively unexplored area of study for this specific technology. The DC characteristics revealed relatively little I_ds at zero gate and drain voltages, and the current grew as V_gs increased. Essential measurements include I_dss at 109 mA and I_dssm at 26 mA, while the peak g_m was 62 mS. Because transconductance is sensitive to variations in V_gs and V_ds, it shows “Vth _roll-off,” where Vth decreases as V_ds increases. The transfer characteristics corroborated this trend, illustrating the impact of drain-induced barrier lowering (DIBL) on threshold voltage (Vth) values, which spanned from −5.06 V to −5.71 V across varying drain-source voltages (V_ds). The equivalent-circuit technique revealed substantial non-linear behaviors in capacitances such as C_gs and C_gd concerning V_gs and V_ds, while also identifying extrinsic factors including parasitic capacitances and resistances. Series resistances (R_gs and R_gd) decreased as V_gs increased, thereby enhancing device conductivity. As V_gs approached neutrality, particularly at elevated V_ds levels, the intrinsic transconductance (g_mo) and time constants (τ_gm, τ_gs, and τ_gd) exhibited enhanced performance. f_t and f_max, which are essential for high-frequency applications, rose with decreasing V_gs and increasing V_ds. When V_gs approached −3 V, the S₂₁ and Y₂₁ readings demonstrated improved signal transmission, with peak S₂₁ values of approximately 11.2 dB. The stability factor (K), which increased with V_ds, highlighted the device’s operational limits. The robust correlation between simulation and experimental data validated the equivalent-circuit model, which is essential for enhancing design and creating RF circuits. Further examination of bias conditions would enhance understanding of the device’s performance. Full article

In this study, we propose a bidirectional chemical sensor platform based on a reconfigurable ion-sensitive field-effect transistor (R-ISFET) architecture. The device incorporates Ni-silicide Schottky barrier source/drain (S/D) contacts, enabling ambipolar conduction and bidirectional turn-on behavior for both p-type and n-type configurations. Channel polarity is dynamically controlled via the program gate (PG), while the control gate (CG) suppresses leakage current, enhancing operational stability and energy efficiency. A dual-control-gate (DCG) structure enhances capacitive coupling, enabling sensitivity beyond the Nernst limit without external amplification. The extended-gate (EG) architecture physically separates the transistor and sensing regions, improving durability and long-term reliability. Electrical characteristics were evaluated through transfer and output curves, and carrier transport mechanisms were analyzed using band diagrams. Sensor performance—including sensitivity, hysteresis, and drift—was assessed under various pH conditions and external noise up to 5 V_pp (i.e., peak-to-peak voltage). The n-type configuration exhibited high mobility and fast response, while the p-type configuration demonstrated excellent noise immunity and low drift. Both modes showed consistent sensitivity trends, confirming the feasibility of complementary sensing. These results indicate that the proposed R-ISFET sensor enables selective mode switching for high sensitivity and robust operation, offering strong potential for next-generation biosensing and chemical detection. Full article

As transistor dimensions continue to scale below 10 nm, traditional MOSFET architectures face increasing limitations from short-channel effects, gate leakage, and variability. FinFETs, especially junctionless FinFETs on silicon-on-insulator (SOI) substrates, offer improved electrostatic control and simplified fabrication, making them attractive for deeply scaled nodes. In this work, we propose a novel Stepped-Spacer Structured FinFET (S³-FinFET) that incorporates a three-layer HfO₂/Si₃N₄/HfO₂ spacer configuration designed to enhance electrostatics and suppress parasitic effects. Using 2D TCAD simulations, the S³-FinFET is evaluated in terms of key performance metrics, including transfer/output characteristics, ON/OFF current ratio, subthreshold swing (SS), drain-induced barrier lowering (DIBL), gate capacitance, and cut-off frequency. The results show significant improvements in leakage control and high-frequency behavior. These enhancements make the S³-FinFET particularly well-suited for Field-Programmable Gate Arrays (FPGAs), where power efficiency, speed, and signal integrity are critical to performance in reconfigurable logic environments. Full article

In this study, a novel silicon carbide (SiC) double-trench MOSFET (DT-MOS) combined Schottky barrier diode (SBD) and MOS-channel diode (MCD) is proposed and investigated using TCAD simulations. The integrated MCD helps inactivate the parasitic body diode when the device is utilized as a freewheeling diode, eliminating bipolar degradation. The adjustment of SBD position provides an alternative path for reverse conduction and mitigates the electric field distribution near the bottom source trench region. As a result of the Schottky contact adjustment, the reverse conduction characteristics are less influenced by the source oxide thickness, and the breakdown voltage (BV) is largely improved from 800 V to 1069 V. The gate-to-drain capacitance is much lower due to the removal of the bottom oxide, bringing an improvement to the turn-on switching rise time from 2.58 ns to 0.68 ns. These optimized performances indicate the proposed structure with both SBD and MCD has advantages in switching and breakdown characteristics. Full article

A dual Al₂O₃ MIS gate structure is proposed to enhance the DC and RF performance of enhancement-mode GaN high-electron mobility transistors (HEMTs). As a result, the proposed MOS-HEMT with a dual recessed MIS gate structure offers 84% improvements in cutoff frequency (f_T) and 92% improvements in maximum oscillation frequency (f_max) compared to conventional HEMTs (from 7.1 GHz to 13.1 GHz and 17.5 GHz to 33.6 GHz, respectively). As for direct-current characteristics, a remarkable reduction in off-state gate leakage current and a 26% enhancement in the maximum saturation drain current (from 519 mA·mm⁻¹ to 658 A·mm⁻¹) are manifested in HEMTs with new structures. The maximum transconductance (g_m) is also raised from 209 mS·mm⁻¹ to 246 mS·mm⁻¹. Correspondingly, almost unchanged gate–source capacitance curves and gate–drain capacitance curves are also discussed to explain the electrical characteristic mechanism. These results indicate the superiority of using a dual Al₂O₃ MIS gate structure in GaN-based HEMTs to promote the RF and DC performance, providing a reference for further development in a miniwatt antenna amplifier and sub-6G frequencies of operation. Full article