Search Results (22)

A closed-loop transmission line (TL) coupled to an LCR resonator is used in this study for a fully-integrated CMOS rotary traveling wave oscillator (RTWO) based on the rotary traveling wave principle. A technique for the suppression of magnetic coupling noise is presented with eight-shaped inductors. The design and measurement of an 8.53 GHz oscillator in the TSMC 0.18 μm CMOS technology are discussed. The fully-integrated chip occupies a die area of 1.2 × 1.2 mm². The oscillator consists of four sub-oscillators and uses four 1:1 symmetric twisted transformers, with the secondary inductors connected to form a twisted closed-loop transmission line for coupling the sub-oscillators. The transformers are configured as eight-shaped structures to minimize the far-field magnetic field radiation from each transformer and the whole transformer. At a supply voltage of 1.7 V, the power consumption is 5.84 mW. The free-running oscillation frequency of the RTWO is tunable from 8.53 GHz to 10.0 GHz. The measured phase noise at a 1 MHz frequency offset is −122.4 dBc/Hz at an oscillation frequency of 8.53 GHz, and the figure of merit (FOM) of the proposed VCO with a specific inductor layout is −193.4 dBc/Hz, surpassing other similar RTWOs. The FOM with a tuning range (FOM_T) is −195.96 dBc/Hz. Full article

This paper presents a fully integrated bandpass filter (BPF) with high tunability based on a novel differential active inductor (DAI), designed for sensor interface circuits operating in the ultra-high frequency (UHF) band. The design of the proposed DAI is based on a symmetrical configuration, utilizing a differential amplifier for the feedforward transconductance and a common-source (CS) transistor for the feedback transconductance. By integrating a cascode scheme with a feedback resistor, the quality factor of the active inductor is significantly improved, leading to enhanced mid-band gain for the bandpass filter. To facilitate independent tuning of the BPF‘s center frequency and mid-band gain, an active resistor adjustment and bias voltage control are employed, providing precise control over the filter’s operational parameters. Post-layout simulations and process corner results are conducted with 0.13 µm CMOS technology at 1.2 V supply voltage. The proposed second order BPF achieves a broad tuning range of 280 MHz to 2.426 GHz, with a passband gain between 8.9 dB and 16.54 dB. The design demonstrates a maximum noise figure of 16.54 dB at 280 MHz, an input-referred 1 dB compression point of −3.78 dBm, and a third-order input intercept point (IIP3) of −0.897 dBm. Additionally, the BPF occupies an active area of only 68.2×30 µm², including impedance-matching part, and consumes a DC power of 14–20 mW. The compact size and low power consumption of the design make it highly suitable for integration into modern wireless sensor interfaces where performance and area efficiency are critical. Full article

Battery charging systems are crucial for energy storage in off-grid photovoltaic (PV) installations. Since the power generated by a PV panel is conditioned by climatic conditions and load characteristics, a maximum power point tracking (MPPT) technique is required to maximize PV power and accelerate battery charging. On the other hand, a battery must be carefully charged, ensuring that its charging current and voltage limits are not exceeded, thereby preventing premature degradation. However, the voltage generated by the PV panel during MPPT operation fluctuates, which can harm the battery, particularly during periods of intense radiation when overvoltages are likely to occur. To address these issues, the design and construction of an enhanced solar battery charger utilizing a single-ended primary-inductor converter (SEPIC) and soft computing (SC)-based control is presented. A control strategy is employed that integrates voltage stabilization and MPPT functions through two dedicated fuzzy logic controllers (FLCs), which manage battery charging using a three-mode scheme: MPPT, Absorption, and Float. This approach optimizes available PV power while guaranteeing fast and safe battery charging. The developed charger leverages the SEPIC’s notable features for PV applications, including a wide input voltage range, minimal input current ripple, and an easy-to-drive switch. Moreover, unlike most PV charger control strategies in the literature that combine improved traditional MPPT methods with classical proportional integral (PI)-based control loops, the proposed control adopts a fully SC-based strategy, effectively addressing common drawbacks of conventional methods, such as slowness and inaccuracy during sudden atmospheric fluctuations. Simulations in MATLAB/Simulink compared the FLCs’ performance with conventional methods (P&O, IncCond, and PID). Additionally, a low-power hardware prototype using an Arduino Due microcontroller was built to evaluate the battery charger’s behavior under real weather conditions. The simulated and experimental results both demonstrate the robustness and effectiveness of the solar charger. Full article

An extreme step-down ratio buck converter is proposed using a double step-down (DSD) buck converter architecture and a single time-based current mode PWM controller able to generate two non-overlapping control signal phases. Current sampling for two inductors is implemented with a multiplexer and a pair of VCOs only, which treats the two inductors as one inductor operating at double the frequency. This is achieved without the use of any large external passive components in the controller while remaining stable. The type-II time-based controller uses a VCO, a frequency difference phase adder (FDPA), and a phase detector, generating a control signal with fully integrated components with minimum area. FDPA for proportional control also significantly limits the signal delay of the high gain controller, allowing the use of time-based control technique at <10 MHz, which improves converter efficiency. The proposed time-based current mode controller DSD buck converter is simulated in 130 nm BCD technology operating at 1 MHz for 10 V to 1 V conversion. The simulated peak efficiency is 82.2% at 0.4 A, and recovers from a 1.8 A loading and unloading current step in 5.75 $\mathrm{\mu }$s and 9.9 $\mathrm{\mu }$s, respectively. Full article

Recent technological advances have renewed the research interest in current-source inverters (CSIs). Nonetheless, CSI research still falls behind its voltage-source counterpart with regards to topologies, modulation, and control. Acknowledging the above, this paper presents a novel single-phase five-level CSI topology. The proposed circuit utilises eight switches and two inductors for the generation of five distinct output levels while maintaining low output voltage THD and $dv/dt$. Furthermore, by offsetting the inductor currents from a binary 1:2 to a trinary 1:3 ratio, the proposed inverter can generate seven current levels at its output. The inverter offers built-in short-circuit protection and can boost a low input DC voltage to a higher peak AC output voltage. These merits, alongside an electrolytic-capacitor-free design, simple current balancing mechanism, and fault-tolerant characteristics, make it a promising candidate for PV module-integrated inverter (MII) systems. The current topology utilises two inductors but is fully functional with single-inductor operation. The paper provides a functional analysis of the inverter topology alongside the inverter switching states and corresponding conduction paths. A detailed analysis of the inductor current dynamics as well as a current-balancing algorithm for dual- and single-inductor operations are given. The theoretical analysis of the proposed circuit and its functional operation are verified using simulations and experimental results carried out on a laboratory prototype. Full article

This paper designs an L-band wide stopband bandpass filter by applying low-temperature cofired ceramic (LTCC) technology to the global positioning system (GPS) frequency band. Taking the Chebyshev filter as a prototype, an equivalent collector element (capacitive and inductor) structure is adopted to fully use the three-dimensional package structure of LTCC to reduce the filter size. The filter is integrated into an eight-layer LTCC dielectric, and the series–parallel connection of the collector elements in the resonance unit is utilized to produce out-of-band transmission zeros, while the input and output ports’ capacitance is adjusted to control the bandwidth. Harmonic suppression is achieved by cascading two new compact stopband filters, while the size increase is insignificant due to LTCC technology. The simulation results are as follows: the center frequency is 1.575 GHz, 1 dB relative bandwidth is 6.3%, insertion loss in the passband is as slight as 1.6 dB, return loss is better than 30 dB, rejection bandwidth up to 16 GHz is more than 44 dB, and the volume of the whole filter is 6.2 × 3.7 × 0.78 $\mathrm{m}{\mathrm{m}}^3$. Full article

Three-dimensional (3D) integration based on through-silicon-via (TSV) technology provides a solution to the miniaturization of electronic systems. In this paper, novel integrated passive devices (IPDs) including capacitor, inductor, and bandpass filter are designed by employing TSV structures. For lower manufacturing costs, polyimide (PI) liners are used in the TSVs. The influences of structural parameters of TSVs on the electrical performance of the TSV-based capacitor and inductor are individually evaluated. Moreover, with the topologies of capacitor and inductor elements, a compact third-order Butterworth bandpass filter with a central frequency of 2.4 GHz is developed, and the footprint is only 0.814 mm × 0.444 mm. The simulated 3-dB bandwidth of the filter is 410 MHz, and the fraction bandwidth (FBW) is 17%. Besides, the in-band insertion loss is less than 2.63 dB, and the return loss in the passband is better than 11.4 dB, showing good RF performance. Furthermore, as the filter is fully formed by identical TSVs, it not only features a simple architecture and low cost, but also provides a promising idea for facilitating the system integration and layout camouflaging of radio frequency (RF) devices. Full article

In inductor applications, different soft magnetic materials are used depending on the frequency range. Owing to powder metallurgy technology and to the increase in the implementation of innovative multifunctional materials, it is possible to find an alternative to the traditional magnetic materials of the inductance application sector. This study concerns a deep analysis related to soft magnetic composite materials. The insulating layer’s effect is investigated to explore the applicability of such materials to the inductor sector. Four coatings systems are selected and two types of samples are prepared in the shape of a toroid and a rod, which are tested in different operating conditions. The rod inductors are also compared with a traditional one, based on soft ferrite materials. This work aims to integrate data coming from different measuring devices: the useful small-signal measurements of an RLC meter are completed by large-cycle data measured through a hysteresigraph. Different parameters are considered for the investigation: magnetic permeability (maximum and initial), iron losses at different induction peak values, and inductor quality factor are the most important. The obtained results prove that each analysis type is not fully reliable without the other in determining the coatings’ effects on the SMC inductors’ performance. In the end, it is demonstrated that SMC inductances can be successfully applied in a particular frequency range. Full article

Silicon technologies for HF applications have been proven for more than two decades, and technologies have greatly evolved. Whether CMOS or BiCMOS technologies, the unique combination of radio frequency, baseband, and digital functions allow a very high level of integration. While it is possible to achieve fully integrated transceivers, the major advantages of these silicon technologies lie mainly in their unparalleled performance in the field of frequency synthesis and frequency conversion. We propose in this paper a review of the major results obtained on these RF components since the beginning of the 2000s, also considering the impact of the technology node. The back-end of line (BEOL) process on which depends the quality of microwave monolithic integrated circuits (MMICs) is briefly presented in the introductory part. If circuit performances are tightly bound to the active devices (i.e., the heterojunction bipolar transistor SiGe HBT or CMOS transistor), passive elements (i.e., quality factor of inductors and varactors, losses of transmission, or interconnection lines) as well as the definition of the substrate also play a major role. The core of the article is oriented toward the noise of synthesized signals and frequency conversion. Frequency synthesis is presented through the analog design of a voltage-controlled oscillator (VCO) or through the direct digital frequency synthesis (DDFS), for which respective figures of merit are presented and discussed in a second section. The spectral purity of the oscillators being decisive in the definition of the throughput of a link is approached through the comparison of different figures of merit (FoM) for a set of circuits achievements over the selected period. If the realization of free oscillators is closely bound to the phase-locked loop (PLL)-type control loop for VCOs, the DDFS solution provides more direct and more flexible alternative at first sight. Therefore, these two solutions are analyzed collectively. Finally, the oscillator integrated in the transmitter or receiver supplies the needed LO (local oscillator) power to the frequency mixer in the frequency conversion module: henceforth, the third part of this study focuses on high-frequency mixer realizations. We thus consider this LO power in some advanced figure of merit mentioned in the second section. The design trade-off of the mixer is presented in an approach combining LO (conversion gain, channel isolation, and phase noise) and RF (HF noise figure and channel isolation) constraints. The final section provides a summary of the results and trends mentioned in the paper. Full article

This paper reviews state-of-the-art design approaches for low-voltage radio frequency (RF) and millimeter-wave (mm-wave) CMOS circuits. Effective design techniques at RF/mm-wave frequencies are described, including body biasing in fully depleted (FD) silicon-on-insulator (SOI) CMOS technologies and circuit topologies based on integrated reactive components (i.e., capacitors, inductors and transformers). The application of low-voltage design techniques is discussed for the main RF/mm-wave circuit blocks, i.e., low-noise amplifiers (LNAs), mixers and power amplifiers (PAs), highlighting the main design tradeoffs. Full article

In this paper, we analyze the effect of an enhanced voltage flip technique on the power performance of a piezoelectric energy harvester. The enhanced voltage flip principle is based on a synchronized-switch-based architecture, and is referred to as FAR (Full Active Rectifier). It uses a tiny amount of the stored charge to boost the voltage flip. This work aims to demonstrate that, beside the enhanced flip efficiency, the FAR also contributes to improve the power efficiency of the harvester, especially under changing load constraint. Therefore, the paper proposes a thorough comparison between the FAR and its conventional counterpart, the Switch-only technique. The FAR is easy to implement and does not require any external inductor or capacitor. It only needs a reduced set of switches, an active diode and a simple control sequence, and can thus be implemented on a fully integrated circuit. The FAR can be used as a standalone voltage flip solution or in addition to further boost the flip efficiency in a state-of-the-art architecture such as SSHC for example. Tests were performed on a 0.35-µm process CMOS prototype IC. Experimental results revealed that the FAR extracts $19.1\mathsf{\mu }W$ from an off-the-shelf piezoelectric transducer when the output voltage is regulated at $1$ V with $1$ V open-circuit voltage and delivers up to 20% more power than the conventional Switch-only technique under load constraint. It also shows over $11\times$ power efficiency improvement compared to a conventional diode-based full bridge rectifier. Full article

This paper reviews and discusses the state of the art of integrated switched-capacitor and integrated inductive power converters and provides a perspective on progress towards the realization of efficient and fully integrated DC–DC power conversion. A comparative assessment has been presented to review the salient features in the utilization of transistor technology between the switched-capacitor and switched inductor converter-based approaches. First, applications that drive the need for integrated switching power converters are introduced, and further implementation issues to be addressed also are discussed. Second, different control and modulation strategies applied to integrated switched-capacitor (voltage conversion ratio control, duty cycle control, switching frequency modulation, R_on modulation, and series low drop out) and inductive converters (pulse width modulation and pulse frequency modulation) are then discussed. Finally, a complete set of integrated power converters are related in terms of their conditions and operation metrics, thereby allowing a categorization to provide the suitability of converter technologies. Full article

This work presents a high efficiency RF-to-DC conversion circuit composed of an LC-CL balun-based Gm-boosting envelope detector, a low noise baseband amplifier, and an offset canceled latch comparator. It was designed to have high sensitivity with low power consumption for wake-up receiver (WuRx) applications. The proposed envelope detector is based on a fully integrated inductively degenerated common-source amplifier with a series gate inductor. The LC-CL balun circuit is merged with the core of the envelope detector by sharing the on-chip gate and source inductors. The proposed technique doubles the transconductance of the input transistor of the envelope detector without any extra power consumption because the gate and source voltage on the input transistor operates in a differential mode. This results in a higher RF-to-DC conversion gain. In order to improve the sensitivity of the wake-up radio, the DC offset of the latch comparator circuit is canceled by controlling the body bias voltage of a pair of differential input transistors through a binary-weighted current source cell. In addition, the hysteresis characteristic is implemented in order to avoid unstable operation by the large noise at the compared signal. The hysteresis window is programmable by changing the channel width of the latch transistor. The low noise baseband amplifier amplifies the output signal of the envelope detector and transfers it into the comparator circuit with low noise. For the 2.4 GHz WuRx, the proposed envelope detector with no external matching components shows the simulated conversion gain of about 16.79 V/V when the input power is around the sensitivity of −60 dBm, and this is 1.7 times higher than that of the conventional envelope detector with the same current and load. The proposed RF-to-DC conversion circuit (WuRx) achieves a sensitivity of about −65.4 dBm based on 45% to 55% duty, dissipating a power of 22 μW from a 1.2 V supply voltage. Full article

In this paper, a new topology for a high-power single-pole-double-throw (SPDT) antenna switch is presented, and its loss mechanisms are fully analyzed. The differential architecture is employed in the proposed switch implementation to prevent unwanted channel formations of OFF-state Rx switch transistors by relieving the voltage swing over the Rx switch devices. In addition to that, the load impedance seen by the Tx switch is stepped down to reduce the voltage swing even more, allowing the antenna switch to handle a high-power signal without distortions. To drop the switch operating impedance, two matching networks are required at the input and the output of the Tx switch, respectively, and they are carefully implemented considering the integration issue of the front-end circuitries. From the loss analysis of the whole signal path, an optimum switch operating impedance is decided in view of a trade-off between power handling capability and insertion loss of the antenna switch. The insertion loss of the proposed design is compared to the conventional design with electromagnetic (EM) simulated transformer and inductors. The proposed antenna switch is implemented in a standard 0.18 µm CMOS process, and all switch devices adopt the deep n-well structure. The measured performance of the proposed transmitter front-end chain shows a 1 dB compression point (P_1dB) of 32.1 dBm with 38.3% power-added efficiency (PAE) at 1.9 GHz. Full article

Inductor integration is of vital importance for miniaturization of power supply on chips. In this paper, a backside integrated power inductor is presented. The inductor is placed at the backside of a silicon interposer and connected to the front side metal layers by through-silicon vias (TSVs) for area saving and simple fabrication. An inductance model is proposed to effectively capture the total inductance of the power inductor by an analytical method. The results obtained from the analytical model and finite element method exhibit good agreement with various design parameters and the error between the proposed model and measurement remains less than 7.91%, which indicates that the proposed model can predict the inductance suitably. Full article