Voltage Flip Efﬁciency Enhancement for Piezo Energy Harvesting

: In this paper, we analyze the effect of an enhanced voltage ﬂip technique on the power performance of a piezoelectric energy harvester. The enhanced voltage ﬂip principle is based on a synchronized-switch-based architecture, and is referred to as FAR (Full Active Rectiﬁer). It uses a tiny amount of the stored charge to boost the voltage ﬂip. This work aims to demonstrate that, beside the enhanced ﬂip efﬁciency, the FAR also contributes to improve the power efﬁciency of the harvester, especially under changing load constraint. Therefore, the paper proposes a thorough comparison between the FAR and its conventional counterpart, the Switch-only technique. The FAR is easy to implement and does not require any external inductor or capacitor. It only needs a reduced set of switches, an active diode and a simple control sequence, and can thus be implemented on a fully integrated circuit. The FAR can be used as a standalone voltage ﬂip solution or in addition to further boost the ﬂip efﬁciency in a state-of-the-art architecture such as SSHC for example. Tests were performed on a 0.35-µm process CMOS prototype IC. Experimental results revealed that the FAR extracts 19.1 µ W from an off-the-shelf piezoelectric transducer when the output voltage is regulated at 1V with 1 V open-circuit voltage and delivers up to 20% more power than the conventional Switch-only technique under load constraint. It also shows over 11 × power efﬁciency improvement compared to a conventional diode-based full bridge rectiﬁer. performance of more a complex PEH architecture such as SSHI or SSHC. Experimental results performed on a CMOS prototype conﬁrmed that, under load constraint, the FAR principle achieved better performance compared to Switch-only, and is more robust against circuit non-idealities. These conclusive results opened interesting research perspectives that we are currently working on, consisting of combining the FAR principle with SSHI or SSHC to improve both voltage ﬂip and power efﬁciency.


Introduction
With the advent of IoT, the need for portable, and self-powered devices has been dramatically increasing. Batteries are still the most common way of powering embedded applications. Yet, due to their size, weight, impractical replacement, limited lifetime, and above all environmental impact, batteries tend to become unwelcomed in ultra-compact ultra-low power applications.
Harvesting energy from ambient background (solar, eolian, thermal, kinetic, etc.), has been a hot research topic over the last years. The goal is to do without batteries by implementing highly efficient dynamic power generators. In particular, the literature reports many implementations of kinetic harvesters involving piezoelectric devices Çiftci et al. [1], Chen et al. [2], Du and Seshia [3], Sanchez et al. [4], inductive devices Rahimi et al. [5], and electrostatic (capacitive) devices Tao et al. [6], Stanzione et al. [7].
Piezoelectric energy harvesters (PEH) are among the most investigated and popular kinetic energy harvesting systems, first because of the wide availability of ambient vibration sources, and second because they can achieve relatively high power density, i.e., from tens to several hundreds of microwatts per cubic centimeter, compared to the capacitive or inductive conversion principles. Moreover, they are easy to combine with conventional integrated circuit technologies Stanzione et al. [7]. Figure 1 shows the basic topology of a PEH system. It breaks down into three core parts: (1) A piezoelectric transducer (PT).  Thanks to the piezoelectric properties of its material, the PT turns the mechanical energy into electrical energy. The equivalent electrical model of the PT consists in the parallel combination of an AC current source, which provides the current I peh proportional to mechanical excitation, with an inherent piezoelectric capacitor C peh . The storage element can be a supercapacitor C L , and the load is usually modelled as a resistor R L . Note that R L may change dynamically according to the power requirements of loads such as sensors or wireless modules for instance. The main role of the interface circuit is to rectify the AC voltage of the PT, V peh , and provide the system with stable voltage supply. Ideally, the voltage supply should be independent of the load but in practice, a change in the value of R L can strongly affect the power efficiency of the harvester.
The most common interface circuit for rectifying V peh is a Full-Bridge Rectifier (FBR). Yet, the voltage drop across the rectifying diodes makes the FBR unsuitable for low-voltage PT (i.e., V peh in the 1 V range or below). In order to circumvent the diodes' threshold issue, Herbawi et al. [8] proposed the principle of active rectification that uses a negative voltage converter (NVC) combined to a series-connected active diode (AD) instead of the FBR Peters et al. [9]. The NVC acts like an FBR but uses transistors instead of diodes, thus yielding lower voltage drop across the rectifier. The AD prevents C L -to-PT current backflow.
Furthermore, the combination of the inherent capacitor C peh in parallel with I peh causes I peh and V peh to be normally in phase quadrature. This contributes to further dramatically hamper FBR efficiency because C peh needs to discharge and recharge at each zero-crossing moment of I peh . Numerous interface topologies and architectures have been proposed to improve power efficiency by applying nonlinear synchronous switching Richard et al. [10]. All these architectures use external devices, i.e.inductor and/or capacitor, to handle the charge of C peh . Synchronous Electric Charge Extraction (SECE) consists in extracting the energy accumulated in C peh by transferring it into an inductor, which in turn transfers it into the storage device Hehn et al. [11], Dini et al. [12], Shi et al. [13], Morel et al. [14,15]. SECE alleviates the load dependency of the system but requires a bulky inductor and tends to have degraded performance for periodic excitation of PT. Synchronized Switch Harvesting architectures reuse the own charge of C peh to invert the polarity of V peh upon I peh zero-crossing. They employ either an inductor (SSHI) (Sanchez et al. [4], Du et al. [16], Ramadass and Chandrakasan [17], Wu et al. [18], Chamanian et al. [19,20]) or a set of capacitors (SSHC) ( Chen et al. [2], Du and Seshia [3], Chen et al. [21], Hong et al. [22]) to store the charge of C peh temporarily before sending it back once the electrodes of the PT have been swapped. Architectures combining both an inductor and a capacitor have also been reported in Çiftci et al. [23] and Çiftci et al. [1]. Synchronized-switchbased architectures globally achieve better power efficiency than SECE for both shock and periodic excitation. According to Ramadass and Chandrakasan [17], full voltage flip of V peh could theoretically allow very high (i.e., infinite) efficiency. Yet, in practice the characteristics of the components strongly limit the voltage flip efficiency, and I peh still needs to provide C peh with complementary charge prior to transferring energy from the PT to C L and R L . Moreover, SSHC and SSHI architectures have load-dependent performance, which means that the power efficiency strongly depends on changes in R L and/or the excitation's amplitude. Çiftci et al. [1] proposed a circuit that reduces the load-dependency of the power efficiency. But such systems require more complex control.
Therefore, there is a genuine interest in proposing an easy-to-implement synchronized switch architecture that both achieves high-efficiency voltage flip and is able to maintain fair power efficiency during transient changes of the load R L . Enhancing the voltage flip minimizes the charge needed by C peh and thus allows to extract energy from the PT shortly after the voltage flip. This point is particularly critical in low-voltage systems, i.e., V peh ≤ 1 V, that harvest power in the tens of microwatts range.
In this paper, we demonstrate the benefit of a synchronized-switch-based architecture, referred to as full active rectifier (FAR) and first proposed in Wassouf et al. [24], to alleviate the load influence of the piezoelectric energy harvester. The FAR is based on the SSHC concept that consists in flipping V peh by means of a capacitor, but has much simpler control and needs no additional capacitors. In terms of power performance, the FAR is similar to the Switch-only principle Ramadass [25], and thus performs worse than state-of-the-art SSHI or SSHC. But it is important to note that, discussing raw absolute performance is not the point of this paper. The key result we propose here is the theoretical and experimental proof that thanks to the voltage flip enhancement, the FAR achieves better power efficiency under load constraint than Switch-only. It is yet also important to note that the proposed technique may be applied in addition to state-of-the-art voltage flip architectures that reuse the charge of C peh (i.e., SSHI and SSHC), and hence contribute to enhance their performance.
The paper is organized as follows: Section 2 presents the enhanced voltage flip concept, the FAR IC topology, its operation principle, and provides a thorough analysis of charge loss and power performance compared to Switch-only. Section 3 provides experimental results. Finally, Section 4 concludes this paper.

Enhanced Voltage Flip
The voltage flip enhancement technique that we propose consists in recharging C peh with C L . At first glance, the concept of reusing the stored charge may appear as counter intuitive but in this section, we demonstrate that it contributes to enhance the power efficiency of the harvester. At each zero-crossing instant of I peh , the piezo capacitor C peh is first shorted, and then immediately recharged with a fraction of the charge from the storage capacitor C L Wassouf et al. [24]. In the following sections, the proposed concept will be referred to as the FAR.
The concept is based on the use of a large storage capacitance C L , which should be at least one order of magnitude greater than C peh . This can easily be admitted because storage capacitances have usually large values. As discussed in Section 2.3, the concept also imperatively needs the rectified voltage V rec to be regulated, in order to ensure optimal power extraction of the proposed harvester.
For comparison purpose, because the FAR and the conventional Switch-only principle have a priori the same energy balance, we designed the FAR integrated circuit architecture presented below. This circuit allows to implement both FAR and Switch-only modes. Figure 2 presents the topology of the FAR IC. A set of switches (SW 0 to SW 3 ) consisting of transmission gates (TG) is connected to an active diode (AD) to form the rectifying part of the system. The logic control block (CB) of Figure 3 performs the switching sequence described below. The circuit also features a voltage regulator (VR) Du and Seshia [3], a ring oscillator (RO) Ferreira and Galup-Montoro [26], and switch drivers (SD). The later include a charge pump Tsuji et al. [27] and level shifters Du and Seshia [3], Matsuzuka et al. [28] that are needed to control the switches properly. Note that blocks VR, RO and SD are standard functions, which are largely documented in the state-of-the-art literature. Therefore, they are not further detailed in this paper.

FAR IC Topology
Full Active Rectifier (FAR) IC architecture Wassouf et al. [24]. The AD is used for both preventing the current from flowing back from C L and detecting the zero-crossing moment of I peh . It comprises a PMOS switch and an ultra-low power comparator proposed in Du and Seshia [3]. When the voltage at node V sp drops below the rectified output voltage V rec (Figure 2), the PMOS switch of AD is turned off, and the voltage flip operation is triggered as explained below.

FAR Operation Principle
The zero-crossing of I peh causes the AD's comparator output signal AD comp to go high. AD comp triggers the signal sequence generated by CB. The CB signals control in turn the AD and the switches SW 0 to SW 3 . Figure 3 shows the architecture of CB. Signal AD ctrl controls the PMOS switch of AD, signal Φ 0 controls SW 0 , signals Φ P and Φ N both control switches SW 1 and SW 2 , and signal Φ K controls SW 3 . Figure 4 shows the sequence and its effect on the PEH's voltages, while Table 1 shows the operating scheme of the switches according to the control signals. It is worth noticing that the voltage flip operation is triggered by signal AD ctrl and thus the control block auto-adapts according to the zero-crossing moment of I peh regardless of the PT's excitation frequency f ex .
The operation of the FAR breaks down into 3 phases.

Shorting Phase
Signal AD comp acts as the clock signal of a D flip-flop whose data input is set to a constant logic "high" state ( Figure 3). When AD comp goes high, a trigger signal TRIG turns on signals Φ P and Φ N simultaneously, which puts switches SW 1 and SW 2 in high impedance, i.e., off (Table 1). In the meantime, signal Φ 0 turns on SW 0 (Figure 4), which shorts C peh . Signal TRIG remains high until C peh is discharged. The duration of the shorting phase τ Φ 0 depends on the value of C peh and the resistance of SW 0 . The TGs used to implement the switches have very low ON-resistance, typically around 15 Ω. Assuming C peh = 100 nF, based on the off-the-shelf transducer characteristics (S118-J12S-1808YB, Piezo.com) used in the experiments (Section 3), the corresponding RC time constant is thus 1.5 µs. The duration τ Φ 0 is controlled by means of a counter (CNT in Figure 3) clocked by the RO signal OSC. This signal is initially used to clock the charge pump used in the switch drivers, and has a frequency of 125 kHz. Therefore, OSC allows controlling τ Φ 0 with 8 µs accuracy. In the proposed system, we used a modulo 4 counter, which thus yields τ Φ 0 = 32 µs. This duration is largely sufficient to ensure complete discharging of C peh .

Sharing Phase
Once TRIG is reset, i.e., TRIG goes high, a toggle sets either Φ P or Φ N to high depending on whether I peh is positive or negative, respectively. When Φ P is high, SW 1 is connected to node V sp and SW 2 is connected to ground, and inversely when Φ N is high (Table 1). In the meantime, Φ K goes high, which closes SW 3 and causes C L to share its charge with C peh . During this sharing phase, SW 3 is in series with either SW 1 or SW 2 . Since all switches are implemented with the same TGs, the RC time constant is thus 3 µs. Therefore, we also used a modulo 4 counter ( Figure 3) to set the duration of the sharing phase τ Φ K = 32 µs, which is also sufficient to complete the charge transfer.

Signal
Switch At the end of the sharing phase, the value of V peh across C peh is V built : V built only depends on the charge Q L stored in C L , the charge of C peh being Q peh = 0 after the shorting phase. If C L C peh , then |V built | = V rec V recmax , which is the value of V rec right before the voltage flip operation is triggered (see Figure 4). Note that, V built continuously increases as C L charges.

Power Extraction Phase
Once C peh is recharged, SW 3 turns off while either SW 1 or SW 2 remains on, depending on whether I peh is negative (Φ N high) or positive (Φ P high), respectively ( Figure 4). Since the terminals of the PT are swapped by SW 1 and SW 2 at each phase inversion of I peh , this procudes the rectifying of V peh (i.e., V sp = V peh ). In this phase, the AD's PMOS switch turns on as soon as V peh > V rec , which in turn connects the PT to C L . As a result, most of the charges transfer directly from PT to C L and R L .
Note that the PMOS switch turns on very shortly after the sharing phase, since the voltage at node V sp is V peh = |V built | = V rec as mentioned in Section 2.2.2. This has significant consequence on the power efficiency as discussed in Section 2.3.

Power Performance Analysis
If we suppose that I peh is a sine current source such as whereÎ peh represents the amplitude and f ex is the vibration frequency, then the expression of the open-circuit voltage V OC across the PT is given by: withV OC the open-circuit amplitude. When V OC (t) shifts from −V OC to +V OC , the total amount of charge generated by the PT in half a period is thus (Du and Seshia [3], Ramadass [25]): where ω = 2π f ex .

With Infinite R L
The total charge loss Q loss breaks down into two main contributions: Q 1 , lost by C L during the recharging of C peh (sharing phase) and Q 2 , the charge that goes to C peh during the power extraction phase, i.e., when C peh is in parallel with C L .
In steady state, when V rec reaches its maximum value V recmax (Figure 4) imposed by VR, the expressions for Q 1 and Q 2 are where ∆V represents the ripple of V rec caused by the recharging of C peh . The total charge loss is then From (1) and (5), we may consider ∆V ≈ 0 provided that C L C peh . Therefore, we can consider that C L fully recharges C peh , making Q 1 = V built · C peh the principal charge loss (i.e., Q 1 ≈ Q loss ). We can thus express the total charge stored on C L in half a period as and then the total charge on a full period is then 2Q L . Thus, the output power is given by From (9), we can deduce that the maximum power extraction is achieved when V rec =V OC , which corresponds to a maximum power This result shows that the power efficiency is inherently load-dependent because applying a finite value load R L affects V rec , as it would for any synchronized switch harvesting system ( Çiftci et al. [1], Chen et al. [21], Du et al. [29]) and suggests VR should regulate V rec toV OC (Ramadass and Chandrakasan [17]). Moreover, it is identical to Switchonly, the architecture and signals of which are presented in Figure 5.
When R L is infinite and V rec is regulated toV OC , the amount of charge needed to recharge either C L (FAR) or C peh (Switch-only) is Q peh/2. Yet, energy harvesting systems are meant to supply a finite value load with charges delivered by C L and PT. As demonstrated in the next section and in Section 3.2, the proposed FAR architecture has an impact on the power performance when R L has finite value. Furthermore, since FAR and Switch-only have the same power performance a priori, we compared both architectures.

With
Finite R L Figure 6 shows the equivalent electrical model of the PEH during the power extraction phase (i.e., AD is "ON"), when R L has a finite value. Note that this model assumes the series resistances of the switches and ADs are negligible, which is realistic considering R L is around several tens of kilo-ohms as discussed below. The expression of V rec is given by: where τ = R L C // and K is the initial condition constant such as V rec (0) = V built , considering t = 0 s corresponds to the zero-crossing moment of I peh . Equation (11) applies for V rec lower thanV OC . When V rec reachesV OC , it is regulated to this value by VR. Figure 7a shows V rec (t) for the FAR architecture (V rec| FAR ) simulated on half a period of I peh when applying a finite load R L at t = 0 s. The parameters of PT are: C peh = 100 nF and I peh = 20πe −6 A, and the excitation frequency is f ex = 100 Hz. This corresponds toV OC = 1 V. The load is R L = 48 kΩ, and K is set so that V rec (0) = K − R L τωÎ peh/(1+(τω) 2 ) =VOC ·C L/(C peh +C L ), which is the value of V built when V rec =V OC at the zero-crossing moment of I peh (See Section 2.2.2).
C peh I peh V rec C L R L In the Switch-only architecture, the evolution of V rec breaks down into two phases. First, its AD is "OFF" and C peh recharges, while in the meantime, C L discharges into R L . Therefore, in this phase, V rec and V peh evolve separately. On the one hand, the expression of V rec is where K SO is the initial value of V rec at the zero-crossing moment of I peh . On the other hand, the expression of V peh is The second phase of V rec for the Switch-only starts when AD is "ON" (i.e., V peh = V rec ). In this phase, the equivalent schematic of the Switch-only architecture is exactly the same as for the FAR (cf. Figure 6). Therefore, the expression of V rec is deduced from (11) but with an offset V o f f : This offset V o f f is induced by the decay of V rec during the first phase of Switch-only. Furthermore, just as for the FAR architecture, when V rec reachesV OC , it is regulated by VR. Figure 7b shows V rec for the Switch-only architecture (V rec| SO ) simulated with the same parameters as for the FAR simulation presented in Figure 7a. Note that, for Switch-only V rec (0) = K SO =V OC = 1 V.
To establish whether V o f f is positive or negative, i.e., which one yields the greater value (11 or 14, FAR or Switch-only), we first needed to find the moment t 1 when V rec of Switch-only caught up with V peh , which corresponds to the moment when AD turns "ON": ote: there is no analytic expression to solve (15). Therefore, to evaluate t 1 we need to apply a numerical method, such as Newton-Raphson ( Conejo and Baringo [30]). The value t 1 is then injected into (14) to determine V o f f so that Equations (12)-(14) yield the same value. Numerical simulations (Figure 8) reveal that, whatever the values of the parameters in (11) and (14), V o f f < 0, which means that for t ≥ t 1 , V rec| FAR > V rec| SO .
V off This result has significant consequences for the power efficiency of the systems as R L evolves. More specifically, from (11) we found the limit value R L lim of R L for which V rec| FAR reachedV OC at t = T/2. Applying R L lim in (14) yielded V rec| SO (T/2) <V OC . Since the value of V rec (T/2) set the initial conditions of V rec for the next half period of I peh , we verified that for R L = R L lim , the average value of V rec| SO decreased to compensate for the presence of R L while the average value of V rec| FAR remained constant. More generally, when R L < R L lim , V rec decreased in both architectures, V rec| SO decreased faster and, more importantly, stabilized to a lower value than V rec| FAR . Note that, for either architecture, V rec adjusted to a steady-state average value that depended on the amount of energy the harvester transfered from the PT to R L . This amount was lower in Switch-only because the power extraction phase was shorter than in FAR. Furthermore, the value of C L only affected the evolution speed of V rec when R L changed. The faster decreasing speed of V rec| SO cames from the smaller time constant R L C L when the ADwas "OFF" (see 12). The same reason explains why V rec| SO stabilized at a lower value than V rec| FAR . Figure 9 shows the numerical simulations of both architectures with R L = 48 kΩ and the same initial conditions as above. We noticed that V rec| SO stabilized around 3 mV below V rec| FAR . For power, FAR was also more efficient than Switch-only once V rec had been stabilized. Figure 10 shows the average power difference ∆P = P FAR − P SO between FAR and Switch-only. It is worth noticing that at t = 0 s, i.e., before and shortly after applying R L , Switch-only achieved slightly better power performance than FAR ( ∆P < 0 ). This was due to the fact that without R L , the FAR principle yielded lower average values of V rec . However, energy harvesting systems are not just meant to charge a storage device; they are intrinsically designed to supply energy to a load. Therefore, as shown here in the FAR implementation, there was a benefit in using voltage flip enhancement to improve power performance. Furthermore, we believe that combining the voltage flip enhancement principle to SSHI or SSHC might contribute to further improve the power performance under load constraint. But for the time being, this statement is based on theoretical assumptions and needs to be further investigated.

Prototype Design and Experimental Setup
We designed and tested a fully integrated prototype fabricated using AMS 0.35 µm High-Voltage CMOS technology. The circuit features all the blocks of the FAR architecture presented in Figure 2. The voltage supply was 3.3 V for AD, SD and VR and 1.2 V for CB and RO (Figure 2). Note that CB can be configured either in FAR or in Switch-only mode to allow performance comparison between both architectures.
To validate the voltage flip efficiency, we performed post-layout transistor-level 1 s transient simulations with C L = 10 µF and no load resistance R L . The model of the PT was based on the off-the-shelf device S118-J12S-1808YB by Piezo.com with C peh = 100 nF. We setÎ peh and f ex to achieve an open-circuit amplitudeV OC = 1 V. According to (3), this corresponds toÎ peh = 20πe −6 A 62.8 µA and f ex = 100 Hz. Since there was no R L , we set VR to regulate V rec toV OC , which corresponded to the theoretical maximum power efficiency, P recmax = 20 µW according to (10). Figure 11 shows the simulation results performed with Cadence ® . Note that C L was pre-charged with V rec = 0.7 V by a cold start circuit, not detailed here. Once V rec ≥ 0.7 V, the control block CB was activated and the the FAR system started to operate. The middle plot in Figure 11 shows that when V rec was regulated toV OC , V built was around 0.99 V (∆V 10 mV, see inset zoom view), which corresponded to 99% voltage flip efficiency. It also revealed the effect of the "ON" resistance of the non-ideal AD PMOS switch, which caused V peh = V sp to exceed V rec . The bottom plot focusedon a voltage flip sequence following a zero-crossing of I peh . The voltage flip duration was 64 µs. One noticed that the AD output signal AD comp returned to a low level almost instantly after the voltage flip operation started. This was due to a temporary increase in voltage at node V sp (Figure 2) caused by charge injection when switches SW 1 and SW 2 opened. Therefore, to prevent spurious behavior of the FAR, the signal AD ctrl was locked by the combinatorial OR function of AD comp , Φ 0 and Φ K . Signal AD comp went high again as C peh recharged during the sharing phase, and eventually returned to low leveld shortly after this phase was complete, as V peh = V sp increased and power extraction started. Figure 12 shows a micrograph of the ASIC and the test bench. For mechanical excitation, we used an LDS ® V400 series shaker by Brüel & Kjaer, driven by an AC power source 6813B by Agilent ® . The excitation signal was a 100 Hz sine waveform and the acceleration was set to getV OC = 1 V. For these experiments, the extracted energy was stored on a conventional capacitor C L = 100 µF. A LabVIEW ® platform performs shaker control and raw signal acquisition via a Tektronix ® TDS series digital oscilloscope. Figure 13 shows the measured waveforms of V peh and V rec corresponding to the above mentioned parameters and operating conditions of the FAR architecture. After the voltage flip operation, the voltage across C peh was V built = 0.864 V. This corresponded to 86.4% voltage flip efficiency, which was lower than the Cadence simulated value. There were two reasons for this. First, when operating the PT close to its mechanical resonance frequency (130 Hz), the strong coupling effect induced harmonic oscillations that prevented complete voltage flip, as can be seen in Figure13a. Second, the series resistance of the T-gate switches combined with the various interconnections between the test board and the PT induced a larger time constant. As can be seen on Figure 13b, this effect was greater during the sharing phase when the charge from C L transited through SW 3 and SW 2/3 , and the series resistance was thus larger than during the shorting phase. One solution to circumvent this issue was to extend the duration of the sharing phase, but this had only limited benefit because the deleterious effect of harmonic oscillations prevailed. We experimentally determined that a 32 µs sharing phase duration yielded optimal voltage flip efficiency. Note that with C L = 100 µF, the voltage ripple ∆V on V rec is negligible (i.e., below 1 mV). To evaluate the benefit of the proposed voltage flip enhancement principle on power efficiency, we measured the output power in both FAR and Switch-only mode. For this experiment, we applied a variable load resistance and disabled VR. Figure 14a shows the output power as a function of 1/R L . One can clearly see that FAR achieved better power performance as 1/R L increased and delivered around 100% more power than Switch-only for 1/R L 0.024 S (R L 41 kΩ). Yet, as demonstrated in Section 2.3.2 (see Figure 9), for a given value of R L , both architectures did not yield the same output voltage. Therefore, for a more realistic comparison, Figure 14b shows the output power as a function of V rec . For both architectures maximum power was achieved when V rec V OC . As mentioned in Section 2.3.2, Switch-only achieved slightly better performance than FAR with P SO max = 19.3 µW and P FAR max = 19.1 µW, respectively. Yet, for a given value of V rec <V OC , FAR delivered up to 20% more power than Switch-only. This result confirmed the theoretical demonstration (Section 2.3.2) that FAR achieved better power efficiency than Switch-only under load constraint. It is also worth pointing out that FAR kept operating, and the efficiency improvement ratio remained almost constant (around 20%), for V rec as low as 0.7 V, i.e., as the load constraint increased (when R L drained more current from C L ). Note that for V rec < 0.5 V, the ASIC was unable to work properly. Concerning absolute value, the measurements revealed that the power improvement of FAR over Switch-only was much more significant than the simulations presented in Figures 9 and 10. The reason is that FAR was more robust against circuit non-idealities than Switch-only, and particularly against the offset of the AD comparator, which can be as high as a few millivolts. Indeed, in FAR, during the sharing phase SW 3 shorted the inputs of the AD comparator and the voltage at node V sp was pre-charged to V rec . This caused the comparator to flip state shortly after the sharing phase had been completed, as mentioned in Section 2.2.3. Conversely, in Switch-only V peh first had to overcome the offset of the AD comparator before power extraction started. The influence of the offset was particularly important for large C L as a few millivolts difference between V rec and V peh may represent a large amount of charge and thus a large power difference. For the time being, this was the most tangible assumption, but further investigations are currently under way to gain a better understanding of this phenomenon.

Experimental Results
The maximum output power improving rate (MOPIR) (Ramadass and Chandrakasan [17], Chen et al. [21]) allows the comparison of FAR power performance with that of a conventional FBR. MOPIR = P FAR P FBR (16) where P FAR and P FBR are the output powers of FAR and FBR, respectively. The maximum output power of FBR is (Ramadass and Chandrakasan [17]) where V th is the diodes' threshold voltage. If we consider a conventional Schottky-diode based FBR with high-performance diodes having a low V th ()around 0.3 V), using a FBR under the same operating condition as the FAR yielded P FBR max = 1.6 µW. The MOPIR was thus around 11.94×. Table 2 compares the proposed FAR concept with some of the best results available in the recent literature. As mentioned in the introduction, discussing absolute raw performance was not the object of this paper. When considering the FAR as a stand-alone rectifier solution, the power efficiency was equivalent to Switch-only, which was much lower than the SSHI or SSHC systems referenced in the table. Hence, the PIC was lower compared to the state-of-the-art. Nevertheless, the FAR operated with an open circuit V OC of only 1 V while the latest systems usually have a larger V OC . Therefore, compared to a conventional diode-based FBR, the output power ratio of FAR was much higher, and above all, helped keep power efficiency as the load constraint increased.

Conclusions
This paper reported on a simple concept of voltage flip enhancement for piezoelectric energy harvesting. A thorough analysis of the power performance revealed that, besides the boost effect on the voltage flip, the FAR principle also helped improve the power efficiency of the PEH, especially as the load constraint increased. The FAR can be used as a fully integrated standalone rectifier solution, and is particularly well suited for low-voltage operation. Yet, it may also be considered as an additional boost solution to improve the performance of more a complex PEH architecture such as SSHI or SSHC. Experimental results performed on a CMOS prototype confirmed that, under load constraint, the FAR principle achieved better performance compared to Switch-only, and is more robust against circuit non-idealities. These conclusive results opened interesting research perspectives that we are currently working on, consisting of combining the FAR principle with SSHI or SSHC to improve both voltage flip and power efficiency. Funding: This research was funded by the Agence Nationale de la Recherche: ANR-18-CE09-0033.

Conflicts of Interest:
The authors declare no conflict of interest.