Advances in Low-Voltage Design Techniques for Scaled CMOS Technologies

Dear Colleagues,

The down scaling of CMOS technology has enabled the implementation of complex analog and digital functions on the same die. This has come with a progressive reduction of the supply voltage below 1 V to reduce the electric field within MOS devices. Even lower supply voltage may be requested for ultra-low-power systems, such as biomedical implantable/wearable electronic devices and energy-autonomous Internet of Things (IoT) nodes.

In this context, the design of integrated electronic systems represents a challenging task, especially for analog circuits, since the designer is asked to develop novel techniques and topologies to get a good level of performance while maintaining robustness and reliability in low-voltage low-power conditions.

The aim of this Special Issue is to attract researchers in the area of integrated circuits to highlight the recent advances in low-voltage design techniques. Both review articles, describing the state-of-the-art, and original research articles are welcome.

The topics to be covered in this Special Issue include, but are not limited to, the following:

• Conventional and nonconventional low-voltage analog and digital design techniques
• Theory, design, and new applications of sub-1-V analog and digital circuits
• Circuits for IoT nodes and implantable/wearable biomedical devices
• Low-voltage power-efficient analog-to-digital converters
• Circuits and systems for energy harvesting
• Power management of sub-1-V integrated digital and analog systems
• Time-based analog signal processing

Prof. Dr. Alfio Dario Grasso
Dr. Andrea Ballo
Editors

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