Search Results (51)

Feedthrough interference is inevitably introduced in MEMS gyroscopes due to non-ideal factors such as circuit layout design and fabrication processes, exerting non-negligible impacts on gyroscope performance. This study proposes a feedthrough suppression scheme for MEMS gyroscopes based on mixed-frequency excitation signals. Leveraging the quadratic relationship between excitation voltage and electrostatic force in capacitive resonators, the resonator is excited with a modulated signal at a non-resonant frequency while sensing vibration signals at the resonant frequency. This approach achieves linear excitation without requiring backend demodulation circuits, effectively separating desired signals from feedthrough interference in the frequency domain. A mixed-frequency excitation-based measurement and control system for MEMS gyroscopes is constructed. The influence of mismatch phenomena under non-ideal conditions on the control system is analyzed with corresponding solutions provided. Simulations and experiments validate the scheme’s effectiveness, demonstrating feedthrough suppression through both amplitude-frequency characteristics and scale factor perspectives. Test results confirm the scheme eliminates the zero introduced by feedthrough interference in the gyroscope’s amplitude-frequency response curve and reduces force-to-rebalanced detection scale factor fluctuations caused by frequency split variations by a factor of 21. Under this scheme, the gyroscope achieves zero-bias stability of 0.3118 °/h and angle random walk of 0.2443 °/h/√Hz. Full article

The miniaturization of sensors and non-contact measurement techniques is currently at the forefront of smart grid development. This paper proposes a miniature voltage sensor whose size is significantly reduced while maintaining large bandwidth and high linearity. To minimize the impact of environmental factors on measurement accuracy, a differential structure is utilized to optimize the sensor. The sensor is designed with a dual-channel measurement mode for both high-frequency and power-frequency signals, addressing issues of signal refraction and reflection due to impedance mismatch. COMSOL Multiphysics 6.2 is employed to simulate the sensor’s structural design and placement. Moreover, the experimental analysis of key parameters, such as parallel resistance and capacitance, identifies the optimal parameter combination for low-voltage distribution lines and cables of 10 kV and below. Experiments show that the voltage sensor’s bandwidth ranges from 30 Hz–200 kHz when measured through a frequency response analyzer. Finally, through the measurement carried out on the overhead line and cable, we evaluate the linearity of the sensor according to the experimental data. Specifically, the nonlinear errors of the voltage measurement for the overhead line and cable are 0.62% and 0.57%, respectively. Full article

For the double-sided inductor–capacitor–capacitor (DS-LCC) compensation topology, the parametric deviation of compensation elements results in the mismatch between the resonant frequency and operating frequency. Furthermore, this mismatch leads to the loss of the load-independent constant output characteristics. Therefore, an innovative design approach based on the reduction in the capacitance ratio is proposed to attain the load-independent constant current under the parametric deviation. With the presented method, simply by reducing the compensation capacitor ratio, the load-independent constant current output characteristics can be preserved, and fluctuations in the transmission gain caused by the parametric deviation are minimized. This implies that when the constant transmission gain is achieved by the frequency modulation (FM) control, the required FM range can be reduced. Finally, from the experimental results, in the load range of 3 Ω to 33 Ω, compared to the high capacitance ratio, the load-independent constant current characteristics can be maintained at the low capacitance ratio. In addition, without parametric deviation, the transmission efficiencies at different capacitance ratios are basically the same at 93.5% and 94.2%, respectively. However, the transmission efficiencies under different parametric deviations at the low capacitance ratio are 87.4% and 84.9%, but only 73.9% and 68.2% at the high capacitance ratio. Full article

Energy harvesting systems are becoming increasingly vital for sustainable power supply in Internet of Things (IoT) applications. These systems involve capturing and converting energy from environmental sources into electrical power. This paper presents a high-efficiency 5.8 GHz energy harvester for powering such devices, designed in a 65 nm pure CMOS process. The proposed design utilizes a metal-oxide-semiconductor field-effect-transistor-based Dickson charge pump energy harvester for high-frequency energy conversion. Simulation results are presented and discussed on the post-layout verified and extracted circuits with matching implemented to emulate the real-world testing scenarios. The design addresses challenges specific to high-frequency operation, including parasitic capacitances, frequency-dependent leakage currents, and impedance mismatches, ensuring optimal performance at higher frequencies. The evaluation focuses on key metrics such as output voltage and power conversion efficiency (PCE), with the harvester demonstrating an output voltage of 2.88 V and an efficiency of 82.94%. Full article

This paper presents a novel high-precision 11-bit single-slope/successive approximation register analog-to-digital converter (SS/SAR ADC) architecture specifically designed for CMOS image sensors (CISs). The proposed design solves critical challenges in conventional ADCs by utilizing only two reference voltages, thereby minimizing voltage mismatch and completely eliminating the need for complex switch arrays. This unique approach reduces the transistor count by 64 per column ADC, significantly enhancing area efficiency and circuit simplicity. Furthermore, a groundbreaking on-chip fine step range calibration technique is introduced to mitigate the impact of parasitic capacitance, ensuring the precise alignment between coarse and fine steps and achieving exceptional linearity. Fabricated using a 0.18-µm CMOS process, the ADC demonstrates superior performance metrics, including a differential nonlinearity (DNL) of −1/+1.86 LSB, an integral nonlinearity (INL) of −2.74/+2.79 LSB, an effective number of bits (ENOB) of 8.3 bits, and a signal-to-noise and distortion ratio (SNDR) of 51.77 dB. Operating at 240 kS/s with a power consumption of 22.16 µW, the ADC achieves an outstanding figure-of-merit (${\mathrm{FOM}}_W$) of 0.291 pJ/step. These results demonstrate the proposed architecture’s potential as a transformative solution for high-speed, energy-efficient CIS applications. Full article

A power-efficient 16-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. High-bit sampling makes the bridge capacitance in the digital-to-analog converter (DAC) a unit one, eliminating fractional capacitance mismatch. The high-precision comparator is composed of a four-stage preamplifier and a strong-arm latch, with auto-zeroing used to mitigate input offset further. Digital foreground calibration based on low-bit weight is implemented to correct DAC capacitance mismatch. The post-layout simulation results show that the core ADC achieves 95.61 dB SNDR and 105.1 dB SFDR with calibration, consuming 5.4 mW power under a 3.3 V supply voltage, corresponding to a Schreier figure of merit (FoM) of 175.3 dB. The ADC core area is 1.06 mm² in the 180 nm CMOS technology. Full article

In the planar-type InGaAs photodetector (PD) structure, a diffusion barrier has the effect of modifying the zinc diffusion profile in the interface between the cap and the absorption layer to improve device performance. In this work, an n-type In_0.83Ga_0.17As diffusion barrier layer (DBL) is employed between the In_0.83Al_0.17As cap layer and the low-doped In_0.83Ga_0.17As absorption layer of a lattice-mismatched metamorphic In_0.83Ga_0.17As PD. The device performance of the In_0.83Ga_0.17As PDs in terms of dark current, quantum efficiency, and capacitance were simulated and compared to experimental results. The effects of the thickness and doping concentration of the DBL on PD performance were analyzed and shown to be optimized at both 300 K and 200 K. Based on the simulation results, the electron concentration of the DBL is recommended to be $3\times {10}^{16}–5\times {10}^{16}$ cm⁻³ and a thickness of 0.1 μm is suggested. Full article

The capacitor mismatch among diverse defects caused by variations in the manufacturing process significantly affects the linearity of the capacitor array used to implement the capacitive digital-to-analog converter (CDAC) in the successive-approximation register (SAR) analog-to-digital converter (ADC). Accordingly, the linearity of the SAR ADC is limited by that of capacitor array, resulting in serious yield loss. This paper proposes an efficient foreground self-calibration technique to enhance the linearity of the SAR ADCs by mitigating the capacitor mismatch based on the split ADC architecture along with variable capacitors. In this work, two ADC channels (i.e., ADC1 and ADC2) for the split ADC architecture include their capacitive DACs (CDACs) whose binary-weighted capacitor arrays consist of variable capacitors. A charge-sharing SAR ADC is used for each ADC channel. In the normal operation mode, their digital outputs are averaged to be the final ADC output, as in a conventional split ADC. In the calibration mode, every single binary-weighted capacitor for the two ADCs is sequentially calibrated by making parallel or/and antiparallel connection among two or thee capacitors from the two channels. For instance, because the capacitors of the CDACs ideally exhibit the binary-weighted relation as $C_n=2\times C_{n-1}$, the variable capacitor $C_n$ of ADC1 can be updated to be closest to the sum of $C_{n-1}$ of ADC1 and $C_{n-1}$ of ADC2 for the calibration. For the process, the two capacitor arrays of the two ADCs can be reconfigured to be connected to each other, so that the $C_n$ of ADC1 can be connected with two of the $C_{n-1}$ of ADC1 and ADC2 in antiparallel. The two voltages at the top and the bottom plates of the CDAC are compared by a comparator of ADC1, and the comparison results are used to update $C_n$. This process is iterated, until $C_n$ is in agreement with the sum of two of $C_{n-1}$. Finally, all the capacitors can be calibrated in this way to have the binary-weighted relation. The simulation results based on the proposed work with a split SAR ADC model verified that the proposed technique can be practically used, by showing that the total harmonic distortion and the signal-to-noise-and-distortion ratio were enhanced by $21.8$ dB and $6.4$ dB, respectively. Full article

This paper introduces an innovative method for the analysis of alcohol–water droplets on a CMOS capacitive sensor, leveraging the controlled thermal behavior of the droplets. Using this sensing method, the capacitive sensor measures the total time of evaporation (ToE), which can be influenced by the droplet volume, temperature, and chemical composition. We explored this sensing method by introducing binary mixtures of water and ethanol or methanol across a range of concentrations (0–100%, with 10% increments). The experimental results indicate that while the capacitive sensor is effective in measuring both the total ToE and dielectric properties, a higher dynamic range and resolution are observed in the former. Additionally, an array of sensing electrodes successfully monitors the droplet–sensor surface interaction. However practical considerations such as the creation of parasitic capacitance due to mismatch, arise from the large sensing area in the proposed capacitive sensors and other similar devices. In this paper, we discuss this non-ideality and propose a solution. Also, this paper showcases the benefits of utilizing a CMOS capacitive sensing method for accurately measuring ToE. Full article

In a beamforming circuit for a modern broadband phased-array system, high accuracy and compactness have received sufficient attention as they are directly related to side lobe level and fabrication cost, respectively. In order to meet the low phase error required, this paper proposed an ultra-broadband 6-bit digital step switched-type attenuator (STA) with capacitive/inductive compensation networks. Compared to the conventional methods, the proposed technique employs an improved simplified T-structure with capacitive compensation networks, which simultaneously achieves low insertion loss and high-accuracy amplitude/phase control. In addition, on-chip level shifting circuit is integrated to avoid complex control schemes. The strategy of prioritizing return loss is adopted to alleviate the performance degradation caused by impedance mismatch after cascade. As a proof-of-principle demonstration, a wideband 6-bit STA with core area of only 0.5 mm × 1.8 mm was designed via 0.15-micrometer GaAs pHEMT technology. It exhibits ultra-broadband operation with a 31.5 dB amplitude tuning range and a 0.5 dB tuning step. The insertion loss of the reference state is 4–5.3 dB. The return loss is better than 15 dB for all the 64 states. The RMS amplitude and phase errors are less than 0.2 dB and 2° over the 10 to 20 GHz. Full article

The exceptional performance of the wireless power transfer (WPT) system hinges on its resonant state. However, the capacitance drift caused by manufacturing tolerance and temperature will result in a state of detuning. In this manuscript, a PWM-controlled switched impedance (PCSI) topology that can express inductive and capacitive is proposed to eliminate line mismatches resulting from the above factors. Firstly, the PCSI topology is introduced, and its placement is determined based on the characteristics of the inductor–capacitor–capacitor series (LCC-S) network. Secondly, the working principle of the proposed topology is introduced. Finally, the simulation and experimental results show that the system could be restored to its resonant state by adjusting the PCSI topology. Under different values of resonant capacitors, the PCSI topology enhances the output power of the system by 40 W~150 W compared to the previous state, and the efficiency is increased by 9~13%. Full article

Harmonic distortion is one of the dominant factors limiting the overall signal-to-noise and distortion ratio of seismic-grade sigma-delta MEMS accelerometers. This study investigates harmonic distortion based on the multiple degree-of-freedom model (MDM) established in our previous study. The main advantage of using an MDM is that the effect of finger flexibility on harmonic distortion is considered. Initially, the nonlinear relationship between the input acceleration and output signal is derived using the MDM. Then, harmonic distortion is simulated and described in terms of the nonlinear input–output relationship. It is found that finger flexibility and parasitic capacitance mismatch both decrease harmonic distortion. Finally, the experimental testing of harmonic distortion is implemented. By reducing the finger length to realize a higher stiffness and compensating for the parasitic capacitance mismatch, the total harmonic distortion decreases from −66.8 dB to −86.9 dB. Full article

This paper proposes a 10-bit 400 MS/s dual-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) immune to offset mismatch between channels. A novel comparator multiplexing structure is proposed in our design to mitigate comparator offset mismatch between channels and improve ADC dynamic performance. Compared to traditional TI-SAR ADC utilizing offset calibration technique, hardware and power consumption overhead are minimized in our design. In addition, a split capacitive digital-to-analog converter (CDAC) and a double-tail dynamic comparator using the clock decoupling technique were applied to eliminate comparator common mode input voltage shift, ensuring conversion accuracy and boosting speed. A 400 MS/s 10-bit dual-channel TI-SAR ADC with comparator multiplexing was designed in 40 nm CMOS and compared to the conventional one. The simulated ADC ENOB and SFDR with 6σ offset mismatch were improved from 5.0-bit and 32.2 dB to 9.7-bit and 77.2 dB, respectively, confirming the merits of the proposed design compared to current state-of-the-art works. Full article

This paper introduces a new high-performance successive approximation register (SAR) analog-to-digital converter (ADC) designed for high-speed and low-power wireless local area network (WLAN) applications using a SMIC 55 nm 1p8m CMOS process. The design employs several innovative techniques, including an improved bootstrap switch with high linearity, a 4-reference voltage method to minimize capacitive digital-to-analog converter (CDAC) mismatch, a kickback-canceling comparator to eliminate kick-back noise, and redundant design-assisted window-opening SAR logic to decrease conversion time. Experimental results reveal that the proposed ADC achieves an impressive signal-to-noise and distortion ratio (SNDR) of 55.3 dB and a spurious-free dynamic range (SFDR) of 66.6 dB at a sampling rate of 200 MHz with Nyquist frequency input while consuming a power of 2.8 mW at a 1.2 V power supply. This corresponds to a figure-of-merit (FoM) value of 29 fJ/conversion-step. Thanks to the incorporation of the 4-reference voltage method, the ADC demonstrates a significant area advantage compared to other designs with similar FOM values utilizing more advanced processes, occupying a mere 0.008 mm² of core area. Full article

Capacitive DACs (C-DACs) are widely used as stand-alone DACs or in an ADC as auxiliary DACs. An important performance metric of a C-DAC is its energy consumption and the linearity between the digital input and the analog output. In multi-bit C-DACs, the mismatch between the capacitors can degrade linearity, which can be important in high-resolution applications. In this work, we analyze the power consumption and linearity performance of a class of C-DACs called split-array C-DACs. We show that the simple element rotation technique, which is widely used to suppress the mismatch error of DACs, cannot be used with the power-efficient three-level switching scheme to effectively suppress the mismatch error. Then, we propose a switching scheme which can be used with the power efficient three-level switching and can suppress the in-band mismatch error effectively. Full article