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JLPEA
Special Issues
Analog/Mixed-Signal Integrated Circuit Design
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Analog/Mixed-Signal Integrated Circuit Design

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: 30 April 2025 | Viewed by 4340

Special Issue Editor

Dr. Xinpeng Xing

E-Mail Website
Guest Editor
School of Integrated Circuits, Sun Yat-sen University, Shenzhen 518107, China
Interests: mixed-signal IC; ADC; DAC; TDC; analog front-end

Special Issue Information

Dear Colleagues,

Analog/mixed-signal integrated circuits (ICs) play critical roles in cutting-edge scientific research and engineering applications, such as artificial intelligence, quantum computing, brain–machine interface (BMI), 5G/6G and satellite communications, electric vehicle, etc.  The massive channel integration of analog/mixed-signal circuits is always required in applications with large arrays; furthermore, the low-power design of analog/mixed-signal IC is key for a power-efficient system, which is driven by global carbon reduction targets. All these requirements posed by applications set new difficulties for analog/mixed-signal IC design. This Special Issue, entitled “Analog/Mixed-Signal Integrated Circuit Design”, is being launched to discuss the emerging analog/mixed-signal IC design challenges and demonstrate innovative designs in specific applications. Contributions should include systematic circuit design considerations and at least transistor-level simulation results; measurement results based on tapeout are preferred. The topic of this Special Issue includes but is not limited to the following:

  • Analog IC, including operational amplifiers, bandgap references, comparators, biomedical AFE, and sensor interfaces;
  • Data converter, including ADC, DAC, TDC, DTC, and CDC;
  • Power management, including DC-DC, LDO, and energy harvesting;
  • Clock generation, including oscillator, VCO, PLL, clock data recovery, and Serdes.

Dr. Xinpeng Xing
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • mixed-signal IC
  • analog IC
  • data converter
  • power management
  • clock generation
  • biomedical IC
  • sensor interface
  • low power

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Published Papers (3 papers)

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Research

16 pages, 3143 KiB  
Article
A Low-Power 5-Bit Two-Step Flash Analog-to-Digital Converter with Double-Tail Dynamic Comparator in 90 nm Digital CMOS
by Reena George and Nagesh Ch
J. Low Power Electron. Appl. 2024, 14(4), 53; https://doi.org/10.3390/jlpea14040053 - 4 Nov 2024
Viewed by 837
Abstract
Low-power portable devices play a major role in IoT applications, where the analog-to-digital converters (ADCs) are very important components for the processing of analog signals. In this paper, a 5-bit two-step flash ADC with a low-power double-tail dynamic comparator (DTDC) using the control [...] Read more.
Low-power portable devices play a major role in IoT applications, where the analog-to-digital converters (ADCs) are very important components for the processing of analog signals. In this paper, a 5-bit two-step flash ADC with a low-power double-tail dynamic comparator (DTDC) using the control switching technique is presented. The most significant bit (MSB) in the proposed design is produced by only one low-power DTDC in the first stage, and the remaining bits are generated by the flash ADC in the second stage with the help of an auto-control circuit. A control circuit produced reference voltages with respect to the control input and mid-point voltage (Vk). The proposed design and simulations are carried out using 90 nm CMOS technology. The result shows that the peak differential non-linearity (DNL) and integral non-linearity (INL) are +0.60/−0.69 and +0.66/−0.40 LSB, respectively. The signal-to-noise and distortion ratio (SNDR) for an input signal having a frequency of 1.75 MHz is found to be 30.31 dB. The total power consumption of the proposed design is significantly reduced, which is 439.178 μW for a supply voltage of 1.2 V. The figure of merit (FOM) is about 0.054 pJ/conversion step at 250 MS/s. The present design provides low power consumption and occupies less area compared to the existing works. Full article
(This article belongs to the Special Issue Analog/Mixed-Signal Integrated Circuit Design)
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14 pages, 7528 KiB  
Article
A Power-Efficient 16-bit 1-MS/s Successive Approximation Register Analog-to-Digital Converter with Digital Calibration in 0.18 μm Complementary Metal Oxide Semiconductor
by Xinyuan He, Weifeng Qiao, Xinpeng Xing and Haigang Feng
J. Low Power Electron. Appl. 2024, 14(2), 32; https://doi.org/10.3390/jlpea14020032 - 4 Jun 2024
Viewed by 1317
Abstract
A power-efficient 16-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. High-bit sampling makes the bridge capacitance in the digital-to-analog converter (DAC) a unit one, eliminating fractional capacitance mismatch. The high-precision comparator is composed of a four-stage preamplifier [...] Read more.
A power-efficient 16-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. High-bit sampling makes the bridge capacitance in the digital-to-analog converter (DAC) a unit one, eliminating fractional capacitance mismatch. The high-precision comparator is composed of a four-stage preamplifier and a strong-arm latch, with auto-zeroing used to mitigate input offset further. Digital foreground calibration based on low-bit weight is implemented to correct DAC capacitance mismatch. The post-layout simulation results show that the core ADC achieves 95.61 dB SNDR and 105.1 dB SFDR with calibration, consuming 5.4 mW power under a 3.3 V supply voltage, corresponding to a Schreier figure of merit (FoM) of 175.3 dB. The ADC core area is 1.06 mm2 in the 180 nm CMOS technology. Full article
(This article belongs to the Special Issue Analog/Mixed-Signal Integrated Circuit Design)
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9 pages, 2773 KiB  
Communication
A Compact 0.73~3.1 GHz CMOS VCO Based on Active-Inductor and Active-Resistor Topology
by Chatrpol Pakasiri, Ke-Chung Hsu and Sen Wang
J. Low Power Electron. Appl. 2024, 14(2), 18; https://doi.org/10.3390/jlpea14020018 - 25 Mar 2024
Viewed by 1539
Abstract
In this paper, a wideband VCO that covers popular Long-Term Evolution (LTE) 0.7 GHz and LTE 2.6 GHz frequencies is designed and developed in a standard 0.18 μm CMOS process. The VCO utilizes active inductors to achieve coarse-tuning of the inductance and a [...] Read more.
In this paper, a wideband VCO that covers popular Long-Term Evolution (LTE) 0.7 GHz and LTE 2.6 GHz frequencies is designed and developed in a standard 0.18 μm CMOS process. The VCO utilizes active inductors to achieve coarse-tuning of the inductance and a compact chip area. Moreover, an active feedback resistor is introduced into the active inductor for fine-tuning of the inductance. The feedback resistor also affects the equivalent resistance of the active inductor; therefore, wide inductance tuning and low power consumption can be obtained by optimizing the resistor. The core area of the fabricated CMOS chip is merely 0.046 mm2, excluding all testing pads. With a 6.7~10.1 mW DC consumption, the measured oscillation frequencies range from 0.73 GHz to 3.1 GHz, which demonstrates a 123.8% tuning range. At the frequencies of interest, the measured phase noises are from −80.7 to −84.5 dBc/Hz at a 1 MHz offset frequency. Full article
(This article belongs to the Special Issue Analog/Mixed-Signal Integrated Circuit Design)
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